US20020076902A1 - Low temperature silicon wafer bond process with bulk material bond strength - Google Patents
Low temperature silicon wafer bond process with bulk material bond strength Download PDFInfo
- Publication number
- US20020076902A1 US20020076902A1 US09/189,276 US18927698A US2002076902A1 US 20020076902 A1 US20020076902 A1 US 20020076902A1 US 18927698 A US18927698 A US 18927698A US 2002076902 A1 US2002076902 A1 US 2002076902A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- wafer
- wafers
- energy
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 66
- 229910052710 silicon Inorganic materials 0.000 title claims description 66
- 239000010703 silicon Substances 0.000 title claims description 66
- 230000008569 process Effects 0.000 title description 11
- 239000013590 bulk material Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 93
- 235000012431 wafers Nutrition 0.000 claims description 188
- 238000000137 annealing Methods 0.000 claims description 35
- 230000002209 hydrophobic effect Effects 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000010979 ruby Substances 0.000 claims description 4
- 229910001750 ruby Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 239000007943 implant Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910008045 Si-Si Inorganic materials 0.000 description 2
- 229910006411 Si—Si Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005661 hydrophobic surface Effects 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000002277 temperature effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002808 Si–O–Si Inorganic materials 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000009658 destructive testing Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000002223 garnet Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-NJFSPNSNSA-N oxygen-18 atom Chemical compound [18O] QVGXLLKOCUKJST-NJFSPNSNSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229940095676 wafer product Drugs 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Definitions
- the present invention relates to a method for bonding semiconductor articles and to a semiconductor article comprising bonded semiconductor articles.
- VLSI very large scale integrated circuits
- the VLSI circuits are used in a solid state architecture divisible into two components—an instruction processor that supervises the order and decoding of instructions to be executed by the circuit and a data processor which performs the operations prescribed by the instructions on data.
- This complex circuitry has required multiple levels of circuit interconnects positioned vertically, as well as horizontally, over several wafer layers.
- the layers are fabricated to perform functions such as conductors, semiconductors or insulators.
- the layers have been typically formed by deposition, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).
- CVD chemical vapor deposition
- PVD physical vapor deposition
- the complex circuitry has been fashioned from the layers utilizing sophisticated photo masking techniques.
- One type of layer arrangement which has use in fabricating semiconductor devices, such as VLSI circuits, is a silicon layer positioned on an insulator (SOI) layer. This arrangement has been made by converting a top layer of a silicon wafer with a heavy oxygen implant to form an oxide. An epitaxial layer is grown on top of the oxide.
- SOI insulator
- the SOI arrangement has also been made by bonding silicon wafers to each other. Bonded wafers have been fabricated to a thickness of five microns, with a resistivity in a range of 6 to 8 ohm-cm.
- the SOI structure permits layers of a semiconductor to be stacked using at least one insulating layer, a layer that bonds the layers together, and conductive interconnects or vertical busses extending through the insulating layer that are made utilizing a polymeric material such as an adhesive.
- the annealed, bonded silicon wafers have been used to fabricate devices such as p-I-n diodes, power devices and micro mechanical structures.
- the annealed, bonded wafers have also been used to replace epitaxy fabrication.
- the annealed, bonded wafers have a versatility of thickness range which was not present in epitaxy fabrication in structures such as SOI structures.
- Hydrophilic wafers had three to five monolayers of water and hydroxyl groups that terminated the silicon oxide layer formation at low temperature. With heating, the water groups dissociated, leading to the formation of additional silicon oxide. The hydroxyl groups subsequently disappeared resulting in the formation of Si—O—Si bridging linkages across the two surfaces of two wafers.
- the fabrication technique of silicon wafer bonding and annealing has been confined to early stages of silicon wafer fabrication.
- the annealing is performed prior to any circuit or film fabrication. This limitation is necessary because of the high temperature required to anneal the wafers to each other.
- the annealing temperature range is high enough to damage or destroy elements or films of any integrated circuit that might be positioned on the wafers.
- Embodiments of the present invention comprise a method for bonding one semiconductor surface to a second semiconductor surface.
- the method includes providing an article that has a semiconductor surface.
- the semiconductor surface of the article is contacted to a second semiconductor surface of a second article.
- the semiconductor surfaces are annealed with a pulsed energy source that imparts energy which is confined substantially to the semiconductor surfaces of each article and which is of such a short duration that only the semiconductor surfaces to be bonded are raised to the necessary annealing temperatures leaving opposite semiconductor surfaces at a temperature near the ambient temperature.
- the annealed surfaces are then contacted to each other and bonded to each other.
- the present invention also includes a semiconductor device comprised of two or more bonded semiconductor wafers.
- the bond of the semiconductor wafers is substantially free of defects. Any high temperature effects are confined to a region near the surfaces of the semiconductor wafers which have been annealed.
- the present invention additionally includes a first silicon wafer and a second silicon wafer which is annealed and then bonded to the first silicon wafer.
- the second silicon wafer includes an element which is subject to change at the semiconductor annealing temperature. The element is kept free from any changes due to high temperature exposure as a result of the pulsed annealing method employed.
- FIG. 1 is an exploded perspective view of two wafers that are annealed to make the semiconductor device of the present invention.
- FIG. 2 is a perspective view of one embodiment of the semiconductor device of the present invention.
- FIG. 3 is a cross-sectional view of one embodiment of the semiconductor device of the present invention.
- FIG. 4 is a cross-sectional view of one other embodiment of the semiconductor device of the present invention, the embodiment including an element changed at an annealing temperature of the semiconductor.
- FIG. 5 is a perspective view of the semiconductor mounted for annealing by laser-treatment.
- FIG. 6 is a perspective view of the semiconductor mounted for a laser raster scan.
- FIG. 7 is a top view of a laser raster scan.
- FIG. 8A is a side view of a device for bonding two semiconductor wafers to each other.
- FIG. 8B is a side view of the device of FIG. 8A bonding the two semiconductor wafers to each other.
- FIG. 9 is a top view of a device for separating bonded wafers.
- FIG. 10 is a cross-sectional view of bonded wafers with an epitaxial layer.
- FIG. 11A is a cross-sectional view of a bonded wafer layer of FIG. 10 with an ion implant wherein the implant is positioned within the layer.
- FIG. 11B is a cross-sectional view of a bonded wafer layer of FIG. 10 with an ion implant wherein the implant substantially traverses the layer.
- FIG. 12 is a cross-sectional view of a bonded wafer with a P-N junction.
- FIG. 13 is a cross-sectional view of a bonded wafer that comprises several layers.
- the terms, “chip”, “wafer”, and “substrate” include any structure having an exposed surface of semiconductor material with which to form integrated circuit (IC) structures. These terms are also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon.
- the terms include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures known in the art.
- the term “conductor” is understood to include semiconductors, and the term “insulator” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following description is, therefore, not to be taken in a limiting sense.
- the method of the present invention for annealing and bonding one silicon wafer, such as is illustrated at 10 in FIG. 1 to another silicon wafer 12 , to form a single bonded silicon wafer, illustrated in a perspective view at 14 in FIG. 2 and in cross-section in FIG. 3, includes providing two silicon wafers 10 and 12 , and annealing designated annealing surfaces 16 and 18 of the wafers 10 and 12 with a high intensity, short duration laser pulse in a manner that heats the designated-annealing surfaces 16 and 18 to a temperature of at least about 500° C. within about 20 nanoseconds, while maintaining the remaining wafer mass and opposing non-annealed surfaces 20 and 22 at a temperature that is no greater than about 15 to 25° C. above room temperature.
- the annealed surfaces 16 and 18 are contacted and bonded to each other.
- the present invention also includes a semiconductor device that comprises at least two silicon wafers 10 and 12 , annealed and then bonded to each other, wherein at least one of the wafers has an integrated circuit such as is shown at 23 in FIGS. 2 and 3.
- the bond 24 formed by contacting surfaces of the two wafers 10 and 12 after the surfaces have been annealed, is substantially free of defects.
- One embodiment of the semiconductor device illustrated in cross-section at 30 in FIG. 4, further includes a layer or segment 26 produced by metallization, utilizing a metal such as aluminum, copper or other material such as polysilicon, that is positioned adjacent to silicon 34 .
- the aluminum or other metal is layered over or within a silicon wafer 36 .
- the aluminum or other metal displays no high temperature effects even though the annealing bond temperature utilized in the method of the present invention would be expected to cause aluminum and silicon to dissolve into each other. The dissolution is expected because a eutectic point for aluminum or other metal and silicon occurs at 450° C.
- the method of the present invention imparts to semiconductor device manufacture, a versatility not heretofore possible.
- a semiconductor manufacturer can fabricate desired circuits on different wafers and then bond and anneal the wafers together without damaging or negatively impacting the circuits.
- circuit arrays may be mass produced on wafers and then combined with a variety of other, desired arrays on other wafers through the annealing and bonding process.
- This versatility is a great improvement over the conventional semiconductor fabrication methods which require a manufacturer to either perform the wafer bonding prior to circuit fabrication or to risk the occurrence of undesirable changes in a circuit as a result of exposure by the circuit to the elevated temperature of bonding.
- the silicon wafers provided in the method of the present invention are, in one embodiment, circular in shape with a diameter of about four inches. Wafers with other diameters or with other symmetries with other dimensions may also be suitable for use. Silicon constructions other than wafers are also suitable for use in the method of the present invention. It is also contemplated that semiconductor materials other than silicon may be usable in the method of the present invention, such as gallium arsenide or germanium.
- the silicon wafers are dipped in a dilute hydrofluoric acid (HF) solution in order to remove any native silicon oxide from the wafer surfaces to be bonded.
- HF dilute hydrofluoric acid
- the surfaces are rendered hydrophobic by replacement of oxygen from the silicon oxide on the wafer surface with hydrogen from the HF.
- the wafers with hydrophobic surfaces are then, in one embodiment, initially bonded to each other at room temperature and atmospheric pressure.
- the bonding is performed by contacting the wafers to each other in an environment free of dust or other airborne particles or vapors.
- the bonding process illustrated in one embodiment in FIGS. 8A and 8B, employs a spinner apparatus 200 and wafers 202 and 204 positioned on the spinner apparatus 200 by contacts 206 and 208 .
- the wafers 202 and 204 are initially spun under a low intensity infrared lamp 210 at a temperature that is less than approximately 80° C. After spinning, the wafers 202 and 204 are contacted together and pinched by a pinching mechanism 212 . This initial bonding is principally due to van der Waals forces.
- the bonded wafers are then transferred to an ultra-high vacuum (UHV) chamber which is pumped down to about 3 ⁇ 10 ⁇ 9 Torr.
- UHV ultra-high vacuum
- the bonded wafers are separated into two wafers by a separating mechanism such as is illustrated at 300 in FIG. 9.
- the separating mechanism 300 includes three wedges 302 , 304 and 306 , positionable between the wafers at a rim of each wafer. The separated wafers are observable by a camera transmission from within the vacuum chamber.
- the wafers are stored in an ultra clean environment prior to introduction into the vacuum chamber. These wafers do not undergo an initial bonding step.
- the purpose of the wafer bonding is to retain cleanliness of wafer surfaces that are to be annealed. If the cleanliness can be maintained without bonding, then it is not required that the wafers be initially bonded to each other.
- the wafer surfaces 16 and 18 that had been bonded to each other are exposed to energy from a laser pulse such as is illustrated for wafer surface 16 in FIG. 5.
- This exposure occurs in the vacuum chamber.
- Wafer surfaces 16 and 18 are sequentially exposed to energy from laser 38 .
- the laser pulse sequentially elevates the temperature of the surfaces 16 and 18 to a temperature of about 800° C. At this temperature and energy level, hydrogen is driven from the hydrophobic wafer surfaces 16 and 18 .
- the depth of the wafer thickness which is exposed to the laser energy and which is at a temperature of about 800° C. is no more than about 0.25 microns. Energy as manifested by an elevated temperature is substantially confined to the surface of the wafer.
- a pulsed energy source such as a pulsed laser is preferred because a laser operating in a pulsed mode can instantaneously heat an area of a wafer without influencing the underlying substrate.
- heating with a pulsed laser causes substantially no mechanical damage to the wafer because the thermal relaxation time of the pulsed laser is negligibly small as compared to the reaction time of a mechanical stress such as thermal expansion.
- the pulsed energy source should not be of a magnitude that is so high as to cause the silicon material or other semiconductor material to evaporate.
- the pulsed energy source must be of a magnitude to elevate the temperature to a range of 500 to 800° C.
- the annealing energy is generated by a q-switched ruby laser, producing a wavelength of 0.69 microns.
- the peak power required is about 10 8 watts/cm 2 .
- this energy corresponds to an incident optical pulse energy of approximately 243 joules.
- One other type of laser that may be used in the method of the present invention is a frequency doubled Neodymium doped Yittrium Aluminum Garnet (Nd/YAG) laser emitting 0.53 microns wavelength.
- Nd/YAG Neodymium doped Yittrium Aluminum Garnet
- a laser emitting light within the green spectrum, near the blue spectrum is suitable for use in the present invention. Because the absorption coefficient in silicon increases at shorter wavelengths, a decrease in the required pulse power and energy can be realized by choosing a shorter wavelength laser such as the ruby laser described, or the frequency doubled, Nd/YAG laser, described above.
- energy sources other than pulsed optical energy may be used in the method of the present invention.
- These other energy sources include pulsed ion beam, pulsed x-ray beam and others. These other energy sources have the similar pulse width and energy as is described for laser beam energy.
- This annealing energy and laser source is optimal for the hydrophobic wafer surface because under the process conditions, the optical properties of the silicon are such that absorption coupling to the incident radiation is appreciably greater than for example, silicon dioxide. As a consequence, wafer material opposing the laser-treated surfaces 16 or 18 remains relatively cool.
- the required pulse energy of a laser such as a q-switched ruby laser can be reduced by a factor of ten.
- This operation is performed at the expense of stepping the annealing laser beam 10 to 20 times across the wafer surface.
- the temperature rise of the surface opposite the surface illuminated with the full 243 joule pulse is about 15° C.
- This method embodiment of illuminating a fraction of a wafer surface area requires that the wafer surface area be capable of being scanned.
- the wafer 101 is mounted on a stage 100 , such as is illustrated in FIG.
- a scanning system 104 is comprised of a laser 106 , a multifaceted mirror 108 and focusing optics 110 .
- the beam 102 from the laser 106 is directed toward the multifaceted mirror 108 which rotates clockwise.
- the beam 102 is reflected toward the wafer 101 through the focusing optics 110 .
- the beam 102 impinges the surface of the wafer 101 and moves laterally across the wafer 101 as shown at 112 in FIG. 7.
- the mirror 108 rotates in concert with the movement of the wafer 101 which results in the wafer being raster scanned as is shown in FIG. 7.
- the wafer 10 is fixed and the laser beam is collimated and reflected by x and y galvanometer-controlled mirrors.
- the laser beam is focused by lenses such as are shown at 40 and 42 in FIG. 5 to impinge in a raster x and y movement across the wafer 10 .
- An evolution of hydrogen gas resulting from driving hydrogen from the hydrophobic surfaces of the wafers increases pressure in the vacuum chamber to about 10 ⁇ 6 Torr. After the annealing step, the vacuum pressure in the vacuum chamber was decreased to approximately 3 ⁇ 10 ⁇ 9 Torr. The vacuum is of a magnitude that removes debris from the silicon surface formed during the annealing step.
- Laser annealed surfaces 16 and 18 are brought together and pressed in a manner wherein force is concentrated in the center of the wafers 10 and 12 to initiate a contact 26 which chemically bonds the wafers at 24 .
- the contact produces a bonding wave over the designated annealing surface of the wafer.
- the interface 24 between the two wafers is bonded together by Si—Si bonds.
- the bond strength is typical of bulk silicon.
- Process variables such as laser wavelength, laser output in joules, and vacuum magnitude are adjustable with experimentation in order to optimize the method of the present invention, by experimentation.
- wafers made under one set of identified process parameters are tested for bond strength and bond flaws. The tests are destructive tests. In one test, bonded wafers are pulled apart. In another test, bonded wafers are sectioned and are examined for flaws. Once optimal process variables are identified through fabrication and destructive testing, only a small percentage of the bonded wafers formed are checked for compliance.
- the bonded wafers produced by the method of the present invention may be fabricated for silicon-on-insulator, SOI, processes.
- a bonded wafer 500 is etched, preferentially, to pattern a thin epitaxial layer 502 above a bonded region 505 .
- the epitaxial layer 502 may be used for fabrication of CMOS or high voltage devices.
- the bonded wafer 500 also includes silicon layers 507 and 509 adjacent to the bonded region 505 .
- the bonded wafer 500 also includes an insulating oxide layer 504 adjacent to the silicon layer 509 .
- the insulating oxide layer 504 is formed in a silicon substrate by ion implantation 506 , as is shown schematically for layer 504 in FIGS. 11A and 11B. Ion implants 506 in FIG. 11A are positioned within the layer 504 while ion implants 506 traverse the layer 504 in FIG. 11B.
- the wafer bonding process may be used to produce silicon wafers bonded to germanium to form sensors or fiber optic elements to electronic circuit interfaces. Silicon based circuits may also be integrated with gallium arsenide based circuits or lasers. With this bonding, the non-silicon wafer may be coated with a diffusion barrier such as silicon dioxide or a ceramic or tungsten. Once oxide is stripped from the silicon wafer, the wafer surface is annealed with a laser. The two wafers are clamped together to create a bond. This bonding process embodiment may be used to make a device such as a microminiature, electric-to-fluidic valve.
- the method of the present invention produces bonded wafers that are free from an oxide layer formed at the junction of the wafers.
- the benefit of this bonded wafer product is that it can be used in the manufacture of a device with a NMOS transistor and a PMOS transistor with minimal risk of “latch-up.”
- the localized annealing of the method of the present invention permits fabrication of devices with elements that are susceptible to damage at elevated temperatures because the elevated temperatures are restricted to the wafer surfaces.
- the wafer bonding process of the present invention may be used to bond a p type wafer such as is shown at 450 in FIG. 12, with an n type wafer 452 to form a P-N junction 454 .
- a deep P-N junction can be provided by selecting wafers having substantially the same crystallographic orientation and opposite conductivity types of desired dopant concentrations. The orientations of the two wafers are aligned within approximately one degree.
- One other type of SOI device illustrated at 550 in FIG. 13 that can be prepared with the method of the present invention includes several layers 554 and 556 below a top silicon layer 552 .
- These layers 554 and 556 may include silicon nitride, diamond, polycrystalline silicon, a metallic interlayer and others.
- the top silicon layer 552 is bonded to a silicon wafer 553 at 555 .
- the bonded wafers may be used to fabricate a single chip with multiple devices integrated within the chip.
- the bonded wafers permit improved device design for devices such as surface emitting lasers and light emitting diodes. These devices and device features include insulators hardened by radiation for increased radiation tolerance in military and space IC applications.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
- The present invention relates to a method for bonding semiconductor articles and to a semiconductor article comprising bonded semiconductor articles.
- An increasing complexity of circuitry fabricated on and within semiconductor wafers has required greater complexity in the vertical structure of semiconductor wafers. For instance, early bipolar semiconductor devices were comprised of only two layers, typically deposited by chemical vapor deposition (CVD). These layers included an epitaxial layer and, for silicon wafers, a silicon dioxide passivation layer. Early metal-oxide-semiconductor (MOS) devices had only one silicon dioxide layer.
- In contrast, more contemporary devices are constructed by utilizing a variety of very large scale integrated circuits (VLSI). The VLSI circuits are used in a solid state architecture divisible into two components—an instruction processor that supervises the order and decoding of instructions to be executed by the circuit and a data processor which performs the operations prescribed by the instructions on data. This complex circuitry has required multiple levels of circuit interconnects positioned vertically, as well as horizontally, over several wafer layers. The layers are fabricated to perform functions such as conductors, semiconductors or insulators. The layers have been typically formed by deposition, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The complex circuitry has been fashioned from the layers utilizing sophisticated photo masking techniques.
- One type of layer arrangement which has use in fabricating semiconductor devices, such as VLSI circuits, is a silicon layer positioned on an insulator (SOI) layer. This arrangement has been made by converting a top layer of a silicon wafer with a heavy oxygen implant to form an oxide. An epitaxial layer is grown on top of the oxide.
- The SOI arrangement has also been made by bonding silicon wafers to each other. Bonded wafers have been fabricated to a thickness of five microns, with a resistivity in a range of 6 to 8 ohm-cm. The SOI structure permits layers of a semiconductor to be stacked using at least one insulating layer, a layer that bonds the layers together, and conductive interconnects or vertical busses extending through the insulating layer that are made utilizing a polymeric material such as an adhesive.
- The annealed, bonded silicon wafers have been used to fabricate devices such as p-I-n diodes, power devices and micro mechanical structures. The annealed, bonded wafers have also been used to replace epitaxy fabrication. The annealed, bonded wafers have a versatility of thickness range which was not present in epitaxy fabrication in structures such as SOI structures.
- With silicon wafer bonding and annealing, two flat silicon wafers, which are particle-free, are contacted to each other and bond with each other, chemically and physically. The wafer contact and physical bonding occur at ambient room temperature. The physically bonded wafers are annealed at an elevated temperature in order to increase bond strength by imparting a chemical bond to the wafers.
- Q.-Y. Tong et al., in an article entitled “Hydrophobic Silicon Wafer Bonding” inApplied Phys. Lett., 64, No. 5, on Jan. 31, 1994, at pages 625 to 627, quantified the bond strength of wafers which had been bonded to each other at room temperature and annealed at an elevated temperature. Tong et al. showed that the bond strength increased by about two orders of magnitude from room temperature to 1100° C. Tong et al. studied both hydrophilic wafers and hydrophobic wafers and concluded that bonded hydrophobic wafers displayed superior performance, despite hydrogen bubble generation at the interface of the two bonded wafers. Tong et al. found that the bond energy at the wafer interface approached the fracture energy of bulk silicon at 700° C. and higher temperatures.
- Gosele et al. in an article, “Self-Propagating Room Temperature Silicon Wafer Bonding in Ultrahigh Vacuum,” inAppl. Phys. Lett. in volume 67, No. 24, of Dec. 11, 1995 at pages 3614 to 3616, described a technique for minimizing the hydrogen bubble generation. Gosele et al. studied wafer bonding under high vacuum conditions. Gosele et al. demonstrated that four inch diameter hydrophobic wafers that were separately annealed at 600° to 800° C. in a vacuum to drive off hydrogen from the silicon surfaces when bonded at room temperature in vacuum achieved a uniform bubble-free bonded surface with a bond interface energy of bulk silicon.
- The M. K. Weldon reference, “Physics and Chemistry of Silicon Wafer Bonding Investigated by Infrared Absorption and Spectroscopy,”J. Vac. Sci. Technol. B 14(4), July/August 1996, pp. 3095-3105, described the surface phenomena of annealed silicon wafer surfaces. Wafers considered were hydrophilic wafers and hydrophobic wafers. Weldon et al. observed a shift in Si—H stretching frequency of bonded hydrophobic wafers due to van der Waals attraction. Hydrogen was driven off during annealing at high temperatures and Si—Si bonds were formed between the surfaces of the two annealed wafers.
- Hydrophilic wafers had three to five monolayers of water and hydroxyl groups that terminated the silicon oxide layer formation at low temperature. With heating, the water groups dissociated, leading to the formation of additional silicon oxide. The hydroxyl groups subsequently disappeared resulting in the formation of Si—O—Si bridging linkages across the two surfaces of two wafers.
- The fabrication technique of silicon wafer bonding and annealing has been confined to early stages of silicon wafer fabrication. In particular, the annealing is performed prior to any circuit or film fabrication. This limitation is necessary because of the high temperature required to anneal the wafers to each other. The annealing temperature range is high enough to damage or destroy elements or films of any integrated circuit that might be positioned on the wafers.
- Embodiments of the present invention comprise a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing an article that has a semiconductor surface. The semiconductor surface of the article is contacted to a second semiconductor surface of a second article. The semiconductor surfaces are annealed with a pulsed energy source that imparts energy which is confined substantially to the semiconductor surfaces of each article and which is of such a short duration that only the semiconductor surfaces to be bonded are raised to the necessary annealing temperatures leaving opposite semiconductor surfaces at a temperature near the ambient temperature. The annealed surfaces are then contacted to each other and bonded to each other.
- In another embodiment, the present invention also includes a semiconductor device comprised of two or more bonded semiconductor wafers. The bond of the semiconductor wafers is substantially free of defects. Any high temperature effects are confined to a region near the surfaces of the semiconductor wafers which have been annealed.
- In one other embodiment, the present invention additionally includes a first silicon wafer and a second silicon wafer which is annealed and then bonded to the first silicon wafer. The second silicon wafer includes an element which is subject to change at the semiconductor annealing temperature. The element is kept free from any changes due to high temperature exposure as a result of the pulsed annealing method employed.
- FIG. 1 is an exploded perspective view of two wafers that are annealed to make the semiconductor device of the present invention.
- FIG. 2 is a perspective view of one embodiment of the semiconductor device of the present invention.
- FIG. 3 is a cross-sectional view of one embodiment of the semiconductor device of the present invention.
- FIG. 4 is a cross-sectional view of one other embodiment of the semiconductor device of the present invention, the embodiment including an element changed at an annealing temperature of the semiconductor.
- FIG. 5 is a perspective view of the semiconductor mounted for annealing by laser-treatment.
- FIG. 6 is a perspective view of the semiconductor mounted for a laser raster scan.
- FIG. 7 is a top view of a laser raster scan.
- FIG. 8A is a side view of a device for bonding two semiconductor wafers to each other.
- FIG. 8B is a side view of the device of FIG. 8A bonding the two semiconductor wafers to each other.
- FIG. 9 is a top view of a device for separating bonded wafers.
- FIG. 10 is a cross-sectional view of bonded wafers with an epitaxial layer.
- FIG. 11A is a cross-sectional view of a bonded wafer layer of FIG. 10 with an ion implant wherein the implant is positioned within the layer.
- FIG. 11B is a cross-sectional view of a bonded wafer layer of FIG. 10 with an ion implant wherein the implant substantially traverses the layer.
- FIG. 12 is a cross-sectional view of a bonded wafer with a P-N junction.
- FIG. 13 is a cross-sectional view of a bonded wafer that comprises several layers.
- In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention.
- For purposes of this specification, the terms, “chip”, “wafer”, and “substrate” include any structure having an exposed surface of semiconductor material with which to form integrated circuit (IC) structures. These terms are also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. The terms include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures known in the art. The term “conductor” is understood to include semiconductors, and the term “insulator” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following description is, therefore, not to be taken in a limiting sense.
- The method of the present invention, for annealing and bonding one silicon wafer, such as is illustrated at10 in FIG. 1 to another
silicon wafer 12, to form a single bonded silicon wafer, illustrated in a perspective view at 14 in FIG. 2 and in cross-section in FIG. 3, includes providing twosilicon wafers wafers surfaces non-annealed surfaces - The present invention also includes a semiconductor device that comprises at least two
silicon wafers bond 24, formed by contacting surfaces of the twowafers - One embodiment of the semiconductor device, illustrated in cross-section at30 in FIG. 4, further includes a layer or
segment 26 produced by metallization, utilizing a metal such as aluminum, copper or other material such as polysilicon, that is positioned adjacent tosilicon 34. In the embodiment, the aluminum or other metal is layered over or within asilicon wafer 36. The aluminum or other metal displays no high temperature effects even though the annealing bond temperature utilized in the method of the present invention would be expected to cause aluminum and silicon to dissolve into each other. The dissolution is expected because a eutectic point for aluminum or other metal and silicon occurs at 450° C. - While aluminum is described, it is believed that other materials that melt or change within a temperature range that corresponds to the annealing temperature of silicon do not melt or change when subjected to the wafer annealing method of the present invention. Other materials include copper, polysilicon, and gold.
- The method of the present invention imparts to semiconductor device manufacture, a versatility not heretofore possible. With the method of the present invention, a semiconductor manufacturer can fabricate desired circuits on different wafers and then bond and anneal the wafers together without damaging or negatively impacting the circuits. As a consequence of the method of the present invention, circuit arrays may be mass produced on wafers and then combined with a variety of other, desired arrays on other wafers through the annealing and bonding process. This versatility is a great improvement over the conventional semiconductor fabrication methods which require a manufacturer to either perform the wafer bonding prior to circuit fabrication or to risk the occurrence of undesirable changes in a circuit as a result of exposure by the circuit to the elevated temperature of bonding.
- The silicon wafers provided in the method of the present invention are, in one embodiment, circular in shape with a diameter of about four inches. Wafers with other diameters or with other symmetries with other dimensions may also be suitable for use. Silicon constructions other than wafers are also suitable for use in the method of the present invention. It is also contemplated that semiconductor materials other than silicon may be usable in the method of the present invention, such as gallium arsenide or germanium.
- The silicon wafers are dipped in a dilute hydrofluoric acid (HF) solution in order to remove any native silicon oxide from the wafer surfaces to be bonded. The surfaces are rendered hydrophobic by replacement of oxygen from the silicon oxide on the wafer surface with hydrogen from the HF.
- The wafers with hydrophobic surfaces are then, in one embodiment, initially bonded to each other at room temperature and atmospheric pressure. The bonding is performed by contacting the wafers to each other in an environment free of dust or other airborne particles or vapors. The bonding process, illustrated in one embodiment in FIGS. 8A and 8B, employs a
spinner apparatus 200 andwafers spinner apparatus 200 bycontacts wafers infrared lamp 210 at a temperature that is less than approximately 80° C. After spinning, thewafers pinching mechanism 212. This initial bonding is principally due to van der Waals forces. - The bonded wafers are then transferred to an ultra-high vacuum (UHV) chamber which is pumped down to about 3×10−9 Torr. The bonded wafers are separated into two wafers by a separating mechanism such as is illustrated at 300 in FIG. 9. In one embodiment, the
separating mechanism 300 includes threewedges - In another embodiment, the wafers are stored in an ultra clean environment prior to introduction into the vacuum chamber. These wafers do not undergo an initial bonding step.
- The purpose of the wafer bonding is to retain cleanliness of wafer surfaces that are to be annealed. If the cleanliness can be maintained without bonding, then it is not required that the wafers be initially bonded to each other.
- Once the
wafers wafer surface 16 in FIG. 5. This exposure occurs in the vacuum chamber. Wafer surfaces 16 and 18 are sequentially exposed to energy fromlaser 38. The laser pulse sequentially elevates the temperature of thesurfaces - A pulsed energy source such as a pulsed laser is preferred because a laser operating in a pulsed mode can instantaneously heat an area of a wafer without influencing the underlying substrate. In particular, heating with a pulsed laser causes substantially no mechanical damage to the wafer because the thermal relaxation time of the pulsed laser is negligibly small as compared to the reaction time of a mechanical stress such as thermal expansion.
- The pulsed energy source should not be of a magnitude that is so high as to cause the silicon material or other semiconductor material to evaporate. The pulsed energy source must be of a magnitude to elevate the temperature to a range of 500 to 800° C.
- In one embodiment of the method of the present invention, the annealing energy is generated by a q-switched ruby laser, producing a wavelength of 0.69 microns. The peak power required is about 108 watts/cm2. For a fully illuminated four inch wafer, this energy corresponds to an incident optical pulse energy of approximately 243 joules.
- One other type of laser that may be used in the method of the present invention is a frequency doubled Neodymium doped Yittrium Aluminum Garnet (Nd/YAG) laser emitting 0.53 microns wavelength. A laser emitting light within the green spectrum, near the blue spectrum is suitable for use in the present invention. Because the absorption coefficient in silicon increases at shorter wavelengths, a decrease in the required pulse power and energy can be realized by choosing a shorter wavelength laser such as the ruby laser described, or the frequency doubled, Nd/YAG laser, described above.
- It is contemplated that energy sources other than pulsed optical energy may be used in the method of the present invention. These other energy sources include pulsed ion beam, pulsed x-ray beam and others. These other energy sources have the similar pulse width and energy as is described for laser beam energy. This annealing energy and laser source is optimal for the hydrophobic wafer surface because under the process conditions, the optical properties of the silicon are such that absorption coupling to the incident radiation is appreciably greater than for example, silicon dioxide. As a consequence, wafer material opposing the laser-treated
surfaces - In one other method embodiment, it has been found that by illuminating only a fraction of the wafer, for example 10% of the surface area, at a given time, the required pulse energy of a laser such as a q-switched ruby laser can be reduced by a factor of ten. This operation is performed at the expense of stepping the
annealing laser beam 10 to 20 times across the wafer surface. For a 48 mil thick, 4 inch wafer, the temperature rise of the surface opposite the surface illuminated with the full 243 joule pulse is about 15° C. This method embodiment of illuminating a fraction of a wafer surface area requires that the wafer surface area be capable of being scanned. Thewafer 101 is mounted on astage 100, such as is illustrated in FIG. 6 which is movable in an x-axis and a y-axis in relation to a fixedlaser beam 102. With the embodiment shown in FIG. 6, ascanning system 104 is comprised of alaser 106, amultifaceted mirror 108 and focusingoptics 110. Thebeam 102 from thelaser 106 is directed toward themultifaceted mirror 108 which rotates clockwise. Thebeam 102 is reflected toward thewafer 101 through the focusingoptics 110. Thebeam 102 impinges the surface of thewafer 101 and moves laterally across thewafer 101 as shown at 112 in FIG. 7. Themirror 108 rotates in concert with the movement of thewafer 101 which results in the wafer being raster scanned as is shown in FIG. 7. In another embodiment, thewafer 10 is fixed and the laser beam is collimated and reflected by x and y galvanometer-controlled mirrors. The laser beam is focused by lenses such as are shown at 40 and 42 in FIG. 5 to impinge in a raster x and y movement across thewafer 10. - By scanning the surface of the wafer, another efficiency improvement occurs. This improvement is an increase in the area and volume of the annealed and bonded wafer that is usable for circuit support. Conventionally bonded wafers have a disadvantage in that a silicon device layer covers the wafer to within three millimeters of the edge of the wafer substrate. The remaining wafer surfaces and wafer volume is unusable and is wasted. On a 100 millimeter square area wafer, this leads to a loss of approximately10% of the silicon wafer. Scanning the surface of the wafer with a laser substantially eliminates this wastage.
- An evolution of hydrogen gas resulting from driving hydrogen from the hydrophobic surfaces of the wafers increases pressure in the vacuum chamber to about 10−6 Torr. After the annealing step, the vacuum pressure in the vacuum chamber was decreased to approximately 3×10−9 Torr. The vacuum is of a magnitude that removes debris from the silicon surface formed during the annealing step.
- Laser annealed surfaces16 and 18 are brought together and pressed in a manner wherein force is concentrated in the center of the
wafers contact 26 which chemically bonds the wafers at 24. The contact produces a bonding wave over the designated annealing surface of the wafer. Theinterface 24 between the two wafers is bonded together by Si—Si bonds. The bond strength is typical of bulk silicon. - Process variables such as laser wavelength, laser output in joules, and vacuum magnitude are adjustable with experimentation in order to optimize the method of the present invention, by experimentation. In particular, wafers made under one set of identified process parameters are tested for bond strength and bond flaws. The tests are destructive tests. In one test, bonded wafers are pulled apart. In another test, bonded wafers are sectioned and are examined for flaws. Once optimal process variables are identified through fabrication and destructive testing, only a small percentage of the bonded wafers formed are checked for compliance.
- The bonded wafers produced by the method of the present invention may be fabricated for silicon-on-insulator, SOI, processes. In one embodiment, illustrated in FIG. 10, a bonded
wafer 500 is etched, preferentially, to pattern athin epitaxial layer 502 above a bondedregion 505. Theepitaxial layer 502 may be used for fabrication of CMOS or high voltage devices. The bondedwafer 500 also includes silicon layers 507 and 509 adjacent to the bondedregion 505. The bondedwafer 500 also includes an insulatingoxide layer 504 adjacent to thesilicon layer 509. In one embodiment, the insulatingoxide layer 504 is formed in a silicon substrate byion implantation 506, as is shown schematically forlayer 504 in FIGS. 11A and 11B.Ion implants 506 in FIG. 11A are positioned within thelayer 504 whileion implants 506 traverse thelayer 504 in FIG. 11B. - The wafer bonding process may be used to produce silicon wafers bonded to germanium to form sensors or fiber optic elements to electronic circuit interfaces. Silicon based circuits may also be integrated with gallium arsenide based circuits or lasers. With this bonding, the non-silicon wafer may be coated with a diffusion barrier such as silicon dioxide or a ceramic or tungsten. Once oxide is stripped from the silicon wafer, the wafer surface is annealed with a laser. The two wafers are clamped together to create a bond. This bonding process embodiment may be used to make a device such as a microminiature, electric-to-fluidic valve.
- The method of the present invention produces bonded wafers that are free from an oxide layer formed at the junction of the wafers. The benefit of this bonded wafer product is that it can be used in the manufacture of a device with a NMOS transistor and a PMOS transistor with minimal risk of “latch-up.”
- The localized annealing of the method of the present invention permits fabrication of devices with elements that are susceptible to damage at elevated temperatures because the elevated temperatures are restricted to the wafer surfaces. The wafer bonding process of the present invention may be used to bond a p type wafer such as is shown at450 in FIG. 12, with an
n type wafer 452 to form aP-N junction 454. A deep P-N junction can be provided by selecting wafers having substantially the same crystallographic orientation and opposite conductivity types of desired dopant concentrations. The orientations of the two wafers are aligned within approximately one degree. - One other type of SOI device illustrated at550 in FIG. 13 that can be prepared with the method of the present invention includes
several layers top silicon layer 552. Theselayers top silicon layer 552 is bonded to asilicon wafer 553 at 555. - The bonded wafers may be used to fabricate a single chip with multiple devices integrated within the chip. The bonded wafers permit improved device design for devices such as surface emitting lasers and light emitting diodes. These devices and device features include insulators hardened by radiation for increased radiation tolerance in military and space IC applications.
- Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.
Claims (40)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/189,276 US6423613B1 (en) | 1998-11-10 | 1998-11-10 | Low temperature silicon wafer bond process with bulk material bond strength |
US09/257,659 US6630713B2 (en) | 1998-11-10 | 1999-02-25 | Low temperature silicon wafer bond process with bulk material bond strength |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/189,276 US6423613B1 (en) | 1998-11-10 | 1998-11-10 | Low temperature silicon wafer bond process with bulk material bond strength |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/257,659 Division US6630713B2 (en) | 1998-11-10 | 1999-02-25 | Low temperature silicon wafer bond process with bulk material bond strength |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020076902A1 true US20020076902A1 (en) | 2002-06-20 |
US6423613B1 US6423613B1 (en) | 2002-07-23 |
Family
ID=22696661
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/189,276 Expired - Lifetime US6423613B1 (en) | 1998-11-10 | 1998-11-10 | Low temperature silicon wafer bond process with bulk material bond strength |
US09/257,659 Expired - Lifetime US6630713B2 (en) | 1998-11-10 | 1999-02-25 | Low temperature silicon wafer bond process with bulk material bond strength |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/257,659 Expired - Lifetime US6630713B2 (en) | 1998-11-10 | 1999-02-25 | Low temperature silicon wafer bond process with bulk material bond strength |
Country Status (1)
Country | Link |
---|---|
US (2) | US6423613B1 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050059217A1 (en) * | 2003-09-17 | 2005-03-17 | Patrick Morrow | Methods of forming backside connections on a wafer stack |
US20050211678A1 (en) * | 2004-02-27 | 2005-09-29 | Osram Opto Semiconductors Gmbh | Method for the connection of two wafers, and a wafer arrangement |
US20070119812A1 (en) * | 2005-11-28 | 2007-05-31 | Sebastien Kerdiles | Process and equipment for bonding by molecular adhesion |
FR2894068A1 (en) * | 2005-11-28 | 2007-06-01 | Soitec Silicon On Insulator | Bonding by molecular adhesion of two substrates to one another involves prior to bonding, modifying the surface state of one and/or the other of the substrates to regulate the propagation speed of bonding front |
US20070272991A1 (en) * | 2003-12-03 | 2007-11-29 | Elke Zakel | Method And Device For Alternately Contacting Two Wafers |
US20080113490A1 (en) * | 2006-11-09 | 2008-05-15 | Nec Electronics Corporation | Method for manufacturing semiconductor device |
US20120015497A1 (en) * | 2008-11-19 | 2012-01-19 | Gweltaz Gaudin | Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures |
US8361881B2 (en) | 2003-12-03 | 2013-01-29 | PAC Tech—Packaging Technologies GmbH | Method for alternately contacting two wafers |
DE102004012013B4 (en) * | 2004-02-27 | 2013-08-22 | Osram Opto Semiconductors Gmbh | wafer assembly |
WO2017019472A1 (en) * | 2015-07-30 | 2017-02-02 | Veeco Instruments Inc. | Method and apparatus for controlled dopant incorporation and activation in a chemical vapor deposition system |
Families Citing this family (549)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050280155A1 (en) * | 2004-06-21 | 2005-12-22 | Sang-Yun Lee | Semiconductor bonding and layer transfer method |
US7633162B2 (en) * | 2004-06-21 | 2009-12-15 | Sang-Yun Lee | Electronic circuit with embedded memory |
US7800199B2 (en) * | 2003-06-24 | 2010-09-21 | Oh Choonsik | Semiconductor circuit |
US8018058B2 (en) * | 2004-06-21 | 2011-09-13 | Besang Inc. | Semiconductor memory device |
US7470142B2 (en) * | 2004-06-21 | 2008-12-30 | Sang-Yun Lee | Wafer bonding method |
US8058142B2 (en) | 1996-11-04 | 2011-11-15 | Besang Inc. | Bonded semiconductor structure and method of making the same |
AU9296098A (en) * | 1997-08-29 | 1999-03-16 | Sharon N. Farrens | In situ plasma wafer bonding method |
US6780759B2 (en) * | 2001-05-09 | 2004-08-24 | Silicon Genesis Corporation | Method for multi-frequency bonding |
US7142577B2 (en) * | 2001-05-16 | 2006-11-28 | Micron Technology, Inc. | Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon |
US7018467B2 (en) * | 2002-01-17 | 2006-03-28 | Micron Technology, Inc. | Three-dimensional complete bandgap photonic crystal formed by crystal modification |
US6898362B2 (en) * | 2002-01-17 | 2005-05-24 | Micron Technology Inc. | Three-dimensional photonic crystal waveguide structure and method |
KR100442310B1 (en) * | 2001-11-28 | 2004-07-30 | 최우범 | Wafer bonding machine with plasma treatment and control method thereof |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
ATE353475T1 (en) * | 2002-10-11 | 2007-02-15 | Soitec Silicon On Insulator | METHOD AND DEVICE FOR PRODUCING AN ADHESIVE SUBSTRATE SURFACE |
US7799675B2 (en) * | 2003-06-24 | 2010-09-21 | Sang-Yun Lee | Bonded semiconductor structure and method of fabricating the same |
US20100133695A1 (en) * | 2003-01-12 | 2010-06-03 | Sang-Yun Lee | Electronic circuit with embedded memory |
US7198974B2 (en) * | 2003-03-05 | 2007-04-03 | Micron Technology, Inc. | Micro-mechanically strained semiconductor film |
US6908027B2 (en) * | 2003-03-31 | 2005-06-21 | Intel Corporation | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process |
US7220656B2 (en) * | 2003-04-29 | 2007-05-22 | Micron Technology, Inc. | Strained semiconductor by wafer bonding with misorientation |
US7115480B2 (en) * | 2003-05-07 | 2006-10-03 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
US7273788B2 (en) * | 2003-05-21 | 2007-09-25 | Micron Technology, Inc. | Ultra-thin semiconductors bonded on glass substrates |
US7008854B2 (en) | 2003-05-21 | 2006-03-07 | Micron Technology, Inc. | Silicon oxycarbide substrates for bonded silicon on insulator |
US7662701B2 (en) * | 2003-05-21 | 2010-02-16 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US20100190334A1 (en) * | 2003-06-24 | 2010-07-29 | Sang-Yun Lee | Three-dimensional semiconductor structure and method of manufacturing the same |
US8471263B2 (en) * | 2003-06-24 | 2013-06-25 | Sang-Yun Lee | Information storage system which includes a bonded semiconductor structure |
US7867822B2 (en) | 2003-06-24 | 2011-01-11 | Sang-Yun Lee | Semiconductor memory device |
US7632738B2 (en) * | 2003-06-24 | 2009-12-15 | Sang-Yun Lee | Wafer bonding method |
US7863748B2 (en) * | 2003-06-24 | 2011-01-04 | Oh Choonsik | Semiconductor circuit and method of fabricating the same |
US8071438B2 (en) * | 2003-06-24 | 2011-12-06 | Besang Inc. | Semiconductor circuit |
US6929984B2 (en) * | 2003-07-21 | 2005-08-16 | Micron Technology Inc. | Gettering using voids formed by surface transformation |
US7439158B2 (en) | 2003-07-21 | 2008-10-21 | Micron Technology, Inc. | Strained semiconductor by full wafer bonding |
US7186637B2 (en) | 2003-07-31 | 2007-03-06 | Intel Corporation | Method of bonding semiconductor devices |
US7153753B2 (en) * | 2003-08-05 | 2006-12-26 | Micron Technology, Inc. | Strained Si/SiGe/SOI islands and processes of making same |
US20060000814A1 (en) * | 2004-06-30 | 2006-01-05 | Bo Gu | Laser-based method and system for processing targeted surface material and article produced thereby |
US7261793B2 (en) * | 2004-08-13 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | System and method for low temperature plasma-enhanced bonding |
US7081421B2 (en) | 2004-08-26 | 2006-07-25 | Micron Technology, Inc. | Lanthanide oxide dielectric layer |
US7494939B2 (en) | 2004-08-31 | 2009-02-24 | Micron Technology, Inc. | Methods for forming a lanthanum-metal oxide dielectric layer |
US7374964B2 (en) | 2005-02-10 | 2008-05-20 | Micron Technology, Inc. | Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics |
US8455978B2 (en) | 2010-05-27 | 2013-06-04 | Sang-Yun Lee | Semiconductor circuit structure and method of making the same |
US8367524B2 (en) * | 2005-03-29 | 2013-02-05 | Sang-Yun Lee | Three-dimensional integrated circuit structure |
US20110143506A1 (en) * | 2009-12-10 | 2011-06-16 | Sang-Yun Lee | Method for fabricating a semiconductor memory device |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7544584B2 (en) | 2006-02-16 | 2009-06-09 | Micron Technology, Inc. | Localized compressive strained semiconductor |
US7737500B2 (en) * | 2006-04-26 | 2010-06-15 | International Business Machines Corporation | CMOS diodes with dual gate conductors, and methods for forming the same |
KR100748723B1 (en) * | 2006-07-10 | 2007-08-13 | 삼성전자주식회사 | Bonding method of substrates |
US8962447B2 (en) * | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
US7639912B2 (en) * | 2007-01-31 | 2009-12-29 | Hewlett-Packard Development Company, L.P. | Apparatus and method for subterranean distribution of optical signals |
TW200842932A (en) * | 2007-04-16 | 2008-11-01 | Promos Technologies Inc | Multi-layer semiconductor structure and manufacturing method thereof |
TWI355046B (en) * | 2007-07-10 | 2011-12-21 | Nanya Technology Corp | Two bit memory structure and method of making the |
US10378106B2 (en) | 2008-11-14 | 2019-08-13 | Asm Ip Holding B.V. | Method of forming insulation film by modified PEALD |
US8367516B2 (en) | 2009-01-14 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser bonding for stacking semiconductor substrates |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US9394608B2 (en) | 2009-04-06 | 2016-07-19 | Asm America, Inc. | Semiconductor processing reactor and components thereof |
US8405420B2 (en) | 2009-04-14 | 2013-03-26 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US8373439B2 (en) | 2009-04-14 | 2013-02-12 | Monolithic 3D Inc. | 3D semiconductor device |
US8378715B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
US7986042B2 (en) | 2009-04-14 | 2011-07-26 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9711407B2 (en) | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US8384426B2 (en) | 2009-04-14 | 2013-02-26 | Monolithic 3D Inc. | Semiconductor device and structure |
US8754533B2 (en) | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8427200B2 (en) | 2009-04-14 | 2013-04-23 | Monolithic 3D Inc. | 3D semiconductor device |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US8362482B2 (en) | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US8362800B2 (en) | 2010-10-13 | 2013-01-29 | Monolithic 3D Inc. | 3D semiconductor device including field repairable logics |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8222104B2 (en) | 2009-07-27 | 2012-07-17 | International Business Machines Corporation | Three dimensional integrated deep trench decoupling capacitors |
US8802201B2 (en) | 2009-08-14 | 2014-08-12 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11984445B2 (en) | 2009-10-12 | 2024-05-14 | Monolithic 3D Inc. | 3D semiconductor devices and structures with metal layers |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8476145B2 (en) | 2010-10-13 | 2013-07-02 | Monolithic 3D Inc. | Method of fabricating a semiconductor device and structure |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8148728B2 (en) | 2009-10-12 | 2012-04-03 | Monolithic 3D, Inc. | Method for fabrication of a semiconductor device and structure |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US8026521B1 (en) | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US8373230B1 (en) | 2010-10-13 | 2013-02-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8723335B2 (en) | 2010-05-20 | 2014-05-13 | Sang-Yun Lee | Semiconductor circuit structure and method of forming the same using a capping layer |
KR101134819B1 (en) | 2010-07-02 | 2012-04-13 | 이상윤 | Method for fabricating semiconductor memory |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US8273610B2 (en) | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US8163581B1 (en) | 2010-10-13 | 2012-04-24 | Monolith IC 3D | Semiconductor and optoelectronic devices |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US8114757B1 (en) | 2010-10-11 | 2012-02-14 | Monolithic 3D Inc. | Semiconductor device and structure |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US8379458B1 (en) | 2010-10-13 | 2013-02-19 | Monolithic 3D Inc. | Semiconductor device and structure |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11984438B2 (en) | 2010-10-13 | 2024-05-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
KR20150108428A (en) | 2011-04-11 | 2015-09-25 | 에베 그룹 에. 탈너 게엠베하 | Bendable carrier mounting, device and method for releasing a carrier substrate |
US8912017B2 (en) * | 2011-05-10 | 2014-12-16 | Ostendo Technologies, Inc. | Semiconductor wafer bonding incorporating electrical and optical interconnects |
US9312155B2 (en) | 2011-06-06 | 2016-04-12 | Asm Japan K.K. | High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules |
US10364496B2 (en) | 2011-06-27 | 2019-07-30 | Asm Ip Holding B.V. | Dual section module having shared and unshared mass flow controllers |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
US10854498B2 (en) | 2011-07-15 | 2020-12-01 | Asm Ip Holding B.V. | Wafer-supporting device and method for producing same |
US20130023129A1 (en) | 2011-07-20 | 2013-01-24 | Asm America, Inc. | Pressure transmitter for a semiconductor processing environment |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9017481B1 (en) | 2011-10-28 | 2015-04-28 | Asm America, Inc. | Process feed management for semiconductor substrate processing |
KR102355643B1 (en) * | 2011-12-22 | 2022-01-25 | 에베 그룹 에. 탈너 게엠베하 | Flexible substrate holder, device and method for detaching a first substrate |
EP2798670A1 (en) * | 2011-12-28 | 2014-11-05 | Ev Group E. Thallner GmbH | Method and device for bonding of substrates |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US9659799B2 (en) | 2012-08-28 | 2017-05-23 | Asm Ip Holding B.V. | Systems and methods for dynamic semiconductor process scheduling |
US10714315B2 (en) | 2012-10-12 | 2020-07-14 | Asm Ip Holdings B.V. | Semiconductor reaction chamber showerhead |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US9666763B2 (en) | 2012-11-30 | 2017-05-30 | Corning Incorporated | Glass sealing with transparent materials having transient absorption properties |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11967583B2 (en) | 2012-12-22 | 2024-04-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11961827B1 (en) | 2012-12-22 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8674470B1 (en) | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US20160376700A1 (en) | 2013-02-01 | 2016-12-29 | Asm Ip Holding B.V. | System for treatment of deposition reactor |
US9589770B2 (en) | 2013-03-08 | 2017-03-07 | Asm Ip Holding B.V. | Method and systems for in-situ formation of intermediate reactive species |
US9484191B2 (en) | 2013-03-08 | 2016-11-01 | Asm Ip Holding B.V. | Pulsed remote plasma method and system |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
CN105377783B (en) | 2013-05-10 | 2019-03-08 | 康宁股份有限公司 | Laser welding is carried out to transparent glass sheet using low melt glass or thin absorbing film |
US9240412B2 (en) * | 2013-09-27 | 2016-01-19 | Asm Ip Holding B.V. | Semiconductor structure and device and methods of forming same using selective epitaxial process |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10683571B2 (en) | 2014-02-25 | 2020-06-16 | Asm Ip Holding B.V. | Gas supply manifold and method of supplying gases to chamber using same |
US10167557B2 (en) | 2014-03-18 | 2019-01-01 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
US11015245B2 (en) | 2014-03-19 | 2021-05-25 | Asm Ip Holding B.V. | Gas-phase reactor and system having exhaust plenum and components thereof |
US10858737B2 (en) | 2014-07-28 | 2020-12-08 | Asm Ip Holding B.V. | Showerhead assembly and components thereof |
US9890456B2 (en) | 2014-08-21 | 2018-02-13 | Asm Ip Holding B.V. | Method and system for in situ formation of gas-phase compounds |
US9657845B2 (en) | 2014-10-07 | 2017-05-23 | Asm Ip Holding B.V. | Variable conductance gas distribution apparatus and method |
US10941490B2 (en) | 2014-10-07 | 2021-03-09 | Asm Ip Holding B.V. | Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same |
KR102512044B1 (en) | 2014-10-31 | 2023-03-20 | 코닝 인코포레이티드 | Laser welded glass packages and methods of making |
KR102263121B1 (en) | 2014-12-22 | 2021-06-09 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor device and manufacuring method thereof |
US10529542B2 (en) | 2015-03-11 | 2020-01-07 | Asm Ip Holdings B.V. | Cross-flow reactor and method |
US10276355B2 (en) | 2015-03-12 | 2019-04-30 | Asm Ip Holding B.V. | Multi-zone reactor, system including the reactor, and method of using the same |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US10458018B2 (en) | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
US10083836B2 (en) | 2015-07-24 | 2018-09-25 | Asm Ip Holding B.V. | Formation of boron-doped titanium metal films with high work function |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11978731B2 (en) | 2015-09-21 | 2024-05-07 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
DE112016004265T5 (en) | 2015-09-21 | 2018-06-07 | Monolithic 3D Inc. | 3D SEMICONDUCTOR DEVICE AND STRUCTURE |
US9960072B2 (en) | 2015-09-29 | 2018-05-01 | Asm Ip Holding B.V. | Variable adjustment for precise matching of multiple chamber cavity housings |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US10211308B2 (en) | 2015-10-21 | 2019-02-19 | Asm Ip Holding B.V. | NbMC layers |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11991884B1 (en) | 2015-10-24 | 2024-05-21 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US10322384B2 (en) | 2015-11-09 | 2019-06-18 | Asm Ip Holding B.V. | Counter flow mixer for process chamber |
US11139308B2 (en) | 2015-12-29 | 2021-10-05 | Asm Ip Holding B.V. | Atomic layer deposition of III-V compounds to form V-NAND devices |
KR20180114927A (en) * | 2016-02-16 | 2018-10-19 | 쥐-레이 스위츨란드 에스에이 | Structures, systems and methods for charge transport across bonded interfaces |
US10529554B2 (en) | 2016-02-19 | 2020-01-07 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10468251B2 (en) | 2016-02-19 | 2019-11-05 | Asm Ip Holding B.V. | Method for forming spacers using silicon nitride film for spacer-defined multiple patterning |
US10373830B2 (en) | 2016-03-08 | 2019-08-06 | Ostendo Technologies, Inc. | Apparatus and methods to remove unbonded areas within bonded substrates using localized electromagnetic wave annealing |
US10501866B2 (en) | 2016-03-09 | 2019-12-10 | Asm Ip Holding B.V. | Gas distribution apparatus for improved film uniformity in an epitaxial system |
US10343920B2 (en) | 2016-03-18 | 2019-07-09 | Asm Ip Holding B.V. | Aligned carbon nanotubes |
US9892913B2 (en) | 2016-03-24 | 2018-02-13 | Asm Ip Holding B.V. | Radial and thickness control via biased multi-port injection settings |
US10865475B2 (en) | 2016-04-21 | 2020-12-15 | Asm Ip Holding B.V. | Deposition of metal borides and silicides |
US10190213B2 (en) | 2016-04-21 | 2019-01-29 | Asm Ip Holding B.V. | Deposition of metal borides |
US10032628B2 (en) | 2016-05-02 | 2018-07-24 | Asm Ip Holding B.V. | Source/drain performance through conformal solid state doping |
US10367080B2 (en) | 2016-05-02 | 2019-07-30 | Asm Ip Holding B.V. | Method of forming a germanium oxynitride film |
KR102592471B1 (en) | 2016-05-17 | 2023-10-20 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming metal interconnection and method of fabricating semiconductor device using the same |
US11453943B2 (en) | 2016-05-25 | 2022-09-27 | Asm Ip Holding B.V. | Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor |
US10388509B2 (en) | 2016-06-28 | 2019-08-20 | Asm Ip Holding B.V. | Formation of epitaxial layers via dislocation filtering |
US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
US9859151B1 (en) | 2016-07-08 | 2018-01-02 | Asm Ip Holding B.V. | Selective film deposition method to form air gaps |
US10714385B2 (en) | 2016-07-19 | 2020-07-14 | Asm Ip Holding B.V. | Selective deposition of tungsten |
KR102354490B1 (en) | 2016-07-27 | 2022-01-21 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate |
US9812320B1 (en) | 2016-07-28 | 2017-11-07 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9887082B1 (en) | 2016-07-28 | 2018-02-06 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US10395919B2 (en) | 2016-07-28 | 2019-08-27 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
KR102532607B1 (en) | 2016-07-28 | 2023-05-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and method of operating the same |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US10410943B2 (en) | 2016-10-13 | 2019-09-10 | Asm Ip Holding B.V. | Method for passivating a surface of a semiconductor and related systems |
US10643826B2 (en) | 2016-10-26 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for thermally calibrating reaction chambers |
US11532757B2 (en) | 2016-10-27 | 2022-12-20 | Asm Ip Holding B.V. | Deposition of charge trapping layers |
US10643904B2 (en) | 2016-11-01 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for forming a semiconductor device and related semiconductor device structures |
US10229833B2 (en) | 2016-11-01 | 2019-03-12 | Asm Ip Holding B.V. | Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10435790B2 (en) | 2016-11-01 | 2019-10-08 | Asm Ip Holding B.V. | Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap |
US10134757B2 (en) | 2016-11-07 | 2018-11-20 | Asm Ip Holding B.V. | Method of processing a substrate and a device manufactured by using the method |
KR102546317B1 (en) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Gas supply unit and substrate processing apparatus including the same |
US10340135B2 (en) | 2016-11-28 | 2019-07-02 | Asm Ip Holding B.V. | Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride |
KR20180068582A (en) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
KR20180070971A (en) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10867788B2 (en) | 2016-12-28 | 2020-12-15 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10655221B2 (en) | 2017-02-09 | 2020-05-19 | Asm Ip Holding B.V. | Method for depositing oxide film by thermal ALD and PEALD |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10283353B2 (en) | 2017-03-29 | 2019-05-07 | Asm Ip Holding B.V. | Method of reforming insulating film deposited on substrate with recess pattern |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
KR102457289B1 (en) | 2017-04-25 | 2022-10-21 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10892156B2 (en) | 2017-05-08 | 2021-01-12 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US10446393B2 (en) | 2017-05-08 | 2019-10-15 | Asm Ip Holding B.V. | Methods for forming silicon-containing epitaxial layers and related semiconductor device structures |
US10504742B2 (en) | 2017-05-31 | 2019-12-10 | Asm Ip Holding B.V. | Method of atomic layer etching using hydrogen plasma |
US10886123B2 (en) | 2017-06-02 | 2021-01-05 | Asm Ip Holding B.V. | Methods for forming low temperature semiconductor layers and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
US10685834B2 (en) | 2017-07-05 | 2020-06-16 | Asm Ip Holdings B.V. | Methods for forming a silicon germanium tin layer and related semiconductor device structures |
KR20190009245A (en) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods for forming a semiconductor device structure and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US10312055B2 (en) | 2017-07-26 | 2019-06-04 | Asm Ip Holding B.V. | Method of depositing film by PEALD using negative bias |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10605530B2 (en) | 2017-07-26 | 2020-03-31 | Asm Ip Holding B.V. | Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10249524B2 (en) | 2017-08-09 | 2019-04-02 | Asm Ip Holding B.V. | Cassette holder assembly for a substrate cassette and holding member for use in such assembly |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
USD900036S1 (en) | 2017-08-24 | 2020-10-27 | Asm Ip Holding B.V. | Heater electrical connector and adapter |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
KR102491945B1 (en) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR102401446B1 (en) | 2017-08-31 | 2022-05-24 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10607895B2 (en) | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
KR102630301B1 (en) | 2017-09-21 | 2024-01-29 | 에이에스엠 아이피 홀딩 비.브이. | Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same |
US10844484B2 (en) | 2017-09-22 | 2020-11-24 | Asm Ip Holding B.V. | Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US10319588B2 (en) | 2017-10-10 | 2019-06-11 | Asm Ip Holding B.V. | Method for depositing a metal chalcogenide on a substrate by cyclical deposition |
US10923344B2 (en) | 2017-10-30 | 2021-02-16 | Asm Ip Holding B.V. | Methods for forming a semiconductor structure and related semiconductor structures |
US10910262B2 (en) | 2017-11-16 | 2021-02-02 | Asm Ip Holding B.V. | Method of selectively depositing a capping layer structure on a semiconductor device structure |
KR102443047B1 (en) | 2017-11-16 | 2022-09-14 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
WO2019103613A1 (en) | 2017-11-27 | 2019-05-31 | Asm Ip Holding B.V. | A storage device for storing wafer cassettes for use with a batch furnace |
TWI791689B (en) | 2017-11-27 | 2023-02-11 | 荷蘭商Asm智慧財產控股私人有限公司 | Apparatus including a clean mini environment |
US10290508B1 (en) | 2017-12-05 | 2019-05-14 | Asm Ip Holding B.V. | Method for forming vertical spacers for spacer-defined patterning |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
US11482412B2 (en) | 2018-01-19 | 2022-10-25 | Asm Ip Holding B.V. | Method for depositing a gap-fill layer by plasma-assisted deposition |
TWI799494B (en) | 2018-01-19 | 2023-04-21 | 荷蘭商Asm 智慧財產控股公司 | Deposition method |
USD903477S1 (en) | 2018-01-24 | 2020-12-01 | Asm Ip Holdings B.V. | Metal clamp |
US11018047B2 (en) | 2018-01-25 | 2021-05-25 | Asm Ip Holding B.V. | Hybrid lift pin |
US10535516B2 (en) | 2018-02-01 | 2020-01-14 | Asm Ip Holdings B.V. | Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures |
USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
CN111699278B (en) | 2018-02-14 | 2023-05-16 | Asm Ip私人控股有限公司 | Method for depositing ruthenium-containing films on substrates by cyclical deposition processes |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10731249B2 (en) | 2018-02-15 | 2020-08-04 | Asm Ip Holding B.V. | Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus |
US10658181B2 (en) | 2018-02-20 | 2020-05-19 | Asm Ip Holding B.V. | Method of spacer-defined direct patterning in semiconductor fabrication |
KR102636427B1 (en) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method and apparatus |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (en) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electrode on a substrate and a semiconductor device structure including an electrode |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US10510536B2 (en) | 2018-03-29 | 2019-12-17 | Asm Ip Holding B.V. | Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
KR102501472B1 (en) | 2018-03-30 | 2023-02-20 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method |
KR20190128558A (en) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures |
TW202349473A (en) | 2018-05-11 | 2023-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures |
KR102596988B1 (en) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11270899B2 (en) | 2018-06-04 | 2022-03-08 | Asm Ip Holding B.V. | Wafer handling chamber with moisture reduction |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
KR102568797B1 (en) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing system |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
KR20210027265A (en) | 2018-06-27 | 2021-03-10 | 에이에스엠 아이피 홀딩 비.브이. | Periodic deposition method for forming metal-containing material and film and structure comprising metal-containing material |
WO2020002995A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
KR20200002519A (en) | 2018-06-29 | 2020-01-08 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10767789B2 (en) | 2018-07-16 | 2020-09-08 | Asm Ip Holding B.V. | Diaphragm valves, valve components, and methods for forming valve components |
US10483099B1 (en) | 2018-07-26 | 2019-11-19 | Asm Ip Holding B.V. | Method for forming thermally stable organosilicon polymer film |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US10883175B2 (en) | 2018-08-09 | 2021-01-05 | Asm Ip Holding B.V. | Vertical furnace for processing substrates and a liner for use therein |
US10829852B2 (en) | 2018-08-16 | 2020-11-10 | Asm Ip Holding B.V. | Gas distribution device for a wafer processing apparatus |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR20200030162A (en) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | Method for deposition of a thin film |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (en) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | Substrate holding apparatus, system including the same, and method of using the same |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (en) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same |
US10847365B2 (en) | 2018-10-11 | 2020-11-24 | Asm Ip Holding B.V. | Method of forming conformal silicon carbide film by cyclic CVD |
US10811256B2 (en) | 2018-10-16 | 2020-10-20 | Asm Ip Holding B.V. | Method for etching a carbon-containing feature |
KR102605121B1 (en) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
KR102546322B1 (en) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US10381219B1 (en) | 2018-10-25 | 2019-08-13 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (en) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and substrate processing apparatus including the same |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US10559458B1 (en) | 2018-11-26 | 2020-02-11 | Asm Ip Holding B.V. | Method of forming oxynitride film |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (en) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | A method for cleaning a substrate processing apparatus |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
JP2020096183A (en) | 2018-12-14 | 2020-06-18 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method of forming device structure using selective deposition of gallium nitride, and system for the same |
TW202405220A (en) | 2019-01-17 | 2024-02-01 | 荷蘭商Asm Ip 私人控股有限公司 | Methods of forming a transition metal containing film on a substrate by a cyclical deposition process |
KR20200091543A (en) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor processing device |
CN111524788B (en) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | Method for topologically selective film formation of silicon oxide |
KR20200102357A (en) | 2019-02-20 | 2020-08-31 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for plug fill deposition in 3-d nand applications |
JP2020136677A (en) | 2019-02-20 | 2020-08-31 | エーエスエム・アイピー・ホールディング・ベー・フェー | Periodic accumulation method for filing concave part formed inside front surface of base material, and device |
KR102626263B1 (en) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | Cyclical deposition method including treatment step and apparatus for same |
KR102638425B1 (en) | 2019-02-20 | 2024-02-21 | 에이에스엠 아이피 홀딩 비.브이. | Method and apparatus for filling a recess formed within a substrate surface |
JP2020133004A (en) | 2019-02-22 | 2020-08-31 | エーエスエム・アイピー・ホールディング・ベー・フェー | Base material processing apparatus and method for processing base material |
KR20200108248A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME |
KR20200108242A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer |
KR20200108243A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Structure Including SiOC Layer and Method of Forming Same |
JP2020167398A (en) | 2019-03-28 | 2020-10-08 | エーエスエム・アイピー・ホールディング・ベー・フェー | Door opener and substrate processing apparatus provided therewith |
KR20200116855A (en) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | Method of manufacturing semiconductor device |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11447864B2 (en) | 2019-04-19 | 2022-09-20 | Asm Ip Holding B.V. | Layer forming method and apparatus |
KR20200125453A (en) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system and method of using same |
KR20200130121A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Chemical source vessel with dip tube |
KR20200130118A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Method for Reforming Amorphous Carbon Polymer Film |
KR20200130652A (en) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing material onto a surface and structure formed according to the method |
JP2020188255A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
JP2020188254A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141002A (en) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | Method of using a gas-phase reactor system including analyzing exhausted gas |
KR20200143254A (en) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (en) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | Temperature control assembly for substrate processing apparatus and method of using same |
JP2021015791A (en) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | Plasma device and substrate processing method using coaxial waveguide |
CN112216646A (en) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | Substrate supporting assembly and substrate processing device comprising same |
KR20210010307A (en) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210010820A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods of forming silicon germanium structures |
KR20210010816A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Radical assist ignition plasma system and method |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
JP2021019198A (en) | 2019-07-19 | 2021-02-15 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method of forming topology-controlled amorphous carbon polymer film |
TW202113936A (en) | 2019-07-29 | 2021-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation |
CN112309900A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112309899A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
KR20210018759A (en) | 2019-08-05 | 2021-02-18 | 에이에스엠 아이피 홀딩 비.브이. | Liquid level sensor for a chemical source vessel |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
JP2021031769A (en) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | Production apparatus of mixed gas of film deposition raw material and film deposition apparatus |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
KR20210024423A (en) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for forming a structure with a hole |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
KR20210024420A (en) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210029090A (en) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selective deposition using a sacrificial capping layer |
KR20210029663A (en) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (en) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process |
TW202129060A (en) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | Substrate processing device, and substrate processing method |
TW202115273A (en) | 2019-10-10 | 2021-04-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming a photoresist underlayer and structure including same |
KR20210045930A (en) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | Method of Topology-Selective Film Formation of Silicon Oxide |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (en) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for selectively etching films |
KR20210050453A (en) | 2019-10-25 | 2021-05-07 | 에이에스엠 아이피 홀딩 비.브이. | Methods for filling a gap feature on a substrate surface and related semiconductor structures |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (en) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | Structures with doped semiconductor layers and methods and systems for forming same |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (en) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure |
CN112951697A (en) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
KR20210065848A (en) | 2019-11-26 | 2021-06-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface |
CN112885693A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885692A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
JP2021090042A (en) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | Substrate processing apparatus and substrate processing method |
KR20210070898A (en) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
TW202125596A (en) | 2019-12-17 | 2021-07-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming vanadium nitride layer and structure including the vanadium nitride layer |
KR20210080214A (en) | 2019-12-19 | 2021-06-30 | 에이에스엠 아이피 홀딩 비.브이. | Methods for filling a gap feature on a substrate and related semiconductor structures |
TW202140135A (en) | 2020-01-06 | 2021-11-01 | 荷蘭商Asm Ip私人控股有限公司 | Gas supply assembly and valve plate assembly |
US11993847B2 (en) | 2020-01-08 | 2024-05-28 | Asm Ip Holding B.V. | Injector |
KR20210095050A (en) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming thin film and method of modifying surface of thin film |
TW202130846A (en) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming structures including a vanadium or indium layer |
KR20210100010A (en) | 2020-02-04 | 2021-08-13 | 에이에스엠 아이피 홀딩 비.브이. | Method and apparatus for transmittance measurements of large articles |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (en) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for growing phosphorous-doped silicon layer and system of the same |
TW202203344A (en) | 2020-02-28 | 2022-01-16 | 荷蘭商Asm Ip控股公司 | System dedicated for parts cleaning |
KR20210116249A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | lockout tagout assembly and system and method of using same |
KR20210116240A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate handling device with adjustable joints |
KR20210117157A (en) | 2020-03-12 | 2021-09-28 | 에이에스엠 아이피 홀딩 비.브이. | Method for Fabricating Layer Structure Having Target Topological Profile |
KR20210124042A (en) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | Thin film forming method |
TW202146689A (en) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | Method for forming barrier layer and method for manufacturing semiconductor device |
TW202145344A (en) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Apparatus and methods for selectively etching silcon oxide films |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
US11996289B2 (en) | 2020-04-16 | 2024-05-28 | Asm Ip Holding B.V. | Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods |
TW202146831A (en) | 2020-04-24 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Vertical batch furnace assembly, and method for cooling vertical batch furnace |
CN113555279A (en) | 2020-04-24 | 2021-10-26 | Asm Ip私人控股有限公司 | Method of forming vanadium nitride-containing layers and structures including the same |
KR20210132600A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element |
KR20210134226A (en) | 2020-04-29 | 2021-11-09 | 에이에스엠 아이피 홀딩 비.브이. | Solid source precursor vessel |
KR20210134869A (en) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Fast FOUP swapping with a FOUP handler |
KR20210141379A (en) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Laser alignment fixture for a reactor system |
TW202147383A (en) | 2020-05-19 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing apparatus |
KR20210145078A (en) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Structures including multiple carbon layers and methods of forming and using same |
KR20210145080A (en) | 2020-05-22 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus for depositing thin films using hydrogen peroxide |
TW202201602A (en) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing device |
TW202218133A (en) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
TW202217953A (en) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing method |
TW202219628A (en) | 2020-07-17 | 2022-05-16 | 荷蘭商Asm Ip私人控股有限公司 | Structures and methods for use in photolithography |
TW202204662A (en) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Method and system for depositing molybdenum layers |
TW202212623A (en) | 2020-08-26 | 2022-04-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming metal silicon oxide layer and metal silicon oxynitride layer, semiconductor structure, and system |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (en) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing material on stepped structure |
KR20220053482A (en) | 2020-10-22 | 2022-04-29 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing vanadium metal, structure, device and a deposition assembly |
TW202223136A (en) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming layer on substrate, and semiconductor processing system |
TW202235675A (en) | 2020-11-30 | 2022-09-16 | 荷蘭商Asm Ip私人控股有限公司 | Injector, and substrate processing apparatus |
CN114639631A (en) | 2020-12-16 | 2022-06-17 | Asm Ip私人控股有限公司 | Fixing device for measuring jumping and swinging |
TW202231903A (en) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate |
USD1023959S1 (en) | 2021-05-11 | 2024-04-23 | Asm Ip Holding B.V. | Electrode for substrate processing apparatus |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
Family Cites Families (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3407479A (en) | 1965-06-28 | 1968-10-29 | Motorola Inc | Isolation of semiconductor devices |
US3471754A (en) | 1966-03-26 | 1969-10-07 | Sony Corp | Isolation structure for integrated circuits |
US3689357A (en) | 1970-12-10 | 1972-09-05 | Gen Motors Corp | Glass-polysilicon dielectric isolation |
US4051354A (en) | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4305640A (en) * | 1978-11-24 | 1981-12-15 | National Research Development Corporation | Laser beam annealing diffuser |
US4292093A (en) * | 1979-12-28 | 1981-09-29 | The United States Of America As Represented By The United States Department Of Energy | Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces |
US4604162A (en) | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
US5208657A (en) | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4761768A (en) | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US4766569A (en) | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4673962A (en) | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US5102817A (en) | 1985-03-21 | 1992-04-07 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4663831A (en) | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
JPH0746702B2 (en) | 1986-08-01 | 1995-05-17 | 株式会社日立製作所 | Semiconductor memory device |
US5017504A (en) | 1986-12-01 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Vertical type MOS transistor and method of formation thereof |
JPS63254762A (en) * | 1987-04-13 | 1988-10-21 | Nissan Motor Co Ltd | Cmos semiconductor device |
JPH01125858A (en) | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
EP0316799B1 (en) | 1987-11-13 | 1994-07-27 | Nissan Motor Co., Ltd. | Semiconductor device |
US5327380B1 (en) | 1988-10-31 | 1999-09-07 | Texas Instruments Inc | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US4962879A (en) * | 1988-12-19 | 1990-10-16 | Duke University | Method for bubble-free bonding of silicon wafers |
US4948937A (en) * | 1988-12-23 | 1990-08-14 | Itt Corporation | Apparatus and method for heat cleaning semiconductor material |
US5021355A (en) | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
US5028977A (en) | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
JP2617798B2 (en) | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | Stacked semiconductor device and method of manufacturing the same |
JPH0821689B2 (en) | 1990-02-26 | 1996-03-04 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US4987089A (en) | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
US5475514A (en) | 1990-12-31 | 1995-12-12 | Kopin Corporation | Transferred single crystal arrayed devices including a light shield for projection displays |
US6143582A (en) | 1990-12-31 | 2000-11-07 | Kopin Corporation | High density electronic circuit modules |
US5097291A (en) * | 1991-04-22 | 1992-03-17 | Nikon Corporation | Energy amount control device |
US5223081A (en) | 1991-07-03 | 1993-06-29 | Doan Trung T | Method for roughening a silicon or polysilicon surface for a semiconductor substrate |
US5110752A (en) | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
US5202278A (en) | 1991-09-10 | 1993-04-13 | Micron Technology, Inc. | Method of forming a capacitor in semiconductor wafer processing |
JPH05198739A (en) | 1991-09-10 | 1993-08-06 | Mitsubishi Electric Corp | Laminated semiconductor device and its manufacture |
KR940006679B1 (en) | 1991-09-26 | 1994-07-25 | 현대전자산업 주식회사 | Dram cell having a vertical transistor and fabricating method thereof |
US5177028A (en) | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
US5156987A (en) | 1991-12-18 | 1992-10-20 | Micron Technology, Inc. | High performance thin film transistor (TFT) by solid phase epitaxial regrowth |
US5528062A (en) | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
US5320880A (en) | 1992-10-20 | 1994-06-14 | Micron Technology, Inc. | Method of providing a silicon film having a roughened outer surface |
US5324673A (en) | 1992-11-19 | 1994-06-28 | Motorola, Inc. | Method of formation of vertical transistor |
US5234535A (en) | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
US5266514A (en) | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
JP2701709B2 (en) * | 1993-02-16 | 1998-01-21 | 株式会社デンソー | Method and apparatus for directly joining two materials |
US5422499A (en) | 1993-02-22 | 1995-06-06 | Micron Semiconductor, Inc. | Sixteen megabit static random access memory (SRAM) cell |
US5306659A (en) | 1993-03-29 | 1994-04-26 | International Business Machines Corporation | Reach-through isolation etching method for silicon-on-insulator devices |
US5438009A (en) | 1993-04-02 | 1995-08-01 | United Microelectronics Corporation | Method of fabrication of MOSFET device with buried bit line |
US5616934A (en) | 1993-05-12 | 1997-04-01 | Micron Technology, Inc. | Fully planarized thin film transistor (TFT) and process to fabricate same |
US5441591A (en) | 1993-06-07 | 1995-08-15 | The United States Of America As Represented By The Secretary Of The Navy | Silicon to sapphire bond |
US5392245A (en) | 1993-08-13 | 1995-02-21 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
JP2605594B2 (en) | 1993-09-03 | 1997-04-30 | 日本電気株式会社 | Method for manufacturing semiconductor device |
GB9319070D0 (en) | 1993-09-15 | 1993-11-03 | Ncr Int Inc | Stencil having improved wear-resistance and quality consistency and method of manufacturing the same |
US5382540A (en) | 1993-09-20 | 1995-01-17 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
US5416041A (en) | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
US5393704A (en) | 1993-12-13 | 1995-02-28 | United Microelectronics Corporation | Self-aligned trenched contact (satc) process |
US5455445A (en) * | 1994-01-21 | 1995-10-03 | Kulite Semiconductor Products, Inc. | Multi-level semiconductor structures having environmentally isolated elements |
US5362665A (en) | 1994-02-14 | 1994-11-08 | Industrial Technology Research Institute | Method of making vertical DRAM cross point memory cell |
US5492853A (en) | 1994-03-11 | 1996-02-20 | Micron Semiconductor, Inc. | Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device |
US5414287A (en) | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
US5460988A (en) | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
US5495441A (en) | 1994-05-18 | 1996-02-27 | United Microelectronics Corporation | Split-gate flash memory cell |
JPH07320996A (en) * | 1994-05-24 | 1995-12-08 | Tokin Corp | Method and jig for electrostatic bonding |
US5440158A (en) | 1994-07-05 | 1995-08-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Electrically programmable memory device with improved dual floating gates |
US5593912A (en) | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
US5508542A (en) | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
JP3549602B2 (en) | 1995-01-12 | 2004-08-04 | 株式会社ルネサステクノロジ | Semiconductor storage device |
US5497017A (en) | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
US5508219A (en) | 1995-06-05 | 1996-04-16 | International Business Machines Corporation | SOI DRAM with field-shield isolation and body contact |
US6027960A (en) * | 1995-10-25 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Laser annealing method and laser annealing device |
US5640342A (en) | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
TW328641B (en) | 1995-12-04 | 1998-03-21 | Hitachi Ltd | Semiconductor integrated circuit device and process for producing the same |
US5892249A (en) | 1996-02-23 | 1999-04-06 | National Semiconductor Corporation | Integrated circuit having reprogramming cell |
JP3570530B2 (en) | 1996-04-26 | 2004-09-29 | 三菱住友シリコン株式会社 | Manufacturing method of SOI wafer |
US5710057A (en) | 1996-07-12 | 1998-01-20 | Kenney; Donald M. | SOI fabrication method |
US5691230A (en) | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
US6211039B1 (en) | 1996-11-12 | 2001-04-03 | Micron Technology, Inc. | Silicon-on-insulator islands and method for their formation |
US6190960B1 (en) | 1997-04-25 | 2001-02-20 | Micron Technology, Inc. | Method for coupling to semiconductor device in an integrated circuit having edge-defined sub-lithographic conductors |
US5909618A (en) | 1997-07-08 | 1999-06-01 | Micron Technology, Inc. | Method of making memory cell with vertical transistor and buried word and body lines |
US5891797A (en) | 1997-10-20 | 1999-04-06 | Micron Technology, Inc. | Method of forming a support structure for air bridge wiring of an integrated circuit |
JP4439020B2 (en) | 1998-03-26 | 2010-03-24 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US6291314B1 (en) | 1998-06-23 | 2001-09-18 | Silicon Genesis Corporation | Controlled cleavage process and device for patterned films using a release layer |
US6093623A (en) | 1998-08-04 | 2000-07-25 | Micron Technology, Inc. | Methods for making silicon-on-insulator structures |
US6274479B1 (en) | 1998-08-21 | 2001-08-14 | Micron Technology, Inc | Flowable germanium doped silicate glass for use as a spacer oxide |
US6423629B1 (en) | 2000-05-31 | 2002-07-23 | Kie Y. Ahn | Multilevel copper interconnects with low-k dielectrics and air gaps |
-
1998
- 1998-11-10 US US09/189,276 patent/US6423613B1/en not_active Expired - Lifetime
-
1999
- 1999-02-25 US US09/257,659 patent/US6630713B2/en not_active Expired - Lifetime
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050059217A1 (en) * | 2003-09-17 | 2005-03-17 | Patrick Morrow | Methods of forming backside connections on a wafer stack |
US6897125B2 (en) | 2003-09-17 | 2005-05-24 | Intel Corporation | Methods of forming backside connections on a wafer stack |
US20050164490A1 (en) * | 2003-09-17 | 2005-07-28 | Patrick Morrow | Methods of forming backside connections on a wafer stack |
US7056813B2 (en) | 2003-09-17 | 2006-06-06 | Intel Corporation | Methods of forming backside connections on a wafer stack |
US8361881B2 (en) | 2003-12-03 | 2013-01-29 | PAC Tech—Packaging Technologies GmbH | Method for alternately contacting two wafers |
US7932611B2 (en) * | 2003-12-03 | 2011-04-26 | PAC Tech—Packaging Technologies GmbH | Device for alternately contacting two wafers |
US20070272991A1 (en) * | 2003-12-03 | 2007-11-29 | Elke Zakel | Method And Device For Alternately Contacting Two Wafers |
US20050211678A1 (en) * | 2004-02-27 | 2005-09-29 | Osram Opto Semiconductors Gmbh | Method for the connection of two wafers, and a wafer arrangement |
US8471385B2 (en) | 2004-02-27 | 2013-06-25 | Osram Opto Semiconductors Gmbh | Method for the connection of two wafers, and a wafer arrangement |
DE102004012013B4 (en) * | 2004-02-27 | 2013-08-22 | Osram Opto Semiconductors Gmbh | wafer assembly |
US20110079911A1 (en) * | 2004-02-27 | 2011-04-07 | Osram Opto Semiconductors Gmbh | Method for the Connection of Two Wafers, and a Wafer Arrangement |
US7872210B2 (en) * | 2004-02-27 | 2011-01-18 | Osram Opto Semiconductors Gmbh | Method for the connection of two wafers, and a wafer arrangement |
US20070119812A1 (en) * | 2005-11-28 | 2007-05-31 | Sebastien Kerdiles | Process and equipment for bonding by molecular adhesion |
US20090294072A1 (en) * | 2005-11-28 | 2009-12-03 | S.O.I.Tec Silicon On Insulator Technologies | Equipment for bonding by molecular adhesion |
US20090261064A1 (en) * | 2005-11-28 | 2009-10-22 | S.O.I.Tec Silicon On Insulator Technologies | Process for bonding by molecular adhesion |
US7601271B2 (en) | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
FR2894068A1 (en) * | 2005-11-28 | 2007-06-01 | Soitec Silicon On Insulator | Bonding by molecular adhesion of two substrates to one another involves prior to bonding, modifying the surface state of one and/or the other of the substrates to regulate the propagation speed of bonding front |
US8091601B2 (en) | 2005-11-28 | 2012-01-10 | S.O.I.Tec Silicon On Insulator Technologies | Equipment for bonding by molecular adhesion |
WO2007060145A1 (en) * | 2005-11-28 | 2007-05-31 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
US8158013B2 (en) | 2005-11-28 | 2012-04-17 | Soitec | Process for bonding by molecular adhesion |
US7622362B2 (en) * | 2006-11-09 | 2009-11-24 | Nec Electronics Corporation | Method for manufacturing semiconductor device |
US20080113490A1 (en) * | 2006-11-09 | 2008-05-15 | Nec Electronics Corporation | Method for manufacturing semiconductor device |
US20120015497A1 (en) * | 2008-11-19 | 2012-01-19 | Gweltaz Gaudin | Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures |
WO2017019472A1 (en) * | 2015-07-30 | 2017-02-02 | Veeco Instruments Inc. | Method and apparatus for controlled dopant incorporation and activation in a chemical vapor deposition system |
US9748113B2 (en) | 2015-07-30 | 2017-08-29 | Veeco Intruments Inc. | Method and apparatus for controlled dopant incorporation and activation in a chemical vapor deposition system |
Also Published As
Publication number | Publication date |
---|---|
US6630713B2 (en) | 2003-10-07 |
US6423613B1 (en) | 2002-07-23 |
US20010014514A1 (en) | 2001-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6423613B1 (en) | Low temperature silicon wafer bond process with bulk material bond strength | |
KR100467755B1 (en) | A method of obtaining a thin film of semiconductor material, including electronic components | |
US7579654B2 (en) | Semiconductor on insulator structure made using radiation annealing | |
KR101035699B1 (en) | A method of direct bonding two substrates used in electronics, optics, or optoelectronics | |
US6599781B1 (en) | Solid state device | |
US8304324B2 (en) | Low-temperature wafer bonding of semiconductors to metals | |
US6908832B2 (en) | In situ plasma wafer bonding method | |
US6455398B1 (en) | Silicon on III-V semiconductor bonding for monolithic optoelectronic integration | |
KR100996539B1 (en) | Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species | |
EP0536790A2 (en) | Method for producing semiconductor articles | |
US20040009649A1 (en) | Wafer bonding of thinned electronic materials and circuits to high performance substrates | |
KR100634528B1 (en) | Fabrication method of single crystal Si film | |
EP0036157A1 (en) | Low temperature annealing of semiconductor devices | |
JP2006210898A (en) | Process for producing soi wafer, and soi wafer | |
KR20120041165A (en) | Sos substrate having low defect density in the vicinity of interface | |
KR20020020895A (en) | Production method for bonding wafer and bonding wafer produced by this method | |
KR20080086899A (en) | Process for producing soi wafer and soi wafer | |
US6555451B1 (en) | Method for making shallow diffusion junctions in semiconductors using elemental doping | |
EP2216803A1 (en) | Manufacturing method for laminated substrate | |
KR20140104477A (en) | Process for stabilizing a bonding interface, located within a structure which comprises an oxide layer and structure obtained | |
KR101124408B1 (en) | Linearly focused laser-annealing of buried species | |
US20060131268A1 (en) | Non-contact discrete removal of substrate surface contaminants/coatings, and method, apparatus, and system for implementing the same | |
TWI382470B (en) | Semiconductor on insulator structure made using radiation annealing | |
JP2024054760A (en) | Processed wafer dividing device and processed wafer dividing method | |
GB2112205A (en) | A thermal processing system for semiconductors and other materials using two or more electron beams |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GEUSIC, JOSEPH E.;REEL/FRAME:009575/0557 Effective date: 19981014 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001 Effective date: 20160426 |
|
AS | Assignment |
Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001 Effective date: 20180703 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001 Effective date: 20180629 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001 Effective date: 20190731 |
|
AS | Assignment |
Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001 Effective date: 20190731 |