US20020056875A1 - Thin film semiconductor device and display device - Google Patents
Thin film semiconductor device and display device Download PDFInfo
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- US20020056875A1 US20020056875A1 US09/212,383 US21238398A US2002056875A1 US 20020056875 A1 US20020056875 A1 US 20020056875A1 US 21238398 A US21238398 A US 21238398A US 2002056875 A1 US2002056875 A1 US 2002056875A1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Definitions
- the present invention relates to a thin film semiconductor device in which bottom gate type thin film transistors each containing an active layer of polycrystalline silicon or the like are formed in an integration structure on an insulating substrate, and also a display device using a thin film semiconductor device as a driving board, and more particularly to a technique for improving the characteristics of a bottom gate type thin film transistor.
- a thin film semiconductor device is suitably used as a driving board for display in an active matrix type liquid crystal display or the like, and its development is being positively promoted at present.
- Polycrystalline silicon or amorphous silicon is used for an active layer (channel region) of a thin film transistor.
- an active layer channel region
- the polycrystalline silicon thin film transistor because it can implement a compact and high-precision active matrix type color liquid crystal display device.
- a thin film transistor is formed as a pixel switching element on an insulating substrate formed of transparent glass or the like, and thus polycrystalline silicon thin films which are practically used as only electrode material or resistance material in a conventional semiconductor technique are used for active layers.
- This technique is only the technique of implementing thin film transistors for high-performance switching elements which can be produced in a high-density design to achieve such image quality as required in the market.
- this technique can also implement such a design that a peripheral circuit portion which has been hitherto provided as an external IC is formed on the same board as a pixel array portion in the same process.
- a top gate structure has been hitherto mainly adopted for thin film transistors.
- a semiconductor thin film is formed on an insulating substrate, and then a gate electrode is formed through a gate insulating film on the semiconductor thin film.
- a thin film semiconductor device for a liquid crystal display a low-cost and large-size glass plate is used as the insulating substrate.
- the glass plate contains a large amount of metal impurities such as Na, etc., and thus the impurities such as Na, etc. are localized in accordance with a driving voltage for the thin film transistor. Accordingly, the characteristic of the thin film transistor is varied in accordance with the electric field due to the localization of the metal impurities.
- a bottom gate structure In order to countermeasure this phenomenon, a bottom gate structure has been recently developed.
- a gate electrode formed of a metal film or the like is disposed on an insulating substrate of a glass plate or the like, and then a semiconductor thin film is formed through a gate insulating film on the gate electrode.
- the gate electrode has an effect of shielding the electric field in the glass plate, and from the structure viewpoint, the bottom gate structure is more excellent on the point of reliability than the top gate structure.
- FIG. 1 is a cross-sectional view showing a conventional thin film semiconductor device.
- the thin film semiconductor device shown in FIG. 1 is achieved by integrating thin film transistors 3 having the bottom gate structure on an insulating substrate 1 .
- the thin film transistor 3 has the bottom gate structure comprising a gate electrode 5 , a gate insulating film 4 , a semiconductor thin film 2 and an interlayer insulating film 9 which are laminated in this order from the lower side.
- a channel region 20 confronting the gate electrode 5 and a source region 7 and a drain region 8 which are located at both sides of the channel region 20 are formed in the semiconductor thin film 2 .
- a stopper 6 is provided just above the channel region 20 to protect the channel region 20 .
- the thin film transistor 3 thus formed is coated by the interlayer insulating film 9 .
- Conductor films 10 S, 10 D of aluminum or the like are formed on the interlayer insulating film 9 , and electrically connected to the source region 7 and the drain region 8 through contact holes formed in the interlayer insulating film 9 , respectively.
- the conductor films 10 S, 10 OD are subjected to a patterning treatment to serve as an electrode and a wire, respectively.
- the thin film transistor 3 and the conductor films 10 S, 10 D are coated by a planarization film 12 .
- An electrooptical material 50 such as liquid crystal or the like is superposed on a planarization film 12 .
- the upper portion of the channel region 20 is coated by the interlayer insulating film 9 formed of SiO 2 , SiN or the like and the planarization film 12 formed of acrylic resin or the like.
- This structure induces no special problem in a usual case.
- positive charges occur at the interface between the planarization film 12 and the electrooptical material 50 on the planarization film 12 .
- water or ions in the electrooptical material 50 are attracted by the potential of the gate electrode 5 or the like.
- a thin film semiconductor device comprises an insulating substrate, a plurality of thin film transistors integrated on the insulating substrate, each thin film transistor including a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, and the semiconductor thin film being formed with a channel region confronting the gate electrode, and a source region and a drain region which are located at both sides of the channel region, and a conductor film which is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
- the conductor film is connected to the same potential as the source region or the drain region.
- the conductor film is connected to a potential which is different from that of the source region or the drain region.
- the different potential is a gate potential.
- the different potential is a floating potential.
- the conductor film has a width dimension larger than that of the channel region.
- the conductor film is overlapped with a portion smaller than the overall length of the channel region.
- the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
- a display device having a pair of insulating substrates which are connected to each other through a predetermined gap, and electrooptical material held in the gap, comprises a counter electrode formed in one of the insulating substrates, and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate, wherein each thin film transistor comprises a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, the semiconductor thin film is formed with a channel region confronting the gate electrode, and a source region and a drain region located at both sides of the channel region, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
- the conductor film is connected to the same potential as the source region or the drain region.
- the conductor film is connected to a potential which is different from that of the source region or the drain region.
- the different potential is a gate potential.
- the different potential is a floating potential.
- the conductor film has a width dimension larger than that of the channel region.
- the conductor film is overlapped with a portion smaller than the overall length of the channel region.
- the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and are formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
- the upper portion of the channel region is covered by the conductor film. Therefore, when positive charges are supplied from the outside, the channel region is electrically shielded by the potential of the conductor film, so that no back channel is formed. Accordingly, the variation of the threshold voltage and the current leak of the thin film transistor having the bottom gate structure can be suppressed.
- FIG. 1 is a partial cross-sectional view showing a conventional thin film semiconductor device
- FIG. 2 is an energy band diagram showing the problem of the conventional thin film semiconductor device
- FIG. 3A is a schematic partial cross-sectional view of an embodiment of a thin film semiconductor device according to the present invention and FIGS. 3B and 3C are partial plan views of FIG. 3A;
- FIGS. 4A to 4 E are cross-sectional views showing a series of steps of manufacturing the thin film semiconductor device of FIG. 1;
- FIG. 5 is a partial cross-sectional view showing another embodiment of the thin film semiconductor device according to the present invention.
- FIG. 6 is a perspective view showing a display device according to the present invention.
- FIG. 3A is a schematic partial cross-sectional view of an embodiment of a thin film semiconductor device according to the present invention and FIGS. 3B and 3C are partial plan views of FIG. 3A.
- the thin film semiconductor device of this embodiment is obtained by integrating thin film transistors 3 on an insulating substrate 1 formed of glass or the like.
- the thin film transistor 3 has the bottom gate structure, and it includes a gate electrode 5 , a gate insulating film 4 , a semiconductor thin film 2 and an interlayer insulating film 9 which are laminated in this order from the lower side.
- the gate electrode 5 is formed by patterning a metal film
- the gate insulating film 4 comprises a monolayer film or a multilayered film
- the semiconductor thin film 2 is formed of polycrystalline silicon or the like
- the interlayer insulating film 9 is formed of SiO 2 or the like.
- a channel region 20 confronting the gate electrode 5 and both of a source region 7 and a drain region 8 which are located at both the sides of the channel region 20 are formed in the semiconductor thin film 2 serving as an element region of the thin film transistor 3 .
- the just upper portion of the channel region 20 is coated by a stopper 6 formed of SiO 2 or the like.
- Conductor films 10 S, 10 D of aluminum or the like are formed on the interlayer insulating film 9 by a patterning treatment.
- the conductor film 10 S is electrically connected to the source region 7 of the thin film transistor 3 through a contact hole formed in the interlayer insulating film 9 .
- the conductor film 10 D is electrically connected to the drain region 8 of the thin film transistor 3 through a contact hole formed in the interlayer insulating film 9 .
- These conductor films 10 S, 10 D function as an electrode and a wire.
- the conductor films 10 S, 10 D are coated by a planarization film 12 formed of acrylic resin or the like.
- This embodiment is characterized as follows. That is, the conductor 10 S is formed on the surface of the interlayer insulating film 9 so as to extend along a portion which is overlapped with the channel region 20 , thereby electrically shielding the channel region 20 from the outside. With the above construction, formation of a back channel in the channel region 20 can be prevented, and the variation of the threshold voltage and the current leak of the thin film transistor 3 can be suppressed.
- a part of the conductor 10 S which is patterned as the source electrode and the signal wire is used as electrical shield. That is, the conductor film 10 S for shield is connected to the same potential as the source region 7 . If occasions demand, the conductor film 10 D which is patterned as the drain electrode may be used for electrical shield. Alternatively, an electrical shielding conductor film may be formed just above the channel region 20 separately from the source electrode and the drain electrode. In this case, the electric shielding conductor film may be connected to a potential (for example, gate potential) which is different from the potential of the source region and the potential of the drain region. Even when it is connected to a floating potential, it can function as electric shield.
- a potential for example, gate potential
- FIG. 3B is a plan view showing the thin film transistor 3 shown in FIG. 3A.
- the islandish semiconductor thin film 2 is formed so as to cross the gate electrode 5 and so that the gate insulating film is sandwiched between the gate electrode 5 and the semiconductor thin film 2 .
- the overlapped portion of the semiconductor thin film 2 with the gate electrode 5 serves as the channel region 20 .
- the conductor film 10 S is connected to the source region through the contact hole CON formed in the interlayer insulating film, and the conductor film 10 D is likewise connected to the drain region through the contact hole CON formed in the interlayer insulating film.
- the conductor film 10 S at the source side is extended so as to be overlapped with the channel region 20 .
- the conductor film 10 S has a width dimension W1 larger than the width dimension W2 of the channel region 20 , whereby the current leak passage between the source region and the drain region can be perfectly shielded. Further, the conductor film 10 S is overlapped with a portion L1 which is smaller than the overall length L2 of the channel region. By electrically shielding at least a part of the channel region 20 , the current leak can be suppressed.
- FIG. 3C shows a modification in which the conductor film 10 S is extended so as to be overlapped with the overall channel region 20 .
- FIGS. 4A to 4 E are cross-sectional views of the thin film semiconductor device which show a series of steps of the manufacturing method of the thin film semiconductor device shown in FIG. 1.
- a metal film 5 a is formed on the overall surface of the insulating substrate 1 of glass or the like by a sputtering method.
- the metal film 5 a preferably has low resistance, and further it preferably has a high melting point. Therefore, W, Cr, Mo, Ti is generally used for the metal film 5 a.
- the thickness of the metal film 5 a is set to about 100 nm, for example.
- the metal film 5 a is patterned by an isotropic dry etching treatment to be processed into the gate electrode 5 .
- the isotropic dry etching treatment the sectional shape of the gate electrode 5 can be processed into a trapezoidal shape. That is, the end face of the gate electrode 5 is tapered in the range of 5 degrees to 15 degrees.
- SiO 2 is deposited at a thickness of 100 to 200 nm by a plasma CVD method (PE-CVD method) to form the gate insulating film 4 with which the gate electrode 5 is coated.
- PE-CVD method plasma CVD method
- amorphous silicon is deposited at a thickness of 20 to 60 nm to form the semiconductor thin film 2 .
- the gate insulating film 4 and the semiconductor thin film 2 can be continuously grown in the same film forming chamber with keeping the vacuum condition.
- the insulating substrate 1 is heated up to 400° C.
- the amorphous silicon semiconductor thin film 2 formed by the PE-CVD method contains about 10% hydrogen, and this hydrogen is separated by a heat treatment at 400° C.
- an XeCl excimer laser beam of 308 nm in wavelength is irradiated to crystallize the semiconductor thin film 2 .
- the amorphous silicon is melted by the energy of the laser beam, and it becomes polycrystal when it is solidified.
- the gate electrode 5 is processed in a trapezoidal shape, thereby preventing step breaking of the semiconductor thin film 2 at the step portion.
- SiO 2 is deposited on the semiconductor thin film 2 by the PE-CVD method.
- the film thickness thereof is set to about 200 nm.
- the SiO 2 film thus formed is patterned by using a back-side exposure technique to be processed into the stopper 6 . That is, the back-side exposure is performed by using the gate electrode 5 having the shielding performance as a mask, the stopper 6 which is matched with the gate electrode 5 with self alignment can be obtained.
- impurities for example, phosphorus
- the laser beam is irradiated again to activate the doped atoms.
- the same method as the crystallization is used, and the irradiation is sufficiently performed with weak energy because it is unnecessary to enlarge the crystals.
- SiO 2 is deposited at a thickness of 300 nm for insulation between wires, thereby forming the interlayer insulating film 9 .
- metal aluminum is deposited by the sputtering method and then patterned in a predetermined form to be processed into the conductor films 10 S, 10 D. At this time, the mask for patterning is improved so that the conductor film 10 S at the source side is extended onto the channel region 20 .
- the conductor film 10 S may cover the overall channel region 20 , however, it is sufficient to cover a part of the channel region 20 by the conductor film 10 . However, it is necessary to avoid a defective portion of the conductor film 10 S from occurring along the width direction of the channel region.
- FIG. 5 is a partial cross-sectional view showing another embodiment of the thin film semiconductor device according to the present invention.
- the thin film semiconductor device of this embodiment is achieved by integrating thin film transistors 3 having the bottom gate structure on an insulating substrate 1 of glass or the like, each thin film transistor 3 including a gate electrode 5 , a gate insulating film 4 , a semiconductor thin film 2 and an interlayer insulating film 9 which are laminated in this order from the lower side.
- the thin film semiconductor device of this embodiment is used for a driving board of an active matrix type display device. Therefore, each thin film transistor 3 is connected to a pixel electrode 14 .
- the thin film transistor 3 has a double gate structure to enhance the reliability thereof. That is, in the thin film transistor 3 , a pair of channel regions 20 which confront a pair of gate electrodes 5 are formed in the semiconductor thin film 2 .
- the gate electrode 5 is coated by the gate insulating film 4 of SiO 2 or the like.
- the semiconductor thin film 2 of polycrystalline silicon or the like is formed on the gate insulating film 4 .
- a stopper 6 is formed on the semiconductor thin film 2 by the patterning treatment so as to be matched with each gate electrode 5 .
- the portion of the semiconductor thin film 2 which locates just below the stopper 6 serves as the channel region 20 .
- a source region 7 and a drain region 8 which are obtained by doping high-concentration impurities are formed in the semiconductor thin film 2 .
- LDD regions 71 , 78 , 81 obtained by doping low-concentration impurities are also formed.
- the thin film transistor 3 thus constructed is coated by an interlayer insulating film 9 formed of SiO 2 or the like.
- a conductor film 10 S which also serves as a signal wire is formed on the interlayer insulating film 9 by the patterning treatment, and is electrically connected to the source region of the thin film transistor 3 through a contact hole.
- the conductor film 10 S is formed of aluminum or the like, and it extends to the upper portion of the channel region 20 and functions as an electrical shield.
- a conductor film 10 D is formed at the drain region 8 side by the patterning treatment, and extends to the upper portion of the other channel region 20 .
- These conductor films 10 S and 10 D are coated by a planarization film 12 .
- a pixel electrode 14 of ITO or the like is formed on the planarization film 12 by the patterning treatment.
- the pixel electrode 14 is electrically connected to the drain region 8 of the thin film transistor 3 through a contact hole formed in the planarization film 12 and the conductor film 10 D for connection.
- the thin film transistor 3 is designed so that a pair of channel regions 20 confronting a pair of gate electrodes 5 are formed in the semiconductor thin film 2 , and the conductor films 10 S, 10 D are formed on the surface of the interlayer insulating film 9 so as to be overlapped with the respective channel regions 20 .
- the electric shield may be formed so as to be overlapped with at least one channel region 20 .
- metal other than aluminum may be used for the conductor films 10 S, 10 D.
- the pixel electrode 14 may be extended to the upper portion of the channel region so that it serves as electric shield.
- the thin film transistor 3 is used for the switching driving of the pixel electrode 14 , and alternated video signals are applied to the thin film transistor 3 . Accordingly, in the actual switching operation, the source region 7 and the drain region 8 are alternately replaced by each other. In other words, the potential of the conductor films 10 S, 10 D is varied. It is necessary to set the film thickness of the interlayer insulating film 9 and the stopper 6 so that the potential does not exceed the threshold voltage at the back gate side of the thin film transistor 3 .
- one insulating substrate 60 is joined to the other insulating substrate 1 at a predetermined interval.
- the one insulating substrate 60 is formed of glass or the like, and a counter electrode 61 is beforehand formed on the surface thereof.
- liquid crystal is filled as the electrooptical material 50 in the gap between both the substrates 60 , 1 .
- FIG. 6 is a perspective view showing an example of an active matrix type liquid crystal display device in which the thin film semiconductor device according to the present invention is fabricated as a driving board.
- the display device has such a structure that the electrooptical material 50 formed of liquid crystal or the like is held between the driving board 1 and the counter board 60 .
- a pixel array portion and a peripheral circuit portion are integrated in the driving board 1 .
- the peripheral circuit portion is divided into a vertical scan circuit 41 and a horizontal scan circuit 42 .
- Terminal electrodes 47 for external connection are formed at the upper end side of the driving board 1 .
- Each terminal electrode 47 is connected through a wire 48 to the vertical scan circuit 41 and the horizontal scan circuit 42 .
- Gate wires 43 and signal wires 10 which cross each other are formed in the pixel array portion.
- the gate wires 43 are connected to the vertical scan circuit 41 , and the signal wires 10 are connected to the horizontal scan circuit 42 .
- the pixel electrode 14 and the thin film transistor 3 for driving the pixel electrode 14 are formed at the cross portion between the wires 43 , 10 .
- the thin film transistor 3 has the double gate structure shown in FIG. 5.
- the thin film transistors constituting the vertical scan circuit 41 and the horizontal scan circuit 42 have the single gate structure shown in FIG. 3A.
- a counter electrode (not shown) is also formed on the inner surface of the counter board 60 .
- the conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region, thereby electrically shielding the channel region from the outside, whereby the factor of instabilizing the operation of the thin film transistor having the bottom gate structure is removed, and thus the stable operation can be ensured. Therefore, there can be provided high-reliability and high-quality devices.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a thin film semiconductor device in which bottom gate type thin film transistors each containing an active layer of polycrystalline silicon or the like are formed in an integration structure on an insulating substrate, and also a display device using a thin film semiconductor device as a driving board, and more particularly to a technique for improving the characteristics of a bottom gate type thin film transistor.
- 2. Description of the Related Art
- A thin film semiconductor device is suitably used as a driving board for display in an active matrix type liquid crystal display or the like, and its development is being positively promoted at present. Polycrystalline silicon or amorphous silicon is used for an active layer (channel region) of a thin film transistor. Particularly, more attention is paid to the polycrystalline silicon thin film transistor because it can implement a compact and high-precision active matrix type color liquid crystal display device. According to this technique, a thin film transistor is formed as a pixel switching element on an insulating substrate formed of transparent glass or the like, and thus polycrystalline silicon thin films which are practically used as only electrode material or resistance material in a conventional semiconductor technique are used for active layers. This technique is only the technique of implementing thin film transistors for high-performance switching elements which can be produced in a high-density design to achieve such image quality as required in the market. At the same time, this technique can also implement such a design that a peripheral circuit portion which has been hitherto provided as an external IC is formed on the same board as a pixel array portion in the same process.
- A top gate structure has been hitherto mainly adopted for thin film transistors. In the top gate structure, a semiconductor thin film is formed on an insulating substrate, and then a gate electrode is formed through a gate insulating film on the semiconductor thin film. In a thin film semiconductor device for a liquid crystal display, a low-cost and large-size glass plate is used as the insulating substrate. The glass plate contains a large amount of metal impurities such as Na, etc., and thus the impurities such as Na, etc. are localized in accordance with a driving voltage for the thin film transistor. Accordingly, the characteristic of the thin film transistor is varied in accordance with the electric field due to the localization of the metal impurities. In order to countermeasure this phenomenon, a bottom gate structure has been recently developed. In the bottom gate structure, a gate electrode formed of a metal film or the like is disposed on an insulating substrate of a glass plate or the like, and then a semiconductor thin film is formed through a gate insulating film on the gate electrode. The gate electrode has an effect of shielding the electric field in the glass plate, and from the structure viewpoint, the bottom gate structure is more excellent on the point of reliability than the top gate structure.
- FIG. 1 is a cross-sectional view showing a conventional thin film semiconductor device.
- The thin film semiconductor device shown in FIG. 1 is achieved by integrating
thin film transistors 3 having the bottom gate structure on aninsulating substrate 1. For simplification of illustration, only one thin film transistor is illustrated. Thethin film transistor 3 has the bottom gate structure comprising agate electrode 5, a gateinsulating film 4, a semiconductorthin film 2 and an interlayerinsulating film 9 which are laminated in this order from the lower side. In thethin film transistor 3, achannel region 20 confronting thegate electrode 5, and asource region 7 and adrain region 8 which are located at both sides of thechannel region 20 are formed in the semiconductorthin film 2. Astopper 6 is provided just above thechannel region 20 to protect thechannel region 20. Thethin film transistor 3 thus formed is coated by theinterlayer insulating film 9.Conductor films interlayer insulating film 9, and electrically connected to thesource region 7 and thedrain region 8 through contact holes formed in theinterlayer insulating film 9, respectively. Theconductor films 10S, 10OD are subjected to a patterning treatment to serve as an electrode and a wire, respectively. When thin film semiconductor device thus formed is applied to a driving board for a display device, thethin film transistor 3 and theconductor films planarization film 12. Anelectrooptical material 50 such as liquid crystal or the like is superposed on aplanarization film 12. - In the bottom gate type
thin film transistor 3, the upper portion of thechannel region 20 is coated by theinterlayer insulating film 9 formed of SiO2, SiN or the like and theplanarization film 12 formed of acrylic resin or the like. This structure induces no special problem in a usual case. However, if it is installed into a display device or the like, it induces a problem on reliability. That is, positive charges occur at the interface between theplanarization film 12 and theelectrooptical material 50 on theplanarization film 12. Specifically, water or ions in theelectrooptical material 50 are attracted by the potential of thegate electrode 5 or the like. These materials are trapped as the positive charges at the interface between theplanarization film 12 and the positive charges are stocked on the surface of theinterlayer insulating film 9, EC falls at the back surface side of theinterlayer insulating film 9 as indicated by a dotted line, and the back channel BCH is formed along the interface between thechannel region 20 and theinterlayer insulating film 9. This induces the variation of the threshold voltage and the current like to the thin film transistor having the bottom gate structure. - The present invention has been implemented to overcome the above problem, and according to an aspect of the present invention, a thin film semiconductor device comprises an insulating substrate, a plurality of thin film transistors integrated on the insulating substrate, each thin film transistor including a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, and the semiconductor thin film being formed with a channel region confronting the gate electrode, and a source region and a drain region which are located at both sides of the channel region, and a conductor film which is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
- In the thin film semiconductor device, the conductor film is connected to the same potential as the source region or the drain region.
- In the thin film semiconductor device, the conductor film is connected to a potential which is different from that of the source region or the drain region.
- In the above thin film semiconductor device, the different potential is a gate potential.
- In the above thin film semiconductor device, the different potential is a floating potential.
- In the above thin film semiconductor device, the conductor film has a width dimension larger than that of the channel region.
- In the above thin film semiconductor device, the conductor film is overlapped with a portion smaller than the overall length of the channel region.
- In the above thin film semiconductor device, the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
- According to another aspect of the present invention, a display device having a pair of insulating substrates which are connected to each other through a predetermined gap, and electrooptical material held in the gap, comprises a counter electrode formed in one of the insulating substrates, and a plurality of pixel electrodes and a plurality of thin film transistors which are integrated on the other insulating substrate, wherein each thin film transistor comprises a gate electrode, a gate insulating film, a semiconductor thin film and an interlayer insulating film which are laminated in this order from the lower side, the semiconductor thin film is formed with a channel region confronting the gate electrode, and a source region and a drain region located at both sides of the channel region, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region.
- In the above display device, the conductor film is connected to the same potential as the source region or the drain region.
- In the above display device, the conductor film is connected to a potential which is different from that of the source region or the drain region.
- In the above display device, the different potential is a gate potential.
- In the above display device, the different potential is a floating potential.
- In the above display device, the conductor film has a width dimension larger than that of the channel region.
- In the above display device, the conductor film is overlapped with a portion smaller than the overall length of the channel region.
- In the above display device, the thin film transistor includes a pair of channel regions which confront a pair of gate electrodes and are formed in the semiconductor thin film, and a conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with at least one of the channel regions.
- According to the present invention, the upper portion of the channel region is covered by the conductor film. Therefore, when positive charges are supplied from the outside, the channel region is electrically shielded by the potential of the conductor film, so that no back channel is formed. Accordingly, the variation of the threshold voltage and the current leak of the thin film transistor having the bottom gate structure can be suppressed.
- FIG. 1 is a partial cross-sectional view showing a conventional thin film semiconductor device;
- FIG. 2 is an energy band diagram showing the problem of the conventional thin film semiconductor device;
- FIG. 3A is a schematic partial cross-sectional view of an embodiment of a thin film semiconductor device according to the present invention and FIGS. 3B and 3C are partial plan views of FIG. 3A;
- FIGS. 4A to4E are cross-sectional views showing a series of steps of manufacturing the thin film semiconductor device of FIG. 1;
- FIG. 5 is a partial cross-sectional view showing another embodiment of the thin film semiconductor device according to the present invention; and
- FIG. 6 is a perspective view showing a display device according to the present invention.
- Preferred embodiments according to the present invention will be described with reference to the accompanying drawings.
- FIG. 3A is a schematic partial cross-sectional view of an embodiment of a thin film semiconductor device according to the present invention and FIGS. 3B and 3C are partial plan views of FIG. 3A. As shown in FIG. 3A, the thin film semiconductor device of this embodiment is obtained by integrating
thin film transistors 3 on an insulatingsubstrate 1 formed of glass or the like. In order to clarify the understanding of the present invention, only onethin film transistor 3 is shown. Thethin film transistor 3 has the bottom gate structure, and it includes agate electrode 5, agate insulating film 4, a semiconductorthin film 2 and aninterlayer insulating film 9 which are laminated in this order from the lower side. Thegate electrode 5 is formed by patterning a metal film, thegate insulating film 4 comprises a monolayer film or a multilayered film, the semiconductorthin film 2 is formed of polycrystalline silicon or the like, and theinterlayer insulating film 9 is formed of SiO2 or the like. Achannel region 20 confronting thegate electrode 5 and both of asource region 7 and adrain region 8 which are located at both the sides of thechannel region 20 are formed in the semiconductorthin film 2 serving as an element region of thethin film transistor 3. The just upper portion of thechannel region 20 is coated by astopper 6 formed of SiO2 or the like.Conductor films interlayer insulating film 9 by a patterning treatment. Theconductor film 10S is electrically connected to thesource region 7 of thethin film transistor 3 through a contact hole formed in theinterlayer insulating film 9. Likewise, theconductor film 10D is electrically connected to thedrain region 8 of thethin film transistor 3 through a contact hole formed in theinterlayer insulating film 9. Theseconductor films conductor films planarization film 12 formed of acrylic resin or the like. - This embodiment is characterized as follows. That is, the
conductor 10S is formed on the surface of theinterlayer insulating film 9 so as to extend along a portion which is overlapped with thechannel region 20, thereby electrically shielding thechannel region 20 from the outside. With the above construction, formation of a back channel in thechannel region 20 can be prevented, and the variation of the threshold voltage and the current leak of thethin film transistor 3 can be suppressed. - In this embodiment, a part of the
conductor 10S which is patterned as the source electrode and the signal wire is used as electrical shield. That is, theconductor film 10S for shield is connected to the same potential as thesource region 7. If occasions demand, theconductor film 10D which is patterned as the drain electrode may be used for electrical shield. Alternatively, an electrical shielding conductor film may be formed just above thechannel region 20 separately from the source electrode and the drain electrode. In this case, the electric shielding conductor film may be connected to a potential (for example, gate potential) which is different from the potential of the source region and the potential of the drain region. Even when it is connected to a floating potential, it can function as electric shield. - FIG. 3B is a plan view showing the
thin film transistor 3 shown in FIG. 3A. - The islandish semiconductor
thin film 2 is formed so as to cross thegate electrode 5 and so that the gate insulating film is sandwiched between thegate electrode 5 and the semiconductorthin film 2. The overlapped portion of the semiconductorthin film 2 with thegate electrode 5 serves as thechannel region 20. Theconductor film 10S is connected to the source region through the contact hole CON formed in the interlayer insulating film, and theconductor film 10D is likewise connected to the drain region through the contact hole CON formed in the interlayer insulating film. Theconductor film 10S at the source side is extended so as to be overlapped with thechannel region 20. Theconductor film 10S has a width dimension W1 larger than the width dimension W2 of thechannel region 20, whereby the current leak passage between the source region and the drain region can be perfectly shielded. Further, theconductor film 10S is overlapped with a portion L1 which is smaller than the overall length L2 of the channel region. By electrically shielding at least a part of thechannel region 20, the current leak can be suppressed. FIG. 3C shows a modification in which theconductor film 10S is extended so as to be overlapped with theoverall channel region 20. - FIGS. 4A to4E are cross-sectional views of the thin film semiconductor device which show a series of steps of the manufacturing method of the thin film semiconductor device shown in FIG. 1. First, as shown in FIG. 4A, a
metal film 5 a is formed on the overall surface of the insulatingsubstrate 1 of glass or the like by a sputtering method. Themetal film 5 a preferably has low resistance, and further it preferably has a high melting point. Therefore, W, Cr, Mo, Ti is generally used for themetal film 5 a. The thickness of themetal film 5 a is set to about 100 nm, for example. - Subsequently, as shown in FIG. 4B, the
metal film 5 a is patterned by an isotropic dry etching treatment to be processed into thegate electrode 5. With the isotropic dry etching treatment, the sectional shape of thegate electrode 5 can be processed into a trapezoidal shape. That is, the end face of thegate electrode 5 is tapered in the range of 5 degrees to 15 degrees. Subsequently, as shown in FIG. 4C, SiO2 is deposited at a thickness of 100 to 200 nm by a plasma CVD method (PE-CVD method) to form thegate insulating film 4 with which thegate electrode 5 is coated. Further, amorphous silicon is deposited at a thickness of 20 to 60 nm to form the semiconductorthin film 2. Thegate insulating film 4 and the semiconductorthin film 2 can be continuously grown in the same film forming chamber with keeping the vacuum condition. Here, the insulatingsubstrate 1 is heated up to 400° C. The amorphous silicon semiconductorthin film 2 formed by the PE-CVD method contains about 10% hydrogen, and this hydrogen is separated by a heat treatment at 400° C. Thereafter, for example, an XeCl excimer laser beam of 308 nm in wavelength is irradiated to crystallize the semiconductorthin film 2. The amorphous silicon is melted by the energy of the laser beam, and it becomes polycrystal when it is solidified. At this time, since thegate electrode 5 is processed in a trapezoidal shape, thereby preventing step breaking of the semiconductorthin film 2 at the step portion. - Further, as shown in FIG. 4D, SiO2 is deposited on the semiconductor
thin film 2 by the PE-CVD method. The film thickness thereof is set to about 200 nm. The SiO2 film thus formed is patterned by using a back-side exposure technique to be processed into thestopper 6. That is, the back-side exposure is performed by using thegate electrode 5 having the shielding performance as a mask, thestopper 6 which is matched with thegate electrode 5 with self alignment can be obtained. Here, impurities (for example, phosphorus) at a predetermined concentration are doped into the semiconductorthin film 2 with an ion doping method by using thestopper 6 as a mask, whereby thesource region 7 and thedrain region 8 are formed. Further, thechannel region 20 into which no impurities are doped remains just below thestopper 6. Through the above process, the basic structure of the thin film transistor having the bottom gate structure can be obtained. - Finally, as shown in FIG. 4E, the laser beam is irradiated again to activate the doped atoms. The same method as the crystallization is used, and the irradiation is sufficiently performed with weak energy because it is unnecessary to enlarge the crystals. Thereafter, SiO2 is deposited at a thickness of 300 nm for insulation between wires, thereby forming the
interlayer insulating film 9. After contact holes are formed in theinterlayer insulating film 9, metal aluminum is deposited by the sputtering method and then patterned in a predetermined form to be processed into theconductor films conductor film 10S at the source side is extended onto thechannel region 20. With this structure, even when positive charges are supplied from the external, no back channel is formed because thechannel region 20 is shielded by the potential of theconductor film 10S. Accordingly, any variation of the threshold voltage and any current leak do not occur in the bottom gate typethin film transistor 3. Theconductor film 10S may cover theoverall channel region 20, however, it is sufficient to cover a part of thechannel region 20 by theconductor film 10. However, it is necessary to avoid a defective portion of theconductor film 10S from occurring along the width direction of the channel region. - FIG. 5 is a partial cross-sectional view showing another embodiment of the thin film semiconductor device according to the present invention.
- As shown in FIG. 5, the thin film semiconductor device of this embodiment is achieved by integrating
thin film transistors 3 having the bottom gate structure on an insulatingsubstrate 1 of glass or the like, eachthin film transistor 3 including agate electrode 5, agate insulating film 4, a semiconductorthin film 2 and aninterlayer insulating film 9 which are laminated in this order from the lower side. The thin film semiconductor device of this embodiment is used for a driving board of an active matrix type display device. Therefore, eachthin film transistor 3 is connected to apixel electrode 14. Thethin film transistor 3 has a double gate structure to enhance the reliability thereof. That is, in thethin film transistor 3, a pair ofchannel regions 20 which confront a pair ofgate electrodes 5 are formed in the semiconductorthin film 2. - The
gate electrode 5 is coated by thegate insulating film 4 of SiO2 or the like. The semiconductorthin film 2 of polycrystalline silicon or the like is formed on thegate insulating film 4. Further, astopper 6 is formed on the semiconductorthin film 2 by the patterning treatment so as to be matched with eachgate electrode 5. The portion of the semiconductorthin film 2 which locates just below thestopper 6 serves as thechannel region 20. Asource region 7 and adrain region 8 which are obtained by doping high-concentration impurities are formed in the semiconductorthin film 2. Further,LDD regions thin film transistor 3 thus constructed is coated by aninterlayer insulating film 9 formed of SiO2 or the like. Aconductor film 10S which also serves as a signal wire is formed on theinterlayer insulating film 9 by the patterning treatment, and is electrically connected to the source region of thethin film transistor 3 through a contact hole. Theconductor film 10S is formed of aluminum or the like, and it extends to the upper portion of thechannel region 20 and functions as an electrical shield. Likewise, aconductor film 10D is formed at thedrain region 8 side by the patterning treatment, and extends to the upper portion of theother channel region 20. Theseconductor films planarization film 12. Apixel electrode 14 of ITO or the like is formed on theplanarization film 12 by the patterning treatment. Thepixel electrode 14 is electrically connected to thedrain region 8 of thethin film transistor 3 through a contact hole formed in theplanarization film 12 and theconductor film 10D for connection. - According to this embodiment, the
thin film transistor 3 is designed so that a pair ofchannel regions 20 confronting a pair ofgate electrodes 5 are formed in the semiconductorthin film 2, and theconductor films interlayer insulating film 9 so as to be overlapped with therespective channel regions 20. In order to achieve the effect of the present invention, the electric shield may be formed so as to be overlapped with at least onechannel region 20. Further, metal other than aluminum may be used for theconductor films pixel electrode 14 may be extended to the upper portion of the channel region so that it serves as electric shield. - The
thin film transistor 3 is used for the switching driving of thepixel electrode 14, and alternated video signals are applied to thethin film transistor 3. Accordingly, in the actual switching operation, thesource region 7 and thedrain region 8 are alternately replaced by each other. In other words, the potential of theconductor films interlayer insulating film 9 and thestopper 6 so that the potential does not exceed the threshold voltage at the back gate side of thethin film transistor 3. - When a display device is fabricated by using the thin film semiconductor device of this embodiment, one insulating
substrate 60 is joined to the other insulatingsubstrate 1 at a predetermined interval. The one insulatingsubstrate 60 is formed of glass or the like, and acounter electrode 61 is beforehand formed on the surface thereof. For example, liquid crystal is filled as theelectrooptical material 50 in the gap between both thesubstrates - FIG. 6 is a perspective view showing an example of an active matrix type liquid crystal display device in which the thin film semiconductor device according to the present invention is fabricated as a driving board.
- The display device has such a structure that the
electrooptical material 50 formed of liquid crystal or the like is held between the drivingboard 1 and thecounter board 60. A pixel array portion and a peripheral circuit portion are integrated in the drivingboard 1. The peripheral circuit portion is divided into avertical scan circuit 41 and ahorizontal scan circuit 42.Terminal electrodes 47 for external connection are formed at the upper end side of the drivingboard 1. Eachterminal electrode 47 is connected through awire 48 to thevertical scan circuit 41 and thehorizontal scan circuit 42.Gate wires 43 andsignal wires 10 which cross each other are formed in the pixel array portion. Thegate wires 43 are connected to thevertical scan circuit 41, and thesignal wires 10 are connected to thehorizontal scan circuit 42. Thepixel electrode 14 and thethin film transistor 3 for driving thepixel electrode 14 are formed at the cross portion between thewires thin film transistor 3 has the double gate structure shown in FIG. 5. The thin film transistors constituting thevertical scan circuit 41 and thehorizontal scan circuit 42 have the single gate structure shown in FIG. 3A. A counter electrode (not shown) is also formed on the inner surface of thecounter board 60. - As described above, according to the present invention, the conductor film is formed on the surface of the interlayer insulating film so as to be overlapped with the channel region, thereby electrically shielding the channel region from the outside, whereby the factor of instabilizing the operation of the thin film transistor having the bottom gate structure is removed, and thus the stable operation can be ensured. Therefore, there can be provided high-reliability and high-quality devices.
Claims (16)
Applications Claiming Priority (3)
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JP09-364554 | 1997-12-18 | ||
JPP09-364554 | 1997-12-18 | ||
JP36455497A JP3587040B2 (en) | 1997-12-18 | 1997-12-18 | Thin film semiconductor device and display device |
Publications (2)
Publication Number | Publication Date |
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US20020056875A1 true US20020056875A1 (en) | 2002-05-16 |
US6410961B1 US6410961B1 (en) | 2002-06-25 |
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US09/212,383 Expired - Lifetime US6410961B1 (en) | 1997-12-18 | 1998-12-16 | Thin film semiconductor device and display device |
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US (1) | US6410961B1 (en) |
JP (1) | JP3587040B2 (en) |
KR (1) | KR100588438B1 (en) |
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WO2007004130A3 (en) * | 2005-06-30 | 2007-10-11 | Polymer Vision Ltd | Pixel perfromance improvement by use of a field-shield |
US20090246939A1 (en) * | 2008-03-25 | 2009-10-01 | Kazufumi Azuma | Method for dehydrogenation treatment and method for forming crystalline silicon film |
JP2014082356A (en) * | 2012-10-17 | 2014-05-08 | Nippon Hoso Kyokai <Nhk> | Thin film device manufacturing method |
US11635663B2 (en) | 2019-01-31 | 2023-04-25 | Japan Display Inc. | Display device and transistor |
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US6482684B1 (en) * | 1998-03-27 | 2002-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with Ge seeded amorphous Si layer |
JP3433101B2 (en) * | 1998-06-03 | 2003-08-04 | 三洋電機株式会社 | Display device |
US6246070B1 (en) * | 1998-08-21 | 2001-06-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same |
US6261881B1 (en) | 1998-08-21 | 2001-07-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit consisting of semiconductor element and method of manufacturing the same |
JP4493741B2 (en) * | 1998-09-04 | 2010-06-30 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
US7249299B1 (en) * | 2003-08-15 | 2007-07-24 | Eastman Kodak Company | Bidirectional horizontal scan circuit with sub-sampling and horizontal adding functions |
US7675501B2 (en) * | 2003-12-17 | 2010-03-09 | Samsung Electronics Co., Ltd. | Liquid crystal display apparatus with light sensor |
JP4877865B2 (en) * | 2004-03-26 | 2012-02-15 | 株式会社半導体エネルギー研究所 | Thin film transistor manufacturing method and display device manufacturing method |
JP5177887B2 (en) * | 2008-12-19 | 2013-04-10 | 株式会社ジャパンディスプレイセントラル | Liquid crystal display |
US20120242923A1 (en) * | 2010-02-25 | 2012-09-27 | Sharp Kabushiki Kaisha | Thin film transistor substrate, method for manufacturing the same, and display device |
JP2011002855A (en) * | 2010-09-22 | 2011-01-06 | Semiconductor Energy Lab Co Ltd | Liquid crystal display |
JP2014056963A (en) * | 2012-09-13 | 2014-03-27 | Toshiba Corp | Thin-film transistor and solid-state imaging device |
JP6319761B2 (en) * | 2013-06-25 | 2018-05-09 | ローム株式会社 | Semiconductor device |
JP2015035506A (en) * | 2013-08-09 | 2015-02-19 | 株式会社東芝 | Semiconductor device |
US10032924B2 (en) * | 2014-03-31 | 2018-07-24 | The Hong Kong University Of Science And Technology | Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability |
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Cited By (7)
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WO2007004130A3 (en) * | 2005-06-30 | 2007-10-11 | Polymer Vision Ltd | Pixel perfromance improvement by use of a field-shield |
US20100163875A1 (en) * | 2005-06-30 | 2010-07-01 | Polymer Vision Limited | Pixel performance improvement by use of a field shield |
US7989806B2 (en) | 2005-06-30 | 2011-08-02 | Creator Technology B.V. | Pixel performance improvement by use of a field-shield |
US20090246939A1 (en) * | 2008-03-25 | 2009-10-01 | Kazufumi Azuma | Method for dehydrogenation treatment and method for forming crystalline silicon film |
US7998841B2 (en) * | 2008-03-25 | 2011-08-16 | Advanced Lcd Technologies Development Center Co., Ltd. | Method for dehydrogenation treatment and method for forming crystalline silicon film |
JP2014082356A (en) * | 2012-10-17 | 2014-05-08 | Nippon Hoso Kyokai <Nhk> | Thin film device manufacturing method |
US11635663B2 (en) | 2019-01-31 | 2023-04-25 | Japan Display Inc. | Display device and transistor |
Also Published As
Publication number | Publication date |
---|---|
KR100588438B1 (en) | 2006-08-30 |
KR19990063153A (en) | 1999-07-26 |
JP3587040B2 (en) | 2004-11-10 |
JPH11186561A (en) | 1999-07-09 |
US6410961B1 (en) | 2002-06-25 |
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