US20020052089A1 - Method of manufacturing a cylindrical storage node in a semiconductor device - Google Patents

Method of manufacturing a cylindrical storage node in a semiconductor device Download PDF

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US20020052089A1
US20020052089A1 US09/983,348 US98334801A US2002052089A1 US 20020052089 A1 US20020052089 A1 US 20020052089A1 US 98334801 A US98334801 A US 98334801A US 2002052089 A1 US2002052089 A1 US 2002052089A1
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storage node
conductive layer
semiconductor device
hole
manufacturing
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US6451663B1 (en
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Sung-Gil Choi
Tae Ahn
Sang Jeong
Dae Chung
Won Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor

Definitions

  • the present invention refers to a method of manufacturing a cylindrical storage node in a semiconductor device with a minimum loss difference of a conductive layer between the center and the edge of cell areas during an etch-back process of storage node isolation.
  • the method of manufacturing a cylindrical storage node according to the present invention maintains electric capacitance uniformity over the entire cell area of a wafer and results in improved device reliability.
  • a semiconductor memory device like a dynamic random access memory (DRAM) includes cell capacitors for storing data.
  • DRAM dynamic random access memory
  • cylindrical stack structures are known as universal capacitor structures.
  • a poly plug 12 for bit line BC contacts is produced in an interlayer insulator 10 , and a nitride layer is deposited as an etch stopping layer 14 .
  • a molding oxide layer 16 is deposited on the nitride layer 14 , and a hole 18 is produced in the molding oxide layer 16 using a photolithographic etch process.
  • the nitride layer 14 exposed in the bottom of the hole 18 , is removed in an etch-back process and the poly plug 12 is exposed.
  • a storage conductive layer 20 is deposited to a uniform thickness.
  • a plugging material 22 is deposited to fill-up the inside of the hole 18 on the storage conductive layer 20 .
  • the plugging material 22 protects the bottom of the hole 18 in the storage node from being etched completely in the etch-back process of isolating the storage node.
  • the height of the deposited plugging material 22 in the center area of the cell having the holes 18 is lower than the height of the deposited plugging material 22 in the cell surrounding areas without the holes 18 in an amount of 2500 to 3000 ⁇ .
  • the time required to complete any etch-back process can be calculated by determining the average etch rate of the process and calculating the time necessary to etch through the layer. Etching is then allowed to continue for an over-etch period necessary to compensate any etch rate non-uniformity, layer thickness non-uniformity, or underlying topography. It is generally desirable to minimize the over-etch time so that the erosion of the underlying layer is minimized. A method of determining the nominal etching endpoint of the process allows such a reduction in over-etch time.
  • the endpoint of the etch-back process as illustrated in FIG. 3 is an etching time required for completely removing the storage conductive layer in cell surrounding areas.
  • the etch-back process removes the plugging material 22 and the storage conductive layer 20 up to the location indicated by a broken line 30 in FIG. 3. Isolation for the storage node is then achieved among each of the holes 18 .
  • the center area of the cell is then etched more than the cell surrounding areas by an amount of about 3000 ⁇ so that the height of the cylindrical node becomes lower than before, which renders maintaining sufficient capacitances in the semiconductor memory device difficult.
  • the etch-back process removes the plugging material 22 and the molding oxide layer 16 by employing an etch selectivity ratio between the oxide layer and the polysilicon and produces a cylindrical storage node 26 .
  • One storage node isolation method is a lift-off method that removes the plugged oxide layer remaining inside of the hole 18 by employing an etchant solution consisting of hydrogen fluoride (HF).
  • HF hydrogen fluoride
  • the HF etchant etches not only the plugged oxide layer but it also etches the interlayer insulator 10 underlying the etch stopping layer 14 , in the edge areas of a wafer.
  • defects such as bridge defects are generated as the next process steps are performed on the wafer.
  • Such defects may lead to failure in driving the semiconductor device, such as twin-bit failure in electrical die sorting EDS tests, which decreases the reliability of the final semiconductor devices.
  • Another method of storage node isolation employs a flowable oxide as the plugging material inside of the hole 18 and isolates the storage node by a chemical-mechanical polishing (CMP) process.
  • CMP chemical-mechanical polishing
  • the CMP process changes the surface morphology of a wafer and produces non-uniform heights of the storage nodes between cells or chips because of micro scratches, which also result in lowering device reliability.
  • the present invention provides a method of manufacturing a cylindrical storage node of a semiconductor device that minimizes a loss difference of the conductive layer, between the center and the edge areas of a cell, caused by an etch-back process of storage node isolation.
  • the method of manufacturing a cylindrical storage node of a semiconductor device according to the present invention maintains uniform electrical capacitances over the entire cell areas of a wafer, which results in improved reliability of the semiconductor device.
  • a method of manufacturing a cylindrical storage node in a semiconductor device comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by an etchback process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator.
  • a method of manufacturing a cylindrical storage node in a semiconductor device comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material, which is an oxide layer, on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by a wet etch process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator.
  • the plugging material is a photoresist which can be etched during the etch-back process by a mixed gas of oxygen and nitrogen as a reactive gas.
  • the plugging material is an oxide layer, which is one of undoped silicate glass (USG), a boron-phosphorus-silicate glass (BPSG), a silicate on glass (SOG), and a flowable oxide.
  • the oxide layer can be etched during the etch-back process by reactive gas mixtures such as CHF 3 /CO/Ar or C 5 F 8 /O 2 /Ar to utilize C-C, CFx radicals that etch the oxide layer selectively, or by a wet etch process involving a solution containing HF.
  • reactive gas mixtures such as CHF 3 /CO/Ar or C 5 F 8 /O 2 /Ar to utilize C-C, CFx radicals that etch the oxide layer selectively, or by a wet etch process involving a solution containing HF.
  • the etchant used for removing the exposed conductive layer is a main gas SF 6 and an additional gas Cl 2 or O 2 that performs an isotropic etch to the exposed conductive layer.
  • the plugging material remaining inside of the multiple holes is removed by an ashing process or a wet etch process.
  • FIGS. 1 - 4 are cross-sectional drawings of a semiconductor device sequentially illustrating a conventional method of manufacturing a cylindrical storage node
  • FIGS. 5 - 9 are cross-sectional drawings of a semiconductor device sequentially illustrating a method of manufacturing a cylindrical storage node in a semiconductor device according to the present invention.
  • Korean Patent Application No. 2000-63415 filed on Oct. 27, 2000, and entitled: “Cylindrical Storage Node Manufacturing Method in Semiconductor Device”, is incorporated herein by reference in its entirety.
  • FIGS. 5 - 9 are cross-sectional drawings of a semiconductor device sequentially illustrating a method of manufacturing a cylindrical storage node in a semiconductor device according to the present invention.
  • an interlayer insulator 10 is deposited, a poly plug 12 for a bit line contact BC is formed on the interlayer insulator 10 , and a nitride layer is deposited as an etch stopping layer 14 .
  • a molding oxide layer 16 is then deposited on the nitride layer 14 , and the hole 18 is produced in the molding oxide layer 16 using a photolithography and an etching process.
  • the etchback process removes the nitride layer exposed at the bottom of the hole 18 and then the poly plug 12 is exposed.
  • a storage conductive layer 20 is deposited to a uniform thickness.
  • a plugging material 22 such as a photoresist, chemical vapor deposition CVD oxide layer, or a flowable oxide layer, is deposited.
  • the CVD oxide layer includes a high temperature undoped silicate glass (USG), boron-phosphorous-silicate glass (BPSG), silicate on glass (SOG).
  • the plugging material 22 prevents the bottom of the hole in the storage node from being etched during an etchback process intended for isolating the storage node.
  • the deposited plugging material 22 in the cell surrounding areas, without the hole 18 underneath, is higher than that in the center of cell areas within the hole 18 by between about 2,500 to 3,000 ⁇ .
  • the etchback process employs a reactive gas mixture of oxygen and nitrogen so that an etch rate in the cell surrounding areas is faster than that in the center of the cell areas in the case that the plugging material 22 is a photoresist.
  • the etchback process etches the photoresist until the etchback process time reaches an endpoint where the photoresist in the cell surrounding areas is removed completely and the plugging photoresist material 22 remain only inside of the hole 18 .
  • the etchback process employs a reactive gas with a high etching selectivity ratio, for example CHF 3 /CO/Ar or C 5 F 8 /O 2 /Ar, between a polysilicon and the oxide layer. Therefore, the etchback process removes the plugging material 22 by using C-C or CFx radical and only the plugging material 22 inside of the hole 18 remains.
  • a reactive gas with a high etching selectivity ratio for example CHF 3 /CO/Ar or C 5 F 8 /O 2 /Ar
  • a wet etch method employing an etching solution containing HF for example the commercial product LAL200 (manufactured by Stellar, Japan), is used for removing the upper portion of the plugging oxide layer 22 except the oxide layer inside of the hole 18 .
  • the wet etching process exposes the upper portion of the molding insulator 16 and the conductive layer 20 in the surrounding areas of the multiple holes.
  • overetch amounts are determined within 50%, and more preferable overetch amounts are determined within 10%, because the excess overetch amounts in a wet etch process can expose the polysilicon at the bottom of the hole 18 in the case that the plugging material 22 has voids 24 as illustrated in FIG. 7.
  • Such an excess overetch process often causes etching of the polysilicon 12 exposed at the bottom of the hole 18 , during the polysilicon etchback process of the surrounding areas, generating a bad chip.
  • the polysilicon etchback process performs an isotropic etch to the exposed polysilicon 12 except to the polysilicon inside of the hole 18 , by employing a main gas SF 6 with an additional gas Cl 2 or O 2 , and isolates the storage conductive layer 20 of one hole from that of the other holes.
  • the plugging material 22 remaining inside of the hole 18 is removed in an ashing process or a wet etch process, and finally, the molding oxide layer 16 is removed, and a cylindrical storage conductive node 26 is thereby obtained.
  • the height loss of the storage conductive node according to the present invention is within about 1,000 ⁇ , so that the memory device according to the present invention can preserve more sufficient cell capacitances than the conventional memory device.
  • the present invention minimizes loss differences of the cylindrical storage node 26 between the center and the edge regions of cell areas caused by an etch-back process of storage node isolation in manufacturing a semiconductor device. Then, the cylindrical storage node manufacturing method according to the present invention maintains an uniform electric capacitance over the entire cell areas of a wafer, which results in an improved device reliability.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention refers to a method of manufacturing a cylindrical storage node in a semiconductor device with a minimum loss difference of a conductive layer between the center and the edge of cell areas during an etch-back process of storage node isolation. The method of manufacturing a cylindrical storage node according to the present invention maintains electric capacitance uniformity over the entire cell area of a wafer and results in improved device reliability. [0002]
  • 2. Description of the Related Art [0003]
  • A semiconductor memory device like a dynamic random access memory (DRAM) includes cell capacitors for storing data. As the degree of integration in a semiconductor memory device increases, the area of a cell unit decreases. Therefore, several approaches to guarantee availability of required capacitances in a limited space of a semiconductor memory device are researched and developed. [0004]
  • In general, cylindrical stack structures are known as universal capacitor structures. Referring to FIG. 1, in order to produce a cylindrical storage node in a semiconductor device, a [0005] poly plug 12 for bit line BC contacts is produced in an interlayer insulator 10, and a nitride layer is deposited as an etch stopping layer 14. As a next process step to produce the cylindrical storage node, a molding oxide layer 16 is deposited on the nitride layer 14, and a hole 18 is produced in the molding oxide layer 16 using a photolithographic etch process. The nitride layer 14, exposed in the bottom of the hole 18, is removed in an etch-back process and the poly plug 12 is exposed. Finally, a storage conductive layer 20 is deposited to a uniform thickness.
  • Referring to FIG. 2, a plugging [0006] material 22 is deposited to fill-up the inside of the hole 18 on the storage conductive layer 20. The plugging material 22 protects the bottom of the hole 18 in the storage node from being etched completely in the etch-back process of isolating the storage node. The height of the deposited plugging material 22 in the center area of the cell having the holes 18 is lower than the height of the deposited plugging material 22 in the cell surrounding areas without the holes 18 in an amount of 2500 to 3000 Å.
  • In general, the time required to complete any etch-back process can be calculated by determining the average etch rate of the process and calculating the time necessary to etch through the layer. Etching is then allowed to continue for an over-etch period necessary to compensate any etch rate non-uniformity, layer thickness non-uniformity, or underlying topography. It is generally desirable to minimize the over-etch time so that the erosion of the underlying layer is minimized. A method of determining the nominal etching endpoint of the process allows such a reduction in over-etch time. [0007]
  • The endpoint of the etch-back process as illustrated in FIG. 3 is an etching time required for completely removing the storage conductive layer in cell surrounding areas. The etch-back process removes the [0008] plugging material 22 and the storage conductive layer 20 up to the location indicated by a broken line 30 in FIG. 3. Isolation for the storage node is then achieved among each of the holes 18. The center area of the cell is then etched more than the cell surrounding areas by an amount of about 3000 Å so that the height of the cylindrical node becomes lower than before, which renders maintaining sufficient capacitances in the semiconductor memory device difficult.
  • Referring to FIG. 4, the etch-back process removes the [0009] plugging material 22 and the molding oxide layer 16 by employing an etch selectivity ratio between the oxide layer and the polysilicon and produces a cylindrical storage node 26.
  • One storage node isolation method is a lift-off method that removes the plugged oxide layer remaining inside of the [0010] hole 18 by employing an etchant solution consisting of hydrogen fluoride (HF). The HF etchant etches not only the plugged oxide layer but it also etches the interlayer insulator 10 underlying the etch stopping layer 14, in the edge areas of a wafer. As a result, defects such as bridge defects are generated as the next process steps are performed on the wafer. Such defects may lead to failure in driving the semiconductor device, such as twin-bit failure in electrical die sorting EDS tests, which decreases the reliability of the final semiconductor devices.
  • Another method of storage node isolation employs a flowable oxide as the plugging material inside of the [0011] hole 18 and isolates the storage node by a chemical-mechanical polishing (CMP) process. However, the CMP process changes the surface morphology of a wafer and produces non-uniform heights of the storage nodes between cells or chips because of micro scratches, which also result in lowering device reliability.
    • SUMMARY OF THE INVENTION
  • To overcome the above described problems, the present invention provides a method of manufacturing a cylindrical storage node of a semiconductor device that minimizes a loss difference of the conductive layer, between the center and the edge areas of a cell, caused by an etch-back process of storage node isolation. The method of manufacturing a cylindrical storage node of a semiconductor device according to the present invention maintains uniform electrical capacitances over the entire cell areas of a wafer, which results in improved reliability of the semiconductor device. [0012]
  • In accordance with a preferred embodiment of the present invention, there is provided a method of manufacturing a cylindrical storage node in a semiconductor device, comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by an etchback process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator. [0013]
  • In another embodiment of the present invention, there is provided another method of manufacturing a cylindrical storage node in a semiconductor device, comprising forming a plurality of holes in a molding insulator on cell areas, etching an etch stopping layer at the bottom of each hole and exposing a poly plug, depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes, filling a plugging material, which is an oxide layer, on the conductive layer deposited on the plurality of holes, removing an upper portion of the plugging material by a wet etch process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole, removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes, removing the plugging material from each hole, and removing the remaining molding insulator. [0014]
  • According to a feature of the present invention, the plugging material is a photoresist which can be etched during the etch-back process by a mixed gas of oxygen and nitrogen as a reactive gas. According to another feature of the present invention, the plugging material is an oxide layer, which is one of undoped silicate glass (USG), a boron-phosphorus-silicate glass (BPSG), a silicate on glass (SOG), and a flowable oxide. According to another feature of the present invention, the oxide layer can be etched during the etch-back process by reactive gas mixtures such as CHF[0015] 3/CO/Ar or C5F8/O2/Ar to utilize C-C, CFx radicals that etch the oxide layer selectively, or by a wet etch process involving a solution containing HF.
  • According to a feature of the present invention, the etchant used for removing the exposed conductive layer is a main gas SF[0016] 6 and an additional gas Cl2 or O2 that performs an isotropic etch to the exposed conductive layer. According to another feature of an embodiment of the present invention, the plugging material remaining inside of the multiple holes is removed by an ashing process or a wet etch process.
  • These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.[0017]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: [0018]
  • FIGS. [0019] 1-4 are cross-sectional drawings of a semiconductor device sequentially illustrating a conventional method of manufacturing a cylindrical storage node; and
  • FIGS. [0020] 5-9 are cross-sectional drawings of a semiconductor device sequentially illustrating a method of manufacturing a cylindrical storage node in a semiconductor device according to the present invention.
    • DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS
  • Korean Patent Application No. 2000-63415, filed on Oct. 27, 2000, and entitled: “Cylindrical Storage Node Manufacturing Method in Semiconductor Device”, is incorporated herein by reference in its entirety. [0021]
  • The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those of ordinary skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, and one or more intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. [0022]
  • Reference will now be made in detail to preferred embodiments of the present invention, an example of which is illustrated in the accompanying drawings. [0023]
  • FIGS. [0024] 5-9 are cross-sectional drawings of a semiconductor device sequentially illustrating a method of manufacturing a cylindrical storage node in a semiconductor device according to the present invention.
  • Referring now to FIG. 5, on a semiconductor substrate having an active area, a gate, and a bit line (not shown), an [0025] interlayer insulator 10 is deposited, a poly plug 12 for a bit line contact BC is formed on the interlayer insulator 10, and a nitride layer is deposited as an etch stopping layer 14.
  • A [0026] molding oxide layer 16 is then deposited on the nitride layer 14, and the hole 18 is produced in the molding oxide layer 16 using a photolithography and an etching process. The etchback process removes the nitride layer exposed at the bottom of the hole 18 and then the poly plug 12 is exposed. After these processes, a storage conductive layer 20 is deposited to a uniform thickness.
  • Referring to FIG. 6, in order to fill the inside of the [0027] hole 18 on the storage conductive layer 20, a plugging material 22 such as a photoresist, chemical vapor deposition CVD oxide layer, or a flowable oxide layer, is deposited.
  • The CVD oxide layer includes a high temperature undoped silicate glass (USG), boron-phosphorous-silicate glass (BPSG), silicate on glass (SOG). The [0028] plugging material 22 prevents the bottom of the hole in the storage node from being etched during an etchback process intended for isolating the storage node. The deposited plugging material 22 in the cell surrounding areas, without the hole 18 underneath, is higher than that in the center of cell areas within the hole 18 by between about 2,500 to 3,000 Å.
  • Referring to FIG. 7, the etchback process employs a reactive gas mixture of oxygen and nitrogen so that an etch rate in the cell surrounding areas is faster than that in the center of the cell areas in the case that the plugging [0029] material 22 is a photoresist. The etchback process etches the photoresist until the etchback process time reaches an endpoint where the photoresist in the cell surrounding areas is removed completely and the plugging photoresist material 22 remain only inside of the hole 18.
  • When the plugging [0030] material 22 employs an oxide layer, the etchback process employs a reactive gas with a high etching selectivity ratio, for example CHF3/CO/Ar or C5F8/O2/Ar, between a polysilicon and the oxide layer. Therefore, the etchback process removes the plugging material 22 by using C-C or CFx radical and only the plugging material 22 inside of the hole 18 remains.
  • On the contrary, when the process employs an oxide layer as the plugging [0031] material 22, a wet etch method employing an etching solution containing HF, for example the commercial product LAL200 (manufactured by Stellar, Japan), is used for removing the upper portion of the plugging oxide layer 22 except the oxide layer inside of the hole 18. The wet etching process exposes the upper portion of the molding insulator 16 and the conductive layer 20 in the surrounding areas of the multiple holes. Then, overetch amounts are determined within 50%, and more preferable overetch amounts are determined within 10%, because the excess overetch amounts in a wet etch process can expose the polysilicon at the bottom of the hole 18 in the case that the plugging material 22 has voids 24 as illustrated in FIG. 7. Such an excess overetch process often causes etching of the polysilicon 12 exposed at the bottom of the hole 18, during the polysilicon etchback process of the surrounding areas, generating a bad chip.
  • Referring to FIG. 8, the polysilicon etchback process performs an isotropic etch to the exposed [0032] polysilicon 12 except to the polysilicon inside of the hole 18, by employing a main gas SF6 with an additional gas Cl2 or O2, and isolates the storage conductive layer 20 of one hole from that of the other holes.
  • Referring to FIG. 9, the plugging [0033] material 22 remaining inside of the hole 18 is removed in an ashing process or a wet etch process, and finally, the molding oxide layer 16 is removed, and a cylindrical storage conductive node 26 is thereby obtained.
  • The height loss of the storage conductive node according to the present invention is within about 1,000 Å, so that the memory device according to the present invention can preserve more sufficient cell capacitances than the conventional memory device. [0034]
  • The present invention minimizes loss differences of the [0035] cylindrical storage node 26 between the center and the edge regions of cell areas caused by an etch-back process of storage node isolation in manufacturing a semiconductor device. Then, the cylindrical storage node manufacturing method according to the present invention maintains an uniform electric capacitance over the entire cell areas of a wafer, which results in an improved device reliability.
  • While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims. [0036]

Claims (11)

What is claimed is:
1. A method of manufacturing a cylindrical storage node in a semiconductor device, comprising:
forming a plurality of holes in a molding insulator on cell areas;
etching an etch stopping layer at the bottom of each hole and exposing a poly plug;
depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes;
filling a plugging material on the conductive layer deposited on the plurality of holes;
removing an upper portion of the plugging material by an etchback process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole;
removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes;
removing the plugging material from each hole; and
removing the remaining molding insulator.
2. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 1, wherein the plugging material is a photoresist.
3. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 2, wherein an etchant in the etchback process for removing the photoresist is a reactive gas mixture of oxygen and nitrogen.
4. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 1, wherein the plugging material is an oxide layer.
5. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 1, wherein an etchant in the etchback process for removing the oxide layer is selected from the group consisting of CHF3/CO/Ar and C5F8/O2/Ar.
6. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 1, wherein an etchant used in the etching process for removing the exposed conductive layer is a main gas SF6 and an additional gas Cl2 or O2, and performs an isotropic etch to the exposed conductive layer.
7. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 1, wherein the remaining plugging material inside of each hole is removed by an ashing process or a wet etch process.
8. A method of manufacturing a cylindrical storage node in a semiconductor device, comprising:
forming a plurality of holes in a molding insulator on cell areas;
etching an etch stopping layer at the bottom of each hole and exposing a poly plug;
depositing a conductive layer of a uniform thickness on the molding insulator having the plurality of holes;
filling a plugging material, which is an oxide layer, on the conductive layer deposited on the plurality of holes;
removing an upper portion of the plugging material by a wet etch process to expose an upper portion of the molding insulator and the conductive layer in surrounding areas of each hole;
removing the conductive layer exposed in surrounding areas of each hole to isolate the conductive layer in each hole from the conductive layer in other holes.
removing the plugging material from each hole; and
removing the remaining molding insulator.
9. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 8, wherein the oxide layer is one of undoped silicate glass (USG), a boron-phosphorous-silicate glass (BPSG), a silicate on glass (SOG), and a flowable oxide.
10. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 8, wherein an etchant in the wet etch process for removing the oxide layer is a solution containing HF.
11. A method of manufacturing a cylindrical storage node in a semiconductor device as claimed in claim 10, wherein an overetch amount in the wet etch process for the oxide layer is within about 50%.
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