US20020050851A1 - Method and apparatus for biasing radio frequency power transistors - Google Patents

Method and apparatus for biasing radio frequency power transistors Download PDF

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Publication number
US20020050851A1
US20020050851A1 US09/469,222 US46922299A US2002050851A1 US 20020050851 A1 US20020050851 A1 US 20020050851A1 US 46922299 A US46922299 A US 46922299A US 2002050851 A1 US2002050851 A1 US 2002050851A1
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US
United States
Prior art keywords
power transistor
transistor circuit
drain
low
impedance
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/469,222
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English (en)
Inventor
Johan Grundlingh
Robert Leroux
John J. Ilowski
Russell C. Smiley
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Nortel Networks Ltd
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Nortel Networks Ltd
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Publication date
Application filed by Nortel Networks Ltd filed Critical Nortel Networks Ltd
Priority to US09/469,222 priority Critical patent/US20020050851A1/en
Assigned to NORTEL NETWORKS CORPORATION reassignment NORTEL NETWORKS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ILOWSKI, JOHN J., LEROUX, ROBERT, GRUNDLINGH, JOHAN M., SMILEY, RUSSELL C.
Assigned to NORTEL NETWORKS LIMITED reassignment NORTEL NETWORKS LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NORTEL NETWORKS CORPORATION
Priority to US09/658,668 priority patent/US6373331B1/en
Priority to CA 2327887 priority patent/CA2327887A1/en
Priority to EP00311069A priority patent/EP1111774A1/de
Publication of US20020050851A1 publication Critical patent/US20020050851A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

Definitions

  • bias circuits in conventional RF power transistors have always entailed a trade-off.
  • bias circuits must be designed with a high impedance at RF frequencies so as not to affect the transistor input and output impedance or any impedance matching circuit used.
  • the bias circuits must also be designed with a low reactive impedance at low frequencies not to introduce any hysteresis distortion in the signal being amplified.
  • the bias circuit can advantageously be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance.
  • the hysteresis introduced can be substantially reduced.
  • the drain bias is maintained on the drain terminal and a large capacitor is used at an appropriate point in the output matching circuit to reduce hysteresis.
  • FIG. 1A is a diagram of a conventional radio frequency (RF) power transistor circuit with a drain bias circuit connection
  • FIG. 1B is an equivalent diagram of the RF power transistor circuit of FIG. 1A at RF frequencies showing in particular an unmatched output;
  • FIG. 2A is another diagram of the RF power transistor circuit of FIG. 1A packaged with an output impedance matching network in a conventional manner;
  • FIG. 2B is an equivalent diagram of the conventional RF power transistor circuit of FIG. 2A at RF frequencies showing in particular an improved output impedance
  • FIG. 3A is a diagram of a RF power transistor circuit packaged with a drain bias circuit connection according to a preferred embodiment of the invention
  • FIG. 3C is a voltage/time plot of an output signal S out2 (t) produced by the RF power transistor circuit of FIG. 3A;
  • FIG. 5A is a diagram of an RF power transistor circuit packaged with a base bias circuit connection according to another preferred embodiment of the invention.
  • FIG. 5B is an equivalent diagram of the RF power transistor circuit of FIG. 5A at RF frequencies.
  • FIG. 1A there is illustrated a diagram of a conventional LDMOS RF power transistor circuit 20 which includes an LDMOS RF power transistor 10 (hereinafter also referred to as the RF power transistor 10 ) and other components.
  • the RF power transistor 10 is formed of semiconductor material and is shown with a gate G, a drain D and a source S.
  • RF power transistors such as the RF power transistor 10 are typically manufactured in a circuit package that includes a terminal connection from each of the gate G and drain D to an external point on the package 20 . These terminal connections are typically made of bond wires and respectively define a gate terminal 12 and a drain terminal 14 .
  • the source D is on the other hand is directly connected to the circuit package flange which defines the source terminal 16 .
  • a bias circuit 18 is connected to the drain terminal 14 which defines the drain terminal 14 also as a drain bias feedpoint.
  • the bias circuit 18 provides the transistor drain D with a drain biasing current which may be far example, a positive direct current (DC). However, it is to be understood that depending on the MOSFET design of the transistor 10 , the bias circuit 18 could also be connected to provide a negative biasing current.
  • the bias circuit 18 is conventionally designed with resonant elements or quarter-wave stubs to provide a high impedance at RF frequencies so that the output impedance of the transistor 10 at these frequencies is not affected.
  • FIG. 1B there is shown a equivalent circuit for the transistor 10 at RF frequencies to better illustrate the transistor output impedance as seen between the drain and the source terminals 14 , 16 .
  • the output impedance of the transistor 10 at these frequencies can be modelled as the output capacitor 11 connected in parallel with a load impedance 15 which, for this example is set to 3 ohms.
  • the output capacitance modelled by the capacitor 11 reduces the transistor output impedance.
  • the drain inductor 13 affects the reactive component of the transistor output impedance and must also be considered when determining the transistor output impedance seen between the drain and source terminals 14 , 16 .
  • the bias circuit 18 introduces at RF frequencies an impedance extending between the drain terminal 14 and the source terminal 16 which has a tangible effect on the transistor output impedance seen between these terminals. It can be appreciated that if the bias circuit impedance is too low, it may seriously reduce the transistor output impedance. It becomes therefore highly desirable to design the bias circuit 18 with a high impedance at these frequencies so that it does not affect the transistor output impedance. Conventionally, the bias circuit 18 is designed with a high impedance at these frequencies so that it does not affect the transistor output impedance. Even with a high impedance bias circuit 18 however, the transistor output impedance in this arrangement is nevertheless quite low (see above) and certainly not matched to standard microwave impedances which can be for example 50 or 75 ohm.
  • FIG. 2A provides an example of this.
  • the transistor 10 of FIG. 1 is shown equipped with an output matching network generally denoted by 22 .
  • the output matching network 22 is connected between the drain D and the source S of the transistor 10 and consists of an inductor 24 of for example 0.14 nH connected in series with a capacitor 26 set with a relatively large value to become a short circuit at RF frequencies (further details below).
  • the main purpose of this impedance matching network 22 is to use the inductor 24 to resonate out the output capacitance 11 and improve the transistor output impedance.
  • FIG. 2B illustrates the transistor 10 at RF frequencies.
  • the capacitor 26 is sufficiently large (e.g. 700 pF) so that at these frequencies, it becomes a short circuit.
  • the 0.14 nH inductor 24 of the impedance matching network 22 operates to resonate out the 54 pF output capacitance 11 .
  • the hysteresis brought about by the reactive component of the bias circuit 18 causes distortion in proportion to the rate of change of the input signal being amplified.
  • the amount of hysteresis introduced in an input signal may at any given time depend on the recent history of the signal, the rate at which the signal operates or whether the input signal is on a rising edge or a falling edge.
  • the drain bias is fed through a low impedance point at RF frequencies (or a low RF impedance point)
  • the bias circuit 18 no longer adversely impacts the transistor output impedance at RF frequencies and can advantageously be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance.
  • the hysteresis introduced can be substantially reduced.
  • the transistor circuit 30 shown therein comprises a conventional RF power transistor 40 which, similarly to the RF power transistor 10 shown in previous figures can also be any power transistor which can operate at RF frequencies including for example FET transistors, LOMOS transistors or BJT transistors,
  • the transistor 40 is also assumed to be an LDMOS transistor.
  • the RF power transistor 40 has a gate G, a drain D and a source S which are respectively connected to a gate terminal 42 , a drain terminal 44 and a source terminal 46 on the transistor circuit 30 .
  • the drain terminal connection introduces a drain inductance represented by the inductor 45 .
  • the transistor 40 is also packaged with an output impedance matching network 51 formed of an inductor 47 and a capacitor 49 . These components are connected in series between the transistor drain D and source S to increase the transistor output impedance as seen between the drain and source terminals 44 , 46 .
  • the drain bias is fed at a low RF impedance point in the output impedance matching network 55 between the inductor 47 and the capacitor 49 .
  • the transistor circuit 30 is packaged with an additional terminal 48 to provide the necessary external connectivity for feeding the drain bias into this low RF impedance point.
  • the drain bias feedpoint which conventionally is live on the drain terminal 44 falls instead to RF ground.
  • the bias circuit 53 is shorted out and can as a result be designed with a much lower reactive impedance at low frequencies to substantially reduce hysteresis without adversely affecting the transistor output impedance.
  • the bias circuit 53 can be designed with an impedance that can be reduced by a factor of 10 therefore considerably reducing the hysteresis which would otherwise be introduced.
  • the RF power transistor circuit 60 described above in relation to FIGS. 5A and 5B is illustrative of cases where an additional terminal is required for the base bias. However, this may not always be the case.
  • RF power transistors such as LOMOS RF power transistors where the input impedance matching network is located externally to the transistor circuit packages a low RF impedance point may be available externally outside the transistor circuit package. As a result, it may not be necessary to use an additional input bias terminal to connect to a low RF impedance point.
  • the transistor base may connected directly to the base terminal therefore providing a low RF impedance point at the terminal. Instead of feeding the base bias through a different (dedicated) terminal to reach the transistor base, the base bias could be fed directly through the base terminal if such terminal is directly connected to the transistor base.
  • the invention has been described above in relation to LOMOS transistors. It is to be understood that the invention is not restricted to this particular type of MOSFET transistor and could also apply to other types of MOSFET transistors and other transistors including BJT transistors for example. Similarly, with respect to the input side, the invention is not restricted to BJT transistors and could also apply to other types of RF power transistors including MOSFET transistors for example. Generally stated, the invention could be applied to any power transistor which can operate at RF frequencies.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
US09/469,222 1999-12-22 1999-12-22 Method and apparatus for biasing radio frequency power transistors Abandoned US20020050851A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09/469,222 US20020050851A1 (en) 1999-12-22 1999-12-22 Method and apparatus for biasing radio frequency power transistors
US09/658,668 US6373331B1 (en) 1999-12-22 2000-09-08 Method and apparatus for reducing transistor amplifier hysteresis
CA 2327887 CA2327887A1 (en) 1999-12-22 2000-12-07 Method and apparatus for reducing transistor amplifier hysteresis
EP00311069A EP1111774A1 (de) 1999-12-22 2000-12-12 Verfahren und Vorrichtung zur Vorspannung von Hochfrequenzleistungstransistoren

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/469,222 US20020050851A1 (en) 1999-12-22 1999-12-22 Method and apparatus for biasing radio frequency power transistors

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/658,668 Continuation-In-Part US6373331B1 (en) 1999-12-22 2000-09-08 Method and apparatus for reducing transistor amplifier hysteresis

Publications (1)

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US20020050851A1 true US20020050851A1 (en) 2002-05-02

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US09/469,222 Abandoned US20020050851A1 (en) 1999-12-22 1999-12-22 Method and apparatus for biasing radio frequency power transistors
US09/658,668 Expired - Lifetime US6373331B1 (en) 1999-12-22 2000-09-08 Method and apparatus for reducing transistor amplifier hysteresis

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US09/658,668 Expired - Lifetime US6373331B1 (en) 1999-12-22 2000-09-08 Method and apparatus for reducing transistor amplifier hysteresis

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EP (1) EP1111774A1 (de)

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Publication number Priority date Publication date Assignee Title
JP2002204133A (ja) * 2000-12-28 2002-07-19 Matsushita Electric Ind Co Ltd 高周波増幅器
US6770166B1 (en) * 2001-06-29 2004-08-03 Lam Research Corp. Apparatus and method for radio frequency de-coupling and bias voltage control in a plasma reactor
US20030062571A1 (en) * 2001-10-03 2003-04-03 Franca-Neto Luiz M. Low noise microwave transistor based on low carrier velocity dispersion control
CN1625834B (zh) * 2002-02-01 2010-05-26 Nxp股份有限公司 半导体放大器元件的输出电路
US7034620B2 (en) 2002-04-24 2006-04-25 Powerwave Technologies, Inc. RF power amplifier employing bias circuit topologies for minimization of RF amplifier memory effects
IL150006A0 (en) * 2002-06-03 2002-12-01 Paragon Comm Ltd Apparatus for detecting the envelope of rf power signals
US6822321B2 (en) * 2002-09-30 2004-11-23 Cree Microwave, Inc. Packaged RF power transistor having RF bypassing/output matching network
JP2004228989A (ja) * 2003-01-23 2004-08-12 Renesas Technology Corp 半導体装置
US7167043B2 (en) * 2003-11-24 2007-01-23 International Rectifier Corporation Decoupling circuit for co-packaged semiconductor devices
US7366252B2 (en) * 2004-01-21 2008-04-29 Powerwave Technologies, Inc. Wideband enhanced digital injection predistortion system and method
EP1949534A1 (de) * 2005-11-16 2008-07-30 Filtronic PLC Verstärker
US8160518B2 (en) * 2006-08-10 2012-04-17 Freescale Semiconductor, Inc. Multi-mode transceiver having tunable harmonic termination circuit and method therefor
WO2009139680A1 (en) * 2008-05-16 2009-11-19 Telefonaktiebolaget L M Ericsson (Publ) Baseband decoupling of radio frequency power transistors
US8624676B2 (en) * 2012-03-08 2014-01-07 Telefonaktiebolaget L M Ericsson (Publ) Broadband transistor bias network

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Publication number Priority date Publication date Assignee Title
US5117203A (en) * 1990-12-13 1992-05-26 General Electric Company Phase stable limiting power amplifier
JP3120583B2 (ja) * 1992-08-25 2000-12-25 株式会社デンソー 高周波増幅器の安定化回路
JP2606165B2 (ja) * 1994-11-30 1997-04-30 日本電気株式会社 インピーダンス整合回路
JP3737549B2 (ja) * 1995-09-21 2006-01-18 東芝マイクロエレクトロニクス株式会社 利得制御回路および可変利得電力増幅器
JP3479422B2 (ja) * 1996-11-22 2003-12-15 アルプス電気株式会社 利得制御型トランジスタ電力増幅器
GB2332797B (en) * 1997-12-22 2003-05-21 Ericsson Telefon Ab L M Low voltage transistor biasing
US6052033A (en) * 1998-09-30 2000-04-18 Logitech, Inc. Radio frequency amplifier system and method
US6166599A (en) * 1998-12-04 2000-12-26 Qualcomm, Inc. Impedance matching networks for non-linear circuits
US6236274B1 (en) * 2000-01-04 2001-05-22 Industrial Technology Research Institute Second harmonic terminations for high efficiency radio frequency dual-band power amplifier

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Publication number Publication date
US6373331B1 (en) 2002-04-16
EP1111774A1 (de) 2001-06-27

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