US20020045279A1 - Methods for fabricating ferroelectric memory devices using pulsed-power plasma - Google Patents
Methods for fabricating ferroelectric memory devices using pulsed-power plasma Download PDFInfo
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- US20020045279A1 US20020045279A1 US09/569,069 US56906900A US2002045279A1 US 20020045279 A1 US20020045279 A1 US 20020045279A1 US 56906900 A US56906900 A US 56906900A US 2002045279 A1 US2002045279 A1 US 2002045279A1
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- ferroelectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Definitions
- FeRAM ferroelectric random access memory
- the dry etching is performed with plasma generated by RF (radio frequency) or micro power of hundreds kHz or several GHz. This method necessarily induces electrical or physical damage in the device.
- FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma.
- FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma.
- the pulsed-power plasma as used herein means the plasma generated by using pulsed-power inductively coupled plasma technique with time modulation.
- the pulsed-power plasma can generate the less etching damage than the continuous wave (CW) plasma.
- FIG. 3 shows a fabrication method of a ferroelectric memory device in accordance with one embodiment of the present invention.
- a second interlayer-insulating layer 15 with SiO 2 or the like is formed with a thickness of about 5500 ⁇ over the entire structure.
- a photoresist pattern 16 to define the region of contact hole is then formed on the second interlayer-insulating layer 15 .
- the second interlayer-insulating layer is then selectively etched with pulsed-power plasma using the photoresist pattern 16 as an etching mask to form contact holes exposing the Pt top electrode 14 and the Pt bottom electrode 12 .
- the etching is performed with the conditions of a source power of 800 W, a bias power of 600 W, a pressure of 5 mTorr, a temperature of 40° C., a CF 4 flow rate of 15 sccm, and an Ar flow rate of 15 sccm.
- the frequency for generating the pulsed-power plasma may range from 1 kHz to 100 kHz.
- FIG. 4 is a graph showing the ferroelectric polarization characteristics with input voltage at some modulation frequencies for generating the pulsed-power plasma.
- the ferroelectric characteristics such as remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor.
- the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage.
- FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma.
- the cumulative possibility is 50%
- the value of 2 Pr is about 9.2 ⁇ C/cm 2 in case of continuous wave (CW) plasma
- the value of 2 Pr in case of pulsed-power plasma is about 10.2 ⁇ C/cm 2 with regardless of frequency. Accordingly, when the etching is performed with the input of the pulsed-power plasma, the value of 2 Pr is less decreased by about 1 ⁇ C/cm 2 .
- FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma.
- the ferroelectric characteristics such as remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor.
- the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage.
- FIG. 7 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some duty ratios for generating the pulsed-power plasma.
- the cumulative possibility is 50%
- the value of 2 Pr is about 9.2 ⁇ C/cm 2 in case of continuous wave (CW) plasma
- the value of 2 Pr in case of pulsed-power plasma is about 10.4 ⁇ C/cm 2 with regardless of frequency.
- the value of 2 Pr is less decreased by about 1.2 ⁇ C/cm 2 .
Abstract
Description
- The present invention relates to fabrication methods of semiconductor memory devices; and, more particularly, to fabrication methods of ferroelectric memory devices, which can reduce the damage from plasma etching by using a pulsed-power technique.
- By using ferroelectric material into capacitors in semiconductor memory devices, there have been proceeded the developments of the devices which can overcome the limitation of refresh present in the conventional DRAM (Dynamic Random Access Memory) devices and have large capacitance of memory. FeRAM (ferroelectric random access memory) devices as non-volatile memory devices can store information even at the condition of power off and also are equitable in operating speed to the conventional DRAM. So, they are promising as a future generation of storage devices.
- Thin films of SrBi2Ta2O9 (hereinafter, referred as SBT) and Pb(Zr, Ti)O3 (hereinafter, referred as PZT) are mainly used as capacitance material in FeRAM devices. The ferroelectric materials have hundreds or thousands of dielectric constant at room temperature and two stable remanent polarization states. So, they are applied to the practices of nonvolatile memory devices with the states of thin films. The nonvolatile device with the ferroelectric thin film uses the principle that if an electric field is applied to the device to adjust the orientation of polarization and to input a signal, then the orientation of remanent polarization remained when the electric field is removed makes the
digital signal - After completed with the formation of a capacitor comprising of a bottom electrode, a ferroelectric thin film and a top electrode, an oxide layer for interlayer insulating is formed over the entire structure and selectively dry-etched to form contact holes exposing the top electrode and the bottom electrode.
- In the conventional fabrication method of FeRAM device, the dry etching is performed with plasma generated by RF (radio frequency) or micro power of hundreds kHz or several GHz. This method necessarily induces electrical or physical damage in the device.
- In case of DRAM, the etching damage from plasma may be recovered in any later thermal process, so it does not result in problems. However, in case of FeRAM using ferroelectric material such as SBT, the ferroelectric characteristics may be easily deteriorated with the plasma. This deterioration results in decreasing the reading and writing performances of FeRAM and reducing the lifetime of the device. Thus, a separate thermal treatment for recovering the ferroelectric characteristics should be performed at about 700° C. for about 30 minutes.
- Accordingly, there are required process developments, which can reduce the damage of ferroelectric layer generated during dry etching with plasma for the oxide layer covered over the capacitor.
- It is, therefore, an object of the present invention to provide a method for fabricating ferroelectric memory devices, which can prevent the deterioration of ferroelectric characteristics generated from conventional dry etching with continuous wave plasma for interlayer-insulating layer for forming capacitor contact.
- In accordance with an embodiment of the present invention, there is provided a method for fabricating a ferroelectric memory device, which comprises the steps of forming an interlayer-insulating layer over the entire structure completed with the formation of a ferroelectric capacitor including a bottom electrode, a ferroelectric layer and a top electrode; and selectively etching the interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.
- In accordance with another embodiment of the present invention, there is provided a method for fabricating a ferroelectric memory device, which comprises the steps of forming a first interlayer-insulating layer over the entire structure completed with the formation of transistor; forming a capacitor which includes a bottom electrode, a ferroelectric layer and a top electrode and in which the ferroelectric layer and the top electrode are superimposed on a part of the bottom electrode; forming a second interlayer-insulating layer over the ferroelectric capacitor; and selectively etching the second interlayer-insulating layer with pulsed-power plasma to form a contact hole exposing the top electrode of capacitor.
- The present invention is characterized in that the interlayer-insulating layer covering the capacitor is etched with time modulated plasma, namely pulsed-power plasma. The pulsed-power plasma has lower electron temperature and ion energy within the plasma than the conventional continuous wave plasma. This is because high energetic electrons in the plasma are cooled during plasma off-period when the main power is adjusted with several decades microseconds.
- The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
- FIG. 1 is a graph showing electron energy distribution functions of pulsed-power plasma at some duty ratios, compared with electron energy distribution function of continuous wave plasma.
- FIG. 2 is a graph showing electron energy distribution functions of pulsed-power plasma at some modulation frequencies, compared with that of continuous wave plasma.
- FIG. 3 is a cross-sectional view showing the fabrication processes for the ferroelectric memory device in accordance with one embodiment of the present invention.
- FIG. 4 is a graph showing the ferroelectric polarization characteristics with input voltage at some modulation frequencies for generating the pulsed-power plasma.
- FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma.
- FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma.
- FIG. 7 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some duty ratios for generating the pulsed-power plasma.
- The pulsed-power plasma as used herein means the plasma generated by using pulsed-power inductively coupled plasma technique with time modulation.
- The electrical damage suppression method in ferroelectric capacitor contact etching is also described in a document entitled with “Electrical Damage Suppression Using a Pulsed-Power Inductively Coupled Plasma in Ferroelectric Capacitor Contact Etching” published by the th inventors on May 10, 1999 at 1999 4th International Symposium on Plasma Process-Induced Damage, which correlates with the present invention and is incorporated herein by reference.
- The invention will be illustrated in detail by the following preferred embodiments with reference to the accompanying drawings.
- FIG. 1 is a graph showing electron energy distribution functions of pulsed-power plasma at some duty ratios, compared with electron energy distribution function of continuous wave plasma. The duty ratio means the ratio of voltage inputting time for forming pulsed-power plasma among entire plasma generating time.
- FIG. 2 is a graph showing electron energy distribution functions of pulsed-power plasma at some modulation frequencies, compared with that of continuous wave plasma.
- As shown in the results of FIGS. 1 and 2, the pulsed-power plasma can generate the less etching damage than the continuous wave (CW) plasma.
- FIG. 3 shows a fabrication method of a ferroelectric memory device in accordance with one embodiment of the present invention.
- First, a first interlayer-insulating
layer 11 is formed with SiO2 or the like over a semiconductor substrate (not shown) completed with the formation of transistor and the others (not shown). Then, aPt bottom electrode 12, anSBT layer 13 and aPt top electrode 14 are, in turn, formed on the first interlayer-insulating layer 11. At this time, theSBT layer 13 and thePt top electrode 14 are superimposed on a part of thePt bottom electrode 12. - Subsequently, a second interlayer-insulating
layer 15 with SiO2 or the like is formed with a thickness of about 5500Å over the entire structure. Aphotoresist pattern 16 to define the region of contact hole is then formed on the second interlayer-insulatinglayer 15. The second interlayer-insulating layer is then selectively etched with pulsed-power plasma using thephotoresist pattern 16 as an etching mask to form contact holes exposing thePt top electrode 14 and thePt bottom electrode 12. - At this time, the etching is performed with the conditions of a source power of 800 W, a bias power of 600 W, a pressure of 5 mTorr, a temperature of 40° C., a CF4 flow rate of 15 sccm, and an Ar flow rate of 15 sccm. The frequency for generating the pulsed-power plasma may range from 1 kHz to 100 kHz.
- Later, metal wires (not shown) are formed to connect with the
Pt top electrode 14 and thePt bottom electrode 12, respectively. - Meanwhile, though the above-described embodiment explains the present invention with an example of exposing all of the top and bottom electrodes, the present invention may be applied to the process to expose only the top electrode.
- FIG. 4 is a graph showing the ferroelectric polarization characteristics with input voltage at some modulation frequencies for generating the pulsed-power plasma. The ferroelectric characteristics such as
remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor. On the other hand, the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage. - FIG. 5 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some modulation frequencies for generating the pulsed-power plasma. As shown in FIG. 5, when the cumulative possibility is 50%, while the value of 2 Pr is about 9.2 μC/cm2 in case of continuous wave (CW) plasma, the value of 2 Pr in case of pulsed-power plasma is about 10.2 μC/cm2 with regardless of frequency. Accordingly, when the etching is performed with the input of the pulsed-power plasma, the value of 2 Pr is less decreased by about 1 μC/cm2.
- FIG. 6 is a graph showing the ferroelectric polarization characteristics with the input voltage at some duty ratios for generating pulsed-power plasma. The ferroelectric characteristics such as
remanent polarization 2 Pr and coercive voltage Vc at the pulsed-power mode is not changed from the values of initial capacitor. On the other hand, the hysteresis loop after CW contact etching is degraded greatly in term of polarization and coercive voltage. - FIG. 7 is a graph showing the cumulative possibility characteristics with the ferroelectric polarization at some duty ratios for generating the pulsed-power plasma. As shown in FIG. 7, when the cumulative possibility is 50%, while the value of 2 Pr is about 9.2 μC/cm2 in case of continuous wave (CW) plasma, the value of 2 Pr in case of pulsed-power plasma is about 10.4 μC/cm2 with regardless of frequency. Accordingly, when the etching is performed with the input of the pulsed-power plasma, the value of 2 Pr is less decreased by about 1.2 μC/cm2.
- The present invention is to etch the interlayer-insulating layer over the capacitor by using the pulsed-power plasma compared with the conventional continuous wave plasma. Accordingly, the present invention can reduce the etching damage of the ferroelectric layer with regardless of process window in consideration of the plasma properties. According to this, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.
- While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1019990025865A KR100321728B1 (en) | 1999-06-30 | 1999-06-30 | Method for forming feram by using plasma pulse |
KR1999-25865 | 1999-06-30 |
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US20020045279A1 true US20020045279A1 (en) | 2002-04-18 |
US6391659B1 US6391659B1 (en) | 2002-05-21 |
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Cited By (5)
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US11832451B1 (en) | 2021-08-06 | 2023-11-28 | Kepler Computing Inc. | High density ferroelectric random access memory (FeRAM) devices and methods of fabrication |
US11839070B1 (en) | 2021-12-14 | 2023-12-05 | Kepler Computing Inc. | High density dual encapsulation materials for capacitors and methods of fabrication |
US11854593B2 (en) | 2021-09-02 | 2023-12-26 | Kepler Computing Inc. | Ferroelectric memory device integrated with a transition electrode |
US11871583B2 (en) | 2021-09-02 | 2024-01-09 | Kepler Computing Inc. | Ferroelectric memory devices |
US11955512B1 (en) | 2021-12-14 | 2024-04-09 | Kepler Computing Inc. | Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6759339B1 (en) | 2002-12-13 | 2004-07-06 | Silicon Magnetic Systems | Method for plasma etching a microelectronic topography using a pulse bias power |
US7570028B2 (en) * | 2007-04-26 | 2009-08-04 | Advanced Energy Industries, Inc. | Method and apparatus for modifying interactions between an electrical generator and a nonlinear load |
KR101489326B1 (en) * | 2008-09-09 | 2015-02-11 | 삼성전자주식회사 | Method of processing a substrate |
US8716984B2 (en) | 2009-06-29 | 2014-05-06 | Advanced Energy Industries, Inc. | Method and apparatus for modifying the sensitivity of an electrical generator to a nonlinear load |
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US5424244A (en) * | 1992-03-26 | 1995-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
KR100322695B1 (en) * | 1995-03-20 | 2002-05-13 | 윤종용 | Method for manufacturing ferroelectric capacitor |
JPH0969615A (en) * | 1995-08-30 | 1997-03-11 | Sony Corp | Formation method for ferroelectric thin film and manufacturing method for capacitor structure of semiconductor element |
KR970077323A (en) * | 1996-05-13 | 1997-12-12 | 김광호 | Method for forming insulating film of ferroelectric memory device |
KR19990085671A (en) * | 1998-05-20 | 1999-12-15 | 윤종용 | Etching method of metal wiring to prevent damage of ferroelectric capacitor |
-
1999
- 1999-06-30 KR KR1019990025865A patent/KR100321728B1/en not_active IP Right Cessation
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Cited By (14)
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US11832451B1 (en) | 2021-08-06 | 2023-11-28 | Kepler Computing Inc. | High density ferroelectric random access memory (FeRAM) devices and methods of fabrication |
US11854593B2 (en) | 2021-09-02 | 2023-12-26 | Kepler Computing Inc. | Ferroelectric memory device integrated with a transition electrode |
US11942133B2 (en) | 2021-09-02 | 2024-03-26 | Kepler Computing Inc. | Pedestal-based pocket integration process for embedded memory |
US11871583B2 (en) | 2021-09-02 | 2024-01-09 | Kepler Computing Inc. | Ferroelectric memory devices |
US11844203B1 (en) | 2021-12-14 | 2023-12-12 | Kepler Computing Inc. | Conductive and insulative hydrogen barrier layer for memory devices |
US11844225B1 (en) | 2021-12-14 | 2023-12-12 | Kepler Computing Inc. | Dual hydrogen barrier layer for memory devices integrated with low density film for logic structures and methods of fabrication |
US11862517B1 (en) | 2021-12-14 | 2024-01-02 | Kepler Computing Inc. | Integrated trench and via electrode for memory device applications |
US11871584B1 (en) | 2021-12-14 | 2024-01-09 | Kepler Computing Inc. | Multi-level hydrogen barrier layers for memory applications |
US11869843B1 (en) | 2021-12-14 | 2024-01-09 | Kepler Computing Inc. | Integrated trench and via electrode for memory device applications and methods of fabrication |
US11839088B1 (en) | 2021-12-14 | 2023-12-05 | Kepler Computing Inc. | Integrated via and bridge electrodes for memory array applications and methods of fabrication |
US11869928B2 (en) | 2021-12-14 | 2024-01-09 | Kepler Computing Inc. | Dual hydrogen barrier layer for memory devices |
US11839070B1 (en) | 2021-12-14 | 2023-12-05 | Kepler Computing Inc. | High density dual encapsulation materials for capacitors and methods of fabrication |
US11955512B1 (en) | 2021-12-14 | 2024-04-09 | Kepler Computing Inc. | Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication |
US11961877B1 (en) | 2021-12-14 | 2024-04-16 | Kepler Computing Inc. | Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures |
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KR20010005076A (en) | 2001-01-15 |
KR100321728B1 (en) | 2002-01-26 |
US6391659B1 (en) | 2002-05-21 |
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