US20020039827A1 - Method for forming inner capacitor of semiconductor devices using oxide layers formed by the SACVD method - Google Patents

Method for forming inner capacitor of semiconductor devices using oxide layers formed by the SACVD method Download PDF

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US20020039827A1
US20020039827A1 US09/927,535 US92753501A US2002039827A1 US 20020039827 A1 US20020039827 A1 US 20020039827A1 US 92753501 A US92753501 A US 92753501A US 2002039827 A1 US2002039827 A1 US 2002039827A1
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layer
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Jai-Sun Roh
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Definitions

  • the present invention relates to a method for forming a semiconductor device and, more particularly, to a method for forming an inner capacitor of the semiconductor device.
  • FIG. 1 is a cross-sectional view illustrating a conventional inner capacitor in a semiconductor device.
  • a BPSG (Borophosphosilicate Glass) layer 18 is deposited on the resulting structure.
  • a planarization process is applied to the BPSG layer 18 with a flow and CMP (Chemical Mechanical Polishing) processes.
  • the nitride layer 21 is employed as an etching stopper and the SiH 4 -oxide layer 20 is employed to prevent the bowing phenomenon generated in sidewalls of a contact hole.
  • the reference numerals 14 , 15 and 17 denote sidewall spacers of the word lines, a BPSG layer and sidewall spacers of the bit lines, respectively.
  • a PSG (phosphosilicate glass) layer 22 is deposited on the resulting structure and the PSG layer 22 is selectively etched in order to expose the polysilicon contact plugs 19 .
  • a polysilicon layer 23 is formed in the contact holes for charge storage electrodes. The single polysilicon layer 23 is divided into a plurality of charge storage electrodes by the CMP process and a relatively wide surface area of charge storage electrodes is provided by the removal of the remaining PSG layer 22 .
  • the PSG layer 22 used as a sacrifice oxide layer is formed in the APCVD (Atmospheric Pressure Chemical Vapor Deposition) equipment having an injector 200 , which is in the form of a bar, as shown in FIG. 2.
  • the injector 200 has 49 injecting holes 201 which are arranged in a straight line. Since the PSG layer 22 is deposited on the semiconductor substrate mounted on a moving belt by the typical two-pass process while a source gas flows from the injecting holes 201 , there are some areas 301 vulnerable to the thickness uniformity of the PSG layer 22 as shown in FIG. 3.
  • the reference numeral 300 denotes a uniform thickness area. In the case where the PSG layer 22 is deposited at a thickness of approximately 11000 ⁇ , the PSG layer 22 has a non-uniformity of about 5%.
  • FIG. 4 is a schematic layout showing a charge storage electrode contact and a bit line contact, in which a charge storage electrode contact area 401 , a bit line contact area 402 and a charge storage electrode area 403 are shown.
  • the nitride layer 21 and the BPSG layer 18 may be etched in the area 301 because of the non-uniformity of thickness of the PSG layer 22 . Accordingly, this loss of the nitride layer 21 and the BPSG layer 18 causes an electrical interconnection (A) between the polysilicon layer 23 for the charge storage electrode and a bit line contact plug.
  • the loss of the BPSG layer 18 is caused by the loss of the nitride layer 21 and the SiH 4 -oxide layer 20 .
  • the SiH 4 -oxide layer 20 is formed on the BPSG layer 18 at a thickness of approximately 500-2000 ⁇ in order to prevent the bowing phenomenon in sidewalls of the contact holes, because the SiH 4 oxide layer 20 is hardly etched by a clearing solution that is applied to the contact holes.
  • the SiH 4 -oxide layer 20 is formed in a bulk layer by the PECVD (Plasma Enhanced CVD) processing chamber, the quality of the layer is not rigid and then the SiH 4 -oxide layer 20 may be lost with a loss of the upper layer.
  • the method for forming the conventional inner capacitor has a disadvantage in that the loss of the BPSG layer, the nitride layer and the SiH 4 -oxide layer under the sacrifice oxide layer (PSG) layer may occur based on the non-uniformity of thickness of the PSG layer thereon. Accordingly, this loss may cause a short between adjacent metal layers with a resulting failure of the semiconductor device.
  • PSG sacrifice oxide layer
  • a method for forming a charge storage electrode in a semiconductor device comprising the steps of forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate; forming a SACVD oxide layer on the interlayer insulation layer; forming contact holes for charge storage electrodes and bit lines by selectively etching the SACVD oxide layer and the interlayer insulation layer; forming contact plugs in the contact holes, thereby forming a resulting structure; forming a SACVD sacrifice oxide layer on the resulting structure; selectively etching the SACVD sacrifice oxide layer and exposing top surfaces of the contact plugs; forming a conducting layer electrically connected to the contact plugs; separating the conducting layer into a plurality of charge storage electrodes; and removing the SACVD sacrifice oxide layer.
  • FIG. 1 is a cross-sectional view illustrating a conventional inner capacitor in a semiconductor device
  • FIG. 2 is a top view of an injector in APCVD equipment according to the prior art
  • FIG. 3 is a top view showing a wafer on which a PSG layer is deposited according to the prior art
  • FIG. 4 is a schematic layout showing a charge storage electrode contact and a bit line contact according to the prior art
  • FIG. 5 is a cross-sectional view illustrating an inner capacitor in a semiconductor device according to the present invention.
  • FIG. 6 is a top view of a showerhead on SACVD (Sub-Atmospheric CVD) equipment.
  • SACVD Sub-Atmospheric CVD
  • FIG. 5 has the same inner capacitor structure as shown in FIG. 1 and the same processes as have already been described are also applicable to form an inner capacitor.
  • field oxide layers 110 , source/drain regions 120 , word lines 130 and bit lines 160 are formed in and on a semiconductor substrate 100 and a BPSG (Borophosphosilicate Glass) layer 180 is deposited on the resulting structure.
  • a planarization process is applied to the BPSG layer 180 with a flow process and a CMP process.
  • An oxide layer 205 such as an USG (undoped-silicate glass) layer, for preventing the bowing phenomenon generated in sidewalls of a contact hole is formed on the BPSG layer 180 by the SACVD (Sub-Atmospheric CVD) method and a nitride layer 210 is formed on the oxide layer 205 .
  • the oxide layer 205 formed by the SACVD method has a thickness of approximately 500-2000 ⁇ . Further, to increase the density of the oxide layer 205 , an additional thermal treatment may be carried out.
  • the nitride layer 210 is employed as an etching stopper and the reference numerals 140 , 150 and 170 denote sidewall spacers of the word lines, a BPSG layer and sidewall spacers of the bit lines, respectively.
  • a clearing process is carried out and polysilicon contact plugs 190 are formed within the contact holes; contact plugs for the bit lines may be defined simultaneously with the polysilicon contact plugs 190 for charge storage electrodes.
  • a PSG (phosphosilicate glass) layer 220 is deposited on the resulting structure and the PSG layer 220 is selectively etched in order to expose the polysilicon contact plugs 190 .
  • a polysilicon layer 230 is formed in the contact holes for charge storage electrodes. The single polysilicon layer 230 is divided into a plurality of charge storage electrodes by the CMP process and a relatively wide surface area of charge storage electrodes is provided by the removal of the PSG layer 220 .
  • the PSG layer 220 a sacrifice oxide layer, is formed by the SACVD (Sub-Atmospheric CVD) method and has a thickness of approximately 500-2000 ⁇ .
  • SACVD Sub-Atmospheric CVD
  • the detailed formulas for forming the PSG layer 220 in accordance with the present invention are as follows:
  • the oxide layer 205 and the PSG layer 220 according to the present invention are formed by the SACVD method and then the uniformity of the PSG layer 220 may be controlled to be below 1%.
  • the PSG layer in FIG. 1 is formed by the injection of a reactant gas produced by bubbling source gases, such as TEOS and TMPi (trimethylphosphate), with N 2 gas and then is formed by a heterogeneous reaction. Therefore, it is very difficult to obtain a uniform thickness throughout the PSG layer.
  • TEOS and TMPo are used as a source gas for the PSG layer 220 and a showerhead is used instead of bubbling N 2 gas. That is, the source gases are pre-mixed before the injection through the showerhead and thereafter the mixed gases are injected into the wafer so as to form the PSG layer 220 .
  • the deposition temperature is in a range of about 400° C. to 480° C. and this temperature is lower than the 530° C. required in the APCVD method. Accordingly, the SACVD method has an effect on the thermal budget required to form the PSG layer 220 .
  • FIG. 6 is a top view of the showerhead on the SACVD equipment.
  • the showerhead 600 has a plurality of injecting holes 601 evenly arranged in a radial manner so that the showerhead does not have an arrangement that might negatively impact the thickness uniformity of the PSG layer.
  • the oxide layer 205 formed by the SACVD method since there is no interface within the oxide layer 205 formed by the SACVD method, it has solid density twice as high as the SiH 4 -oxide layer formed by the PECVD method so that the loss of the lower layers of the oxide layer 205 may be prevented.
  • the present invention prevents the loss of the interlayer insulation layer, such as a BPSG layer, by improving the thickness uniformity of the PSG layer used as a sacrifice oxide layer, especially in semiconductor capacitor fabricating processes. Accordingly, the present invention prevents short circuiting between adjacent metal layers and thus increase the yield of the semiconductor devices.

Abstract

A method for forming an inner capacitor of a semiconductor device. The method comprises steps of forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate; forming a SACVD oxide layer on the interlayer insulation layer; forming contact holes for charge storage electrodes and bit lines by selectively etching the SACVD oxide layer and the interlayer insulation layer; forming contact plugs in the contact holes, thereby forming a resulting structure; forming a SACVD sacrifice oxide layer on the resulting structure; selectively etching the SACVD sacrifice oxide layer and exposing top surfaces of the contact plugs; forming a conducting layer electrically connected to the contact plugs; separating the conducting layer into a plurality of charge storage electrodes; and removing the SACVD sacrifice oxide layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method for forming a semiconductor device and, more particularly, to a method for forming an inner capacitor of the semiconductor device. [0001]
    • DESCRIPTION OF THE PRIOR ART
  • FIG. 1 is a cross-sectional view illustrating a conventional inner capacitor in a semiconductor device. As shown in FIG. 1, after forming [0002] field oxide layers 11, source/drain regions 12, word lines 13 and bit lines 16 in and on a semiconductor substrate 10, a BPSG (Borophosphosilicate Glass) layer 18, a SiH4-oxide layer 20 and a nitride layer 21 are deposited on the resulting structure. A planarization process is applied to the BPSG layer 18 with a flow and CMP (Chemical Mechanical Polishing) processes. Typically, the nitride layer 21 is employed as an etching stopper and the SiH4-oxide layer 20 is employed to prevent the bowing phenomenon generated in sidewalls of a contact hole. In FIG. 1, the reference numerals 14, 15 and 17 denote sidewall spacers of the word lines, a BPSG layer and sidewall spacers of the bit lines, respectively.
  • Subsequently, after forming contact holes for charge storage electrodes using masking and etching processes, a clearing process is carried out and [0003] polysilicon contact plugs 19 are formed within the contact holes. Typically, contact plugs for the bit lines are defined simultaneously with the polysilicon contact plugs for charge storage electrodes.
  • Next, a PSG (phosphosilicate glass) layer [0004] 22, as a sacrifice oxide layer, is deposited on the resulting structure and the PSG layer 22 is selectively etched in order to expose the polysilicon contact plugs 19. A polysilicon layer 23 is formed in the contact holes for charge storage electrodes. The single polysilicon layer 23 is divided into a plurality of charge storage electrodes by the CMP process and a relatively wide surface area of charge storage electrodes is provided by the removal of the remaining PSG layer 22.
  • In the conventional method for forming the inner capacitor, the PSG layer [0005] 22 used as a sacrifice oxide layer is formed in the APCVD (Atmospheric Pressure Chemical Vapor Deposition) equipment having an injector 200, which is in the form of a bar, as shown in FIG. 2. The injector 200 has 49 injecting holes 201 which are arranged in a straight line. Since the PSG layer 22 is deposited on the semiconductor substrate mounted on a moving belt by the typical two-pass process while a source gas flows from the injecting holes 201, there are some areas 301 vulnerable to the thickness uniformity of the PSG layer 22 as shown in FIG. 3. In FIG. 3, the reference numeral 300 denotes a uniform thickness area. In the case where the PSG layer 22 is deposited at a thickness of approximately 11000 Å, the PSG layer 22 has a non-uniformity of about 5%.
  • FIG. 4 is a schematic layout showing a charge storage electrode contact and a bit line contact, in which a charge storage [0006] electrode contact area 401, a bit line contact area 402 and a charge storage electrode area 403 are shown. When the PSG layer 22 is etched to expose the polysilicon layer 23 for the charge storage electrodes, the nitride layer 21 and the BPSG layer 18 may be etched in the area 301 because of the non-uniformity of thickness of the PSG layer 22. Accordingly, this loss of the nitride layer 21 and the BPSG layer 18 causes an electrical interconnection (A) between the polysilicon layer 23 for the charge storage electrode and a bit line contact plug.
  • The loss of the [0007] BPSG layer 18 is caused by the loss of the nitride layer 21 and the SiH4-oxide layer 20. The SiH4-oxide layer 20 is formed on the BPSG layer 18 at a thickness of approximately 500-2000 Å in order to prevent the bowing phenomenon in sidewalls of the contact holes, because the SiH4oxide layer 20 is hardly etched by a clearing solution that is applied to the contact holes. Typically, since the SiH4-oxide layer 20 is formed in a bulk layer by the PECVD (Plasma Enhanced CVD) processing chamber, the quality of the layer is not rigid and then the SiH4-oxide layer 20 may be lost with a loss of the upper layer.
  • As stated above, the method for forming the conventional inner capacitor has a disadvantage in that the loss of the BPSG layer, the nitride layer and the SiH[0008] 4-oxide layer under the sacrifice oxide layer (PSG) layer may occur based on the non-uniformity of thickness of the PSG layer thereon. Accordingly, this loss may cause a short between adjacent metal layers with a resulting failure of the semiconductor device.
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a method for improving the reliability of the semiconductor fabricating process which uses a sacrifice oxide layer. [0009]
  • It is another object of the present invention to provide a method for preventing short circuiting of a charge storage electrode in a semiconductor memory device. [0010]
  • In accordance with an aspect of the present invention, there is provided a method for forming a charge storage electrode in a semiconductor device, the method comprising the steps of forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate; forming a SACVD oxide layer on the interlayer insulation layer; forming contact holes for charge storage electrodes and bit lines by selectively etching the SACVD oxide layer and the interlayer insulation layer; forming contact plugs in the contact holes, thereby forming a resulting structure; forming a SACVD sacrifice oxide layer on the resulting structure; selectively etching the SACVD sacrifice oxide layer and exposing top surfaces of the contact plugs; forming a conducting layer electrically connected to the contact plugs; separating the conducting layer into a plurality of charge storage electrodes; and removing the SACVD sacrifice oxide layer.[0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which: [0012]
  • FIG. 1 is a cross-sectional view illustrating a conventional inner capacitor in a semiconductor device; [0013]
  • FIG. 2 is a top view of an injector in APCVD equipment according to the prior art; [0014]
  • FIG. 3 is a top view showing a wafer on which a PSG layer is deposited according to the prior art; [0015]
  • FIG. 4 is a schematic layout showing a charge storage electrode contact and a bit line contact according to the prior art; [0016]
  • FIG. 5 is a cross-sectional view illustrating an inner capacitor in a semiconductor device according to the present invention; and [0017]
  • FIG. 6 is a top view of a showerhead on SACVD (Sub-Atmospheric CVD) equipment.[0018]
    • DETAILED DESCRIPTION OF THE INVENTION
  • Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. [0019]
  • First, FIG. 5 has the same inner capacitor structure as shown in FIG. 1 and the same processes as have already been described are also applicable to form an inner capacitor. [0020]
  • Referring to FIG. 5, [0021] field oxide layers 110, source/drain regions 120, word lines 130 and bit lines 160 are formed in and on a semiconductor substrate 100 and a BPSG (Borophosphosilicate Glass) layer 180 is deposited on the resulting structure. A planarization process is applied to the BPSG layer 180 with a flow process and a CMP process. An oxide layer 205, such as an USG (undoped-silicate glass) layer, for preventing the bowing phenomenon generated in sidewalls of a contact hole is formed on the BPSG layer 180 by the SACVD (Sub-Atmospheric CVD) method and a nitride layer 210 is formed on the oxide layer 205. The oxide layer 205 formed by the SACVD method has a thickness of approximately 500-2000 Å. Further, to increase the density of the oxide layer 205, an additional thermal treatment may be carried out.
  • The [0022] nitride layer 210 is employed as an etching stopper and the reference numerals 140, 150 and 170 denote sidewall spacers of the word lines, a BPSG layer and sidewall spacers of the bit lines, respectively.
  • Subsequently, after forming contact holes for charge storage electrodes using masking and etching processes, a clearing process is carried out and [0023] polysilicon contact plugs 190 are formed within the contact holes; contact plugs for the bit lines may be defined simultaneously with the polysilicon contact plugs 190 for charge storage electrodes. Next, a PSG (phosphosilicate glass) layer 220, as a sacrifice oxide layer, is deposited on the resulting structure and the PSG layer 220 is selectively etched in order to expose the polysilicon contact plugs 190. A polysilicon layer 230 is formed in the contact holes for charge storage electrodes. The single polysilicon layer 230 is divided into a plurality of charge storage electrodes by the CMP process and a relatively wide surface area of charge storage electrodes is provided by the removal of the PSG layer 220.
  • Unlike the prior art, the [0024] PSG layer 220, a sacrifice oxide layer, is formed by the SACVD (Sub-Atmospheric CVD) method and has a thickness of approximately 500-2000 Å. The detailed formulas for forming the PSG layer 220 in accordance with the present invention are as follows:
  • Flow rate of He: 10000-14000 sccm; [0025]
  • Flow rate of O[0026] 3: 10000-14000 sccm;
  • Flow rate of TEOS(tetraethylorthosilicate): 900-1500 mg/m; [0027]
  • Flow rate of TEPo: 30-80 mg/m; [0028]
  • Temperature: 400-480° C.; and [0029]
  • Pressure: 100-300 Torr. [0030]
  • As stated above, the [0031] oxide layer 205 and the PSG layer 220 according to the present invention are formed by the SACVD method and then the uniformity of the PSG layer 220 may be controlled to be below 1%. In the case of the APCVD method for forming the conventional inner capacitor, the PSG layer in FIG. 1 is formed by the injection of a reactant gas produced by bubbling source gases, such as TEOS and TMPi (trimethylphosphate), with N2 gas and then is formed by a heterogeneous reaction. Therefore, it is very difficult to obtain a uniform thickness throughout the PSG layer.
  • In the present invention, TEOS and TMPo (trimethylborate) are used as a source gas for the [0032] PSG layer 220 and a showerhead is used instead of bubbling N2 gas. That is, the source gases are pre-mixed before the injection through the showerhead and thereafter the mixed gases are injected into the wafer so as to form the PSG layer 220. Also, the deposition temperature is in a range of about 400° C. to 480° C. and this temperature is lower than the 530° C. required in the APCVD method. Accordingly, the SACVD method has an effect on the thermal budget required to form the PSG layer 220.
  • FIG. 6 is a top view of the showerhead on the SACVD equipment. The [0033] showerhead 600 has a plurality of injecting holes 601 evenly arranged in a radial manner so that the showerhead does not have an arrangement that might negatively impact the thickness uniformity of the PSG layer.
  • Furthermore, since there is no interface within the [0034] oxide layer 205 formed by the SACVD method, it has solid density twice as high as the SiH4-oxide layer formed by the PECVD method so that the loss of the lower layers of the oxide layer 205 may be prevented.
  • As apparent from the above, the present invention prevents the loss of the interlayer insulation layer, such as a BPSG layer, by improving the thickness uniformity of the PSG layer used as a sacrifice oxide layer, especially in semiconductor capacitor fabricating processes. Accordingly, the present invention prevents short circuiting between adjacent metal layers and thus increase the yield of the semiconductor devices. [0035]
  • Although the preferred embodiments of the present invention have been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutes are possible, without departing from the scope and spirit of the present invention as described in the accompanying claims. [0036]

Claims (14)

What is claimed is:
1. A method for forming a charge storage electrode in a semiconductor device, the method comprising the steps of:
forming an interlayer insulation layer over a semiconductor substrate, wherein a plurality of layers to form semiconductor transistors are formed on the semiconductor substrate;
forming a SACVD oxide layer on the interlayer insulation layer;
forming contact holes for charge storage electrodes and bit lines by selectively etching the SACVD oxide layer and the interlayer insulation layer;
forming contact plugs in the contact holes, thereby forming a resulting structure;
forming a SACVD sacrifice oxide layer on the resulting structure;
selectively etching the SACVD sacrifice oxide layer and exposing top surfaces of the contact plugs;
forming a conducting layer electrically connected to the contact plugs;
separating the conducting layer into a plurality of charge storage electrodes; and
removing the SACVD sacrifice oxide layer.
2. The method as recited in claim 1, further comprising a step of applying a thermal treatment to the SACVD oxide layer in order to increase a density thereof.
3. The method as recited in claim 1, further comprising a step of forming a nitride layer on the SACVD oxide layer.
4. The method as recited in claim 1, wherein the SACVD oxide layer is a PSG (phosphosilicate glass) layer.
5. The method as recited in claim 4, wherein the PSG layer is formed by a SACVD equipment which includes a source gas injector having a plurality of injecting holes evenly arranged in a radial manner.
6. The method as recited in claim 5, wherein the PSG layer is formed by a mixed gas of He, O3, TEOS (tetraethylorthosilicate) and TMPo (trimethylborate).
7. The method as recited in claim 6, wherein a flow rate of each of He, O3, TEOS and TMPo is 10000-14000 sccm, 6000-10000 sccm, 900-1500 mg/m and 30-80 mg/m.
8. The method as recited in claim 6, wherein the PSG layer is formed at a temperature of approximately 400-480° C. and at a pressure of approximately 100-300 Torr.
9. The method as recited in claim 1, wherein the SACVD oxide layer is formed at a thickness of approximately 500-2000 Å.
10. The method as recited in claim 1, wherein the step of forming said SACVD oxide layer includes a step of injecting a pre-mixed source gas through a plurality of radially-arranged injecting holes of a SACVD equipment showerhead.
11. The method as recited in claim 10, wherein the step of forming said SACVD oxide layer is performed at a temperature of approximately 400-480° C. and at a pressure of approximately 100-300 Torr.
12. The method as recited in claim 10, wherein said pre-mixed source gas includes TEOS and TMPo.
13. The method as recited in claim 12, further comprising He and O3.
14. The method as recited in claim 13, wherein a flow rate of each of He, O3, TEOS and TMPo is 10000-14000 sccm, 6000-10000 sccm, 900-1500 mg/m and 30-80 mg/m.
US09/927,535 2000-10-04 2001-08-13 Method for forming inner capacitor of semiconductor devices using oxide layers formed through a plurality of radially-arranged injecting holes of a SACVD equipment showerhead Expired - Lifetime US6423610B1 (en)

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KR10-2000-0058275A KR100533969B1 (en) 2000-10-04 2000-10-04 A method for forming storage node of inner capacitor
KR00-58275 2000-10-04
KR2000-58275 2000-10-04

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003582A1 (en) * 2004-06-30 2006-01-05 Hynix Semiconductor Inc. Method for fabricating semiconductor device
CN108598002A (en) * 2018-05-15 2018-09-28 长江存储科技有限责任公司 MOS transistor and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3305901B2 (en) * 1994-12-14 2002-07-24 東芝マイクロエレクトロニクス株式会社 Method for manufacturing semiconductor device
JPH10189898A (en) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5736450A (en) * 1997-06-18 1998-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a cylindrical capacitor
KR19990065141A (en) * 1998-01-08 1999-08-05 윤종용 Self-aligned contact hole formation method
US6037220A (en) * 1998-07-24 2000-03-14 Vanguard International Semiconductor Corporation Method of increasing the surface area of a DRAM capacitor structure via the use of hemispherical grained polysilicon
US6174808B1 (en) * 1999-08-04 2001-01-16 Taiwan Semiconductor Manufacturing Company Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060003582A1 (en) * 2004-06-30 2006-01-05 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US7316973B2 (en) * 2004-06-30 2008-01-08 Hynix Semiconductor, Inc. Method for fabricating semiconductor device
CN108598002A (en) * 2018-05-15 2018-09-28 长江存储科技有限责任公司 MOS transistor and its manufacturing method

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