US20020000625A1 - Semiconductor memory having buried digit lines - Google Patents
Semiconductor memory having buried digit lines Download PDFInfo
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- US20020000625A1 US20020000625A1 US09/318,734 US31873499A US2002000625A1 US 20020000625 A1 US20020000625 A1 US 20020000625A1 US 31873499 A US31873499 A US 31873499A US 2002000625 A1 US2002000625 A1 US 2002000625A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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- the present invention relates to a semiconductor memory and a method for fabricating the same, and more specifically to a structure of a semiconductor memory such as a large-storage-capacity NOR type mask ROM, having buried digit lines, and a method for fabricating the same.
- FIG. 3 is a plan view for illustrating a general cell layout in the NOR type mask ROM having buried digit lines.
- a plurality of buried digit lines 8 and active regions 6 are alternately located.
- a plurality of word lines 13 extend orthogonally to the buried digit lines 8 .
- a region surrounded by a dotted line in FIG. 3 corresponds to a unitary cell.
- “L” indicates a channel length
- “W” indicates a channel width.
- FIGS. 4A to 4 D are diagrammatic sectional views taken along the line A-A in FIG. 3 for illustrating the prior art method.
- an oxide film 4 is formed on a P-type silicon substrate 1 , and a photoresist film 5 is formed on the oxide film 4 , and then patterned to have an opening at a region which is positioned between each pair of adjacent active regions 6 and where a buried digit line is to be formed in future.
- N-type impurity for example, arsenic
- buried digit lines 8 are formed.
- oxidation is carried out so that a gate oxide film 2 is formed on the surface of the substrate 1 as shown in FIG. 4C. Further, a polysilicon film 3 and a tungsten silicide film 11 are formed on the whole surface as shown in FIG. 4D, and then, are selectively removed so that the word line 13 constituted of a polycide gate electrode 12 formed of the tungsten silicide film 11 and the polysilicon film 3 , is formed on the active region 6 .
- JP-A- 05-003303 an English abstract of JP-A- 05-003303 is available and the content of the English abstract is incorporated by reference in its entirety into this application).
- NOR type mask ROM a layer resistance of the buried digit line is desired to be maintained even if the cell size is reduced, from the viewpoint of a demand in a circuit for ensuring a high speed operation margin.
- a margin of the channel length in a cell transistor (Lmin) should be ensured.
- the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor are a tradeoff relation against each other. In the prior art, therefore, it is difficult to reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor.
- Another object of the present invention is to provide a semiconductor memory having buried digit lines, which can reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin of the cell transistor, and a method for fabricating the same.
- a semiconductor memory comprising a semiconductor substrate having a principal surface, a gate electrode which is formed on a gate insulator film formed in an active region on the principal surface of the semiconductor substrate and which is formed of a semiconductor layer and a conducting layer, grooves formed in self alignment with the gate electrode and to penetrate the inside of the semiconductor substrate, a buried digit line formed of a diffused layer which is formed within each of the grooves and which is of a conductivity type opposite to that of the semiconductor substrate, a first insulating film covering a surface of each of the grooves and at least a portion of a side surface of the gate electrode, a second insulating film filled up in the grooves and having a high reflow property, and a word line formed on the principal surface of the semiconductor substrate to extend orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.
- the grooves are formed to have a V-shape in a cross-section, even if the cell area is reduced, it is possible to simultaneously realize at least the maintaining and preferably the reducing of the layer resistance of the buried digit line, and the ensuring of the gate length margin (Lmin) of the cell transistor.
- the grooves can be formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, or alternatively by patterning an insulating film formed on the semiconductor layer and performing an etching using the patterned insulating film as a mask.
- the first insulating film covering a surface of each of the grooves and at least the portion of the side surface of the gate electrode has an etching rate smaller than that of the second insulating film having a high reflow property and filling up the grooves.
- the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate can be carded out by a slant rotating ion implantation.
- the grooves are formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, and in the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate, the impurity is introduced into the semiconductor layer which was not doped the impurity to have the conductivity type opposite to that of the semiconductor substrate.
- the semiconductor layer is formed of a polysilicon film or an amorphous silicon film.
- the semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate when the semiconductor layer is formed, or alternatively, in a later step, the semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate.
- the conducting layer can be formed of a refractory metal film such as a tungsten silicide film, or alternatively can be formed of a polysilicon film or an amorphous silicon film.
- FIGS. 1A to 1 G are diagrammatic sectional views of the NOR type mask ROM having buried digit lines, for illustrating a first embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM;
- FIGS. 2A to 2 G are diagrammatic sectional views of the NOR type mask ROM having buried digit lines, for illustrating a second embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM;
- FIG. 3 is a plan view for illustrating a general cell layout in the NOR type mask ROM having buried digit lines.
- FIGS. 4A to 4 D are diagrammatic sectional views for illustrating a method in accordance with the prior art for fabricating the NOR type mask ROM having buried digit lines.
- FIGS 1 A to 1 G are diagrammatic sectional views for illustrating a first embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM having buried digit lines
- FIG. 1G shows a sectional structure of the NOR type mask ROM fabricated in accordance with that method, and corresponds to a sectional view taken along the line A-A in FIG. 3.
- the first embodiment of the NOR type mask ROM in accordance with the present invention having buried digit lines includes a gate electrode 12 which is located on a gate oxide film 2 formed in an active region 6 on a principal surface of a P-type silicon substrate 1 and which is formed of a polysilicon film 3 and a tungsten silicide film 11 .
- the NOR type mask ROM further includes grooves 7 having a rectangular vertical cross-sectional shape, formed to penetrate the inside of the P-type silicon substrate in a self-alignment with the active regions 6 so that each of the active regions 6 is confined between each pair of adjacent grooves.
- the NOR type mask ROM includes a buried digit line 8 formed of an N+ diffused layer formed at an inner surface of each groove 7 , a CVD (chemical vapor deposition) oxide film 9 formed to cover the buried digit line 8 in each groove 7 and at least a portion of a side surface of the gate electrode 12 , and a BPSG (borophosphosilicate glass) film 10 filled up in each groove 7 and having an etching rate higher than that of the CVD oxide film 9 .
- CVD chemical vapor deposition
- BPSG borophosphosilicate glass
- the NOR type mask ROM includes a word line 13 which is orthogonal to the grooves 7 (namely, the buried digit lines 8 ) and which is constituted of an interconnection layer formed, on each active region, of a polycide gate electrode 12 composed of the polysilicon film 3 and the tungsten silicide film 11 , and on each groove 7 , of only the tungsten silicide film 11 .
- FIGS. 1A to 1 G a first embodiment of the method in accordance with the present invention for fabricating the first embodiment of the NOR type mask ROM in accordance with the present invention, will be described with reference to FIGS. 1A to 1 G.
- the gate oxide film 2 having a thickness of 0.005 ⁇ m to 0.03 ⁇ m, the polysilicon film 3 having a thickness of 0.1 ⁇ m to 0.3 ⁇ m, and an oxide film 4 having a thickness of 0.1 ⁇ m to 0.34 ⁇ m, are formed on the principal surface of the P-type silicon substrate 1 in the named order.
- the oxide film 4 , the polysilicon film 3 and the gate oxide film 2 are etched in the named order.
- the photoresist film 5 is removed, as shown in FIG. 1C, the P-type silicon substrate 1 is etched using the patterned oxide film 4 as a mask, so that the grooves 7 having a width of 0.2 ⁇ m to 0.5 ⁇ m and having a rectangular vertical cross-sectional shape are formed in buried digit line formation regions located and separated to put one active region 6 between each pair of adjacent buried digit line formation regions.
- the grooves 7 can be formed using the patterned photoresist film 5 as a mask, without forming the oxide film 4 .
- an N-type impurity for example, arsenic
- an N-type impurity for example, arsenic
- a slant rotating ion implantation under an energy of 40 keV to 100 keV and a dose of 1 ⁇ 10 14 /cm 2 to 6 ⁇ 10 15 /cm 2 , so that a buried digit line 8 is formed at an inner surface of each groove 7 .
- the CVD oxide film 9 having a thickness of 1.0 ⁇ m to 0.3 ⁇ m and the BPSG oxide film 10 having a thickness of 0.2 ⁇ m to 1.0 ⁇ m, are formed on the P-type silicon substrate 1 in the named order, and an annealing is carried out for 5 minutes to 50 minutes in a nitrogen atmosphere of 800° C. to 950° C., so that the grooves 7 are filled up with the BPSG film 10 and the surface of the substrate 1 (namely, the surface of the BPSG film 10 ) is planarized.
- an etching-back is carried out by a dry etching using the polysilicon film 3 as a stopper, so that the CVD oxide film 9 and the BPSG oxide film 10 are left only within the grooves 7 .
- the etch rate of the CVD oxide film 9 is smaller than that of the BPSG oxide film 10 , even if the etching-back becomes an over-etching, the P-type silicon substrate 1 is never exposed at the side surface of the grooves 7 .
- the tungsten silicide film 11 is formed on the whole surface. Thereafter, the tungsten silicide film 11 and the polysilicon film 3 are selectively partially removed to form the word lines 13 each of which extends on the surface of the P-type, silicon substrate 1 orthogonally to the grooves 7 and each of which is constituted of an interconnection layer formed, on each active region 6 , of the polycide gate electrode 12 composed of the polysilicon film 3 and the tungsten silicide film 11 , and on each groove 7 , of only the tungsten silicide film 11 .
- FIGS. 2A to 2 G are diagrammatic sectional views for illustrating a second embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM having buried digit lines
- FIG. 2G shows a sectional structure of the NOR type mask ROM fabricated in accordance with that method, and corresponds to a sectional view taken along the line A-A in FIG. 3.
- the second embodiment of the NOR type mask ROM in accordance with the present invention having buried digit lines includes a gate electrode 12 which is located on a gate oxide film 2 formed in an active region 6 on a principal surface of a P-type silicon substrate 1 and which is formed of a polysilicon film 3 and a tungsten silicide film 11 .
- the NOR type mask ROM further includes grooves 7 A having a triangular vertical cross-sectional shape having a tapering bottom end (V-shaped groove), formed to penetrate the inside of the P-type silicon substrate in a self-alignment with the active regions 6 so that each of the active regions 6 is confined between each pair of adjacent grooves.
- the NOR type mask ROM includes a buried digit line 8 formed of an N + diffused layer formed at an inner surface of each groove 7 A, a CVD oxide film 9 formed to cover the buried digit line 8 in each groove 7 A and at least a portion of a side surface of the gate electrode 12 , and a BPSG film 10 filled up in each groove 7 A and having an etching rate higher than that of the CVD oxide film 9 .
- the NOR type mask ROM includes a word line 13 which is orthogonal to the grooves 7 A (namely, the buried digit lines 8 ) and which is constituted of an interconnection layer formed, on each active region, of a polycide gate electrode 12 composed of the polysilicon film 3 and the tungsten silicide film 11 , and on each groove 7 A, of only the tungsten silicide film 11 .
- the gate oxide film 2 having a thickness of 0.005 ⁇ m to 0.03 ⁇ m, the polysilicon film 3 having a thickness of 0.1 ⁇ m to 0.3 ⁇ m, and an oxide film 4 having a thickness of 0.1 ⁇ m to 0.3 ⁇ m, are formed on the principal surface of the P-type silicon substrate 1 in the named order.
- the oxide film 4 , the polysilicon film 3 and the gate oxide film 2 are etched in the named order.
- the photoresist film 5 is removed, as shown in FIG. 2C, the P-type silicon substrate 1 is etched using the patterned oxide film 4 as a mask, so that the V-shaped grooves 7 A having a width of 0.2 ⁇ m to 0.5 ⁇ m are formed in buried digit line formation regions located and separated to put one active region 6 between each pair of adjacent buried digit line formation regions.
- the grooves 7 A can be formed using the patterned photoresist film 5 as a mask, without forming the oxide film 4 , similarly to the first embodiment.
- an N-type impurity for example, arsenic
- an N-type impurity for example, arsenic
- an implanting angle of 0 degree under an energy of 40 keV to 100 keV and a dose of 1 ⁇ 10 14 /cm 2 to 6 ⁇ 10 15 /cm 2 , so that a buried digit line 8 is formed at an inner surface of each groove 7 A.
- the CVD oxide film 9 having a thickness of 0.1 ⁇ m to 0.3 ⁇ m and the BPSG oxide film 10 having a thickness of 0.2 ⁇ m to 1.0 ⁇ m are formed on the P-type silicon substrate 1 in the named order, and an annealing is carried out for 5 minutes to 50 minutes in a nitrogen atmosphere of 800° C. to 950° C., so that the grooves 7 A are filled up with the BPSG film 10 and the surface of the substrate 1 (namely, the surface of the BPSG film 10 ) is planarized.
- an etching-back is carried out by a dry etching using the polysilicon film 3 as a stopper, so that the CVD oxide film 9 and the BPSG oxide film 10 are left only within the grooves 7 A.
- the etch rate of the CVD oxide film 9 is smaller than that of the BPSG oxide film 10 , even if the etching-back becomes an over-etching, the P-type silicon substrate 1 is never exposed at the side surface of the grooves 7 A.
- the tungsten silicide film 11 is formed on the whole surface. Thereafter, the tungsten silicide film 11 and the polysilicon film 3 are selectively partially removed to form the word lines 13 each of which extends on the surface of the P-type silicon substrate 1 orthogonally to the grooves 7 A and each of which is constituted of an interconnection layer formed, on each active region 6 , of the polycide gate electrode 12 composed of the polysilicon film 3 and the tungsten silicide film 11 , and on each groove 7 A, of only the tungsten silicide film 11 .
- the whole of the inner surface of the groove 7 A formed in the P-type silicon substrate 1 can be used for the buried digit line.
- the groove 7 A is a V-shape in a vertical cross-section, the slant rotating ion implantation is no longer necessary in the N-type impurity implantation for forming the buried digit line 8 at the inner surface of the grooves 7 , and also, the deeper the level along the V-shaped groove becomes, a spacing between each pair of adjacent buried digit lines becomes larger, so that it becomes possible to suppress a punch-through at a deep position, which cannot be controlled by the polycide gate electrode 12 . Therefore, even if the cell area is reduced, the second embodiment can simultaneously realize at least the maintaining and preferably the reducing of the layer resistance of the buried digit line, and the ensuring of the gate length margin (Lmin) of the cell transistor.
- the gate length margin (Lmin) of the cell transistor can be ensured.
- the reason for this is that, since the groove is a V-shape in a vertical cross-section, it is possible to avoid the punch-trough between a source and a drain at a deep position.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor memory and a method for fabricating the same, and more specifically to a structure of a semiconductor memory such as a large-storage-capacity NOR type mask ROM, having buried digit lines, and a method for fabricating the same.
- 2. Description of Related Art
- Now, a prior art will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view for illustrating a general cell layout in the NOR type mask ROM having buried digit lines. A plurality of buried
digit lines 8 andactive regions 6 are alternately located. A plurality ofword lines 13 extend orthogonally to the burieddigit lines 8. A region surrounded by a dotted line in FIG. 3 corresponds to a unitary cell. In FIG. 3, “L” indicates a channel length, and “W” indicates a channel width. - Next, a method in accordance with the prior art for fabricating the NOR type mask ROM having buried digit lines will be described with reference to FIGS. 4A to4D, which are diagrammatic sectional views taken along the line A-A in FIG. 3 for illustrating the prior art method.
- As shown in FIG. 4A, an
oxide film 4 is formed on a P-type silicon substrate 1, and aphotoresist film 5 is formed on theoxide film 4, and then patterned to have an opening at a region which is positioned between each pair of adjacentactive regions 6 and where a buried digit line is to be formed in future. Then, as shown in FIG. 4B, N-type impurity, for example, arsenic, is implanted into thesubstrate 1 using the patternedphotoresist film 5 as a mask. As a result, burieddigit lines 8 are formed. After thephotoresist film 5 and theoxide film 4 are removed, oxidation is carried out so that agate oxide film 2 is formed on the surface of thesubstrate 1 as shown in FIG. 4C. Further, apolysilicon film 3 and atungsten silicide film 11 are formed on the whole surface as shown in FIG. 4D, and then, are selectively removed so that theword line 13 constituted of apolycide gate electrode 12 formed of thetungsten silicide film 11 and thepolysilicon film 3, is formed on theactive region 6. - Incidentally, an example of the NOR type mask ROM is disclosed by Japanese Patent Application Pre-examination Publication No. JP-A-05-003303 (an English abstract of JP-A-05-003303 is available and the content of the English abstract is incorporated by reference in its entirety into this application).
- In the above mentioned NOR type mask ROM, a layer resistance of the buried digit line is desired to be maintained even if the cell size is reduced, from the viewpoint of a demand in a circuit for ensuring a high speed operation margin. On the other hand, a margin of the channel length in a cell transistor (Lmin) should be ensured. For this purpose, it is desirable to reduce the dose of the N-type impurity in order to suppress a lateral diffusion. However, this results in an increased layer resistance of the buried digit line. Namely, the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor are a tradeoff relation against each other. In the prior art, therefore, it is difficult to reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor.
- Accordingly, it is an object of the present invention to provide a semiconductor memory having a buried digit line, which has overcome the above mentioned problem of the prior art, and a method for fabricating the same.
- Another object of the present invention is to provide a semiconductor memory having buried digit lines, which can reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin of the cell transistor, and a method for fabricating the same.
- The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor memory comprising a semiconductor substrate having a principal surface, a gate electrode which is formed on a gate insulator film formed in an active region on the principal surface of the semiconductor substrate and which is formed of a semiconductor layer and a conducting layer, grooves formed in self alignment with the gate electrode and to penetrate the inside of the semiconductor substrate, a buried digit line formed of a diffused layer which is formed within each of the grooves and which is of a conductivity type opposite to that of the semiconductor substrate, a first insulating film covering a surface of each of the grooves and at least a portion of a side surface of the gate electrode, a second insulating film filled up in the grooves and having a high reflow property, and a word line formed on the principal surface of the semiconductor substrate to extend orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.
- According to another aspect of the present invention, there is provided a method for fabricating a semiconductor memory, comprising the steps of:
- forming a semiconductor layer on a gate insulator film formed on a principal surface of a semiconductor substrate;
- forming grooves to penetrate the inside of the semiconductor substrate in buried digit line formation regions which locate an active region between each pair of adjacent buried digit line formation regions;
- introducing impurity of a conductivity type opposite to that of the semiconductor substrate, into at least a surface of the grooves in the semiconductor substrate;
- depositing a first insulating film on the semiconductor substrate;
- depositing a second insulating film having a high reflow property, to fill up the grooves having the surface covered with the first insulating film, and to planarize a surface of the semiconductor substrate;
- removing the first insulating film and the second insulating film to allow the first insulating film and the second insulating film to remain only within the grooves;
- forming a conducting layer on the semiconductor substrate; and
- selectively partially removing the conducting layer and the semiconductor layer to form a word line extending on the principal surface of the semiconductor substrate orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.
- With the above mentioned arrangement, even if the cell size is reduced, it is possible at least to maintain the layer resistance of the buried digit line.
- In addition, if the grooves are formed to have a V-shape in a cross-section, even if the cell area is reduced, it is possible to simultaneously realize at least the maintaining and preferably the reducing of the layer resistance of the buried digit line, and the ensuring of the gate length margin (Lmin) of the cell transistor.
- The grooves can be formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, or alternatively by patterning an insulating film formed on the semiconductor layer and performing an etching using the patterned insulating film as a mask.
- Preferably, the first insulating film covering a surface of each of the grooves and at least the portion of the side surface of the gate electrode, has an etching rate smaller than that of the second insulating film having a high reflow property and filling up the grooves.
- In addition, the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate, can be carded out by a slant rotating ion implantation.
- Alternatively, the grooves are formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, and in the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate, the impurity is introduced into the semiconductor layer which was not doped the impurity to have the conductivity type opposite to that of the semiconductor substrate.
- Furthermore, the semiconductor layer is formed of a polysilicon film or an amorphous silicon film. The semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate when the semiconductor layer is formed, or alternatively, in a later step, the semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate.
- In addition, the conducting layer can be formed of a refractory metal film such as a tungsten silicide film, or alternatively can be formed of a polysilicon film or an amorphous silicon film.
- The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
- FIGS. 1A to1G are diagrammatic sectional views of the NOR type mask ROM having buried digit lines, for illustrating a first embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM;
- FIGS. 2A to2G are diagrammatic sectional views of the NOR type mask ROM having buried digit lines, for illustrating a second embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM;
- FIG. 3 is a plan view for illustrating a general cell layout in the NOR type mask ROM having buried digit lines; and
- FIGS. 4A to4D are diagrammatic sectional views for illustrating a method in accordance with the prior art for fabricating the NOR type mask ROM having buried digit lines.
- In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
- FIGS1A to 1G are diagrammatic sectional views for illustrating a first embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM having buried digit lines, and FIG. 1G shows a sectional structure of the NOR type mask ROM fabricated in accordance with that method, and corresponds to a sectional view taken along the line A-A in FIG. 3.
- As shown in FIG. 1G, the first embodiment of the NOR type mask ROM in accordance with the present invention having buried digit lines includes a
gate electrode 12 which is located on agate oxide film 2 formed in anactive region 6 on a principal surface of a P-type silicon substrate 1 and which is formed of apolysilicon film 3 and atungsten silicide film 11. The NOR type mask ROM further includesgrooves 7 having a rectangular vertical cross-sectional shape, formed to penetrate the inside of the P-type silicon substrate in a self-alignment with theactive regions 6 so that each of theactive regions 6 is confined between each pair of adjacent grooves. In addition, the NOR type mask ROM includes a burieddigit line 8 formed of an N+ diffused layer formed at an inner surface of eachgroove 7, a CVD (chemical vapor deposition)oxide film 9 formed to cover the burieddigit line 8 in eachgroove 7 and at least a portion of a side surface of thegate electrode 12, and a BPSG (borophosphosilicate glass)film 10 filled up in eachgroove 7 and having an etching rate higher than that of theCVD oxide film 9. Moreover, the NOR type mask ROM includes aword line 13 which is orthogonal to the grooves 7 (namely, the buried digit lines 8) and which is constituted of an interconnection layer formed, on each active region, of apolycide gate electrode 12 composed of thepolysilicon film 3 and thetungsten silicide film 11, and on eachgroove 7, of only thetungsten silicide film 11. - Now, a first embodiment of the method in accordance with the present invention for fabricating the first embodiment of the NOR type mask ROM in accordance with the present invention, will be described with reference to FIGS. 1A to1G.
- As shown in FIG. 1A, the
gate oxide film 2 having a thickness of 0.005 μm to 0.03 μm, thepolysilicon film 3 having a thickness of 0.1 μm to 0.3 μm, and anoxide film 4 having a thickness of 0.1 μm to 0.34 μm, are formed on the principal surface of the P-type silicon substrate 1 in the named order. - As shown in FIG. 1B, by using a patterned
photoresist film 5 as a mask, theoxide film 4, thepolysilicon film 3 and thegate oxide film 2 are etched in the named order. After thephotoresist film 5 is removed, as shown in FIG. 1C, the P-type silicon substrate 1 is etched using the patternedoxide film 4 as a mask, so that thegrooves 7 having a width of 0.2 μm to 0.5 μm and having a rectangular vertical cross-sectional shape are formed in buried digit line formation regions located and separated to put oneactive region 6 between each pair of adjacent buried digit line formation regions. After thepolysilicon film 3 is formed, thegrooves 7 can be formed using the patternedphotoresist film 5 as a mask, without forming theoxide film 4. - Thereafter, as shown in FIG. 1D, an N-type impurity, for example, arsenic, is implanted on the whole surface of the
silicon substrate 1 by a slant rotating ion implantation under an energy of 40 keV to 100 keV and a dose of 1×1014/cm2 to 6×1015/cm2, so that a burieddigit line 8 is formed at an inner surface of eachgroove 7. - As shown in FIG. 1E, the
CVD oxide film 9 having a thickness of 1.0 μm to 0.3 μm and theBPSG oxide film 10 having a thickness of 0.2 μm to 1.0 μm, are formed on the P-type silicon substrate 1 in the named order, and an annealing is carried out for 5 minutes to 50 minutes in a nitrogen atmosphere of 800° C. to 950° C., so that thegrooves 7 are filled up with theBPSG film 10 and the surface of the substrate 1 (namely, the surface of the BPSG film 10) is planarized. - As shown in FIG. 1F, an etching-back is carried out by a dry etching using the
polysilicon film 3 as a stopper, so that theCVD oxide film 9 and theBPSG oxide film 10 are left only within thegrooves 7. In this etching-back process, since the etch rate of theCVD oxide film 9 is smaller than that of theBPSG oxide film 10, even if the etching-back becomes an over-etching, the P-type silicon substrate 1 is never exposed at the side surface of thegrooves 7. - As shown in FIG. 1G, the
tungsten silicide film 11 is formed on the whole surface. Thereafter, thetungsten silicide film 11 and thepolysilicon film 3 are selectively partially removed to form the word lines 13 each of which extends on the surface of the P-type,silicon substrate 1 orthogonally to thegrooves 7 and each of which is constituted of an interconnection layer formed, on eachactive region 6, of thepolycide gate electrode 12 composed of thepolysilicon film 3 and thetungsten silicide film 11, and on eachgroove 7, of only thetungsten silicide film 11. - As mentioned above, in the first embodiment of the NOR type mask ROM in accordance with the present invention, since the whole of the inner surface of the
groove 7 formed in the P-type silicon substrate 1 can be used for the buried digit line, even if the cell area is reduced, it is possible at least to maintain and preferably to reduce the layer resistance of the buried digit lines, differently from the prior art. - FIGS. 2A to2G are diagrammatic sectional views for illustrating a second embodiment of the method in accordance with the present invention for fabricating the NOR type mask ROM having buried digit lines, and FIG. 2G shows a sectional structure of the NOR type mask ROM fabricated in accordance with that method, and corresponds to a sectional view taken along the line A-A in FIG. 3.
- As shown in FIG. 2G, the second embodiment of the NOR type mask ROM in accordance with the present invention having buried digit lines includes a
gate electrode 12 which is located on agate oxide film 2 formed in anactive region 6 on a principal surface of a P-type silicon substrate 1 and which is formed of apolysilicon film 3 and atungsten silicide film 11. The NOR type mask ROM further includesgrooves 7A having a triangular vertical cross-sectional shape having a tapering bottom end (V-shaped groove), formed to penetrate the inside of the P-type silicon substrate in a self-alignment with theactive regions 6 so that each of theactive regions 6 is confined between each pair of adjacent grooves. In addition, the NOR type mask ROM includes a burieddigit line 8 formed of an N+ diffused layer formed at an inner surface of eachgroove 7A, aCVD oxide film 9 formed to cover the burieddigit line 8 in eachgroove 7A and at least a portion of a side surface of thegate electrode 12, and aBPSG film 10 filled up in eachgroove 7A and having an etching rate higher than that of theCVD oxide film 9. Moreover, the NOR type mask ROM includes aword line 13 which is orthogonal to thegrooves 7A (namely, the buried digit lines 8) and which is constituted of an interconnection layer formed, on each active region, of apolycide gate electrode 12 composed of thepolysilicon film 3 and thetungsten silicide film 11, and on eachgroove 7A, of only thetungsten silicide film 11. - Now, a second embodiment of the method in accordance with the present invention for fabricating the second embodiment of the NOR type mask ROM in accordance with the present invention, will be described with reference to FIGS. 2A to2G.
- As shown in FIG. 2A, the
gate oxide film 2 having a thickness of 0.005 μm to 0.03 μm, thepolysilicon film 3 having a thickness of 0.1 μm to 0.3 μm, and anoxide film 4 having a thickness of 0.1 μm to 0.3 μm, are formed on the principal surface of the P-type silicon substrate 1 in the named order. - As shown in FIG. 2B, by using a patterned
photoresist film 5 as a mask, theoxide film 4, thepolysilicon film 3 and thegate oxide film 2 are etched in the named order. After thephotoresist film 5 is removed, as shown in FIG. 2C, the P-type silicon substrate 1 is etched using the patternedoxide film 4 as a mask, so that the V-shapedgrooves 7A having a width of 0.2 μm to 0.5 μm are formed in buried digit line formation regions located and separated to put oneactive region 6 between each pair of adjacent buried digit line formation regions. After thepolysilicon film 3 is formed, thegrooves 7A can be formed using the patternedphotoresist film 5 as a mask, without forming theoxide film 4, similarly to the first embodiment. - Thereafter, as shown in FIG. 2D, an N-type impurity, for example, arsenic, is implanted on the whole surface of the
silicon substrate 1 by an implantation at an implanting angle of 0 degree under an energy of 40 keV to 100 keV and a dose of 1×1014/cm2 to 6×1015/cm2, so that a burieddigit line 8 is formed at an inner surface of eachgroove 7A. - As shown in FIG. 2E, the
CVD oxide film 9 having a thickness of 0.1 μm to 0.3 μm and theBPSG oxide film 10 having a thickness of 0.2 μm to 1.0 μm, are formed on the P-type silicon substrate 1 in the named order, and an annealing is carried out for 5 minutes to 50 minutes in a nitrogen atmosphere of 800° C. to 950° C., so that thegrooves 7A are filled up with theBPSG film 10 and the surface of the substrate 1 (namely, the surface of the BPSG film 10) is planarized. - As shown in FIG. 2F, an etching-back is carried out by a dry etching using the
polysilicon film 3 as a stopper, so that theCVD oxide film 9 and theBPSG oxide film 10 are left only within thegrooves 7A. In this etching-back process, since the etch rate of theCVD oxide film 9 is smaller than that of theBPSG oxide film 10, even if the etching-back becomes an over-etching, the P-type silicon substrate 1 is never exposed at the side surface of thegrooves 7A. - As shown in FIG. 2G, the
tungsten silicide film 11 is formed on the whole surface. Thereafter, thetungsten silicide film 11 and thepolysilicon film 3 are selectively partially removed to form the word lines 13 each of which extends on the surface of the P-type silicon substrate 1 orthogonally to thegrooves 7A and each of which is constituted of an interconnection layer formed, on eachactive region 6, of thepolycide gate electrode 12 composed of thepolysilicon film 3 and thetungsten silicide film 11, and on eachgroove 7A, of only thetungsten silicide film 11. - As mentioned above, in the second embodiment of the NOR type mask ROM in accordance with the present invention, the whole of the inner surface of the
groove 7A formed in the P-type silicon substrate 1 can be used for the buried digit line. In addition, since thegroove 7A is a V-shape in a vertical cross-section, the slant rotating ion implantation is no longer necessary in the N-type impurity implantation for forming the burieddigit line 8 at the inner surface of thegrooves 7, and also, the deeper the level along the V-shaped groove becomes, a spacing between each pair of adjacent buried digit lines becomes larger, so that it becomes possible to suppress a punch-through at a deep position, which cannot be controlled by thepolycide gate electrode 12. Therefore, even if the cell area is reduced, the second embodiment can simultaneously realize at least the maintaining and preferably the reducing of the layer resistance of the buried digit line, and the ensuring of the gate length margin (Lmin) of the cell transistor. - As mentioned above, the following advantages can be obtained according to the present invention.
- (1) The gate length margin (Lmin) of the cell transistor can be ensured. The reason for this is that, since the groove is a V-shape in a vertical cross-section, it is possible to avoid the punch-trough between a source and a drain at a deep position.
- (2) It is possible at least to maintain and preferably to reduce the layer resistance of the buried digit line. The reason for this is that the inner surface area of the groove can be ensured and increased by adjusting the depth and the shape of the groove.
- (3) It is possible to suppress a seeping-out of the code boron in a channel direction of the cell transistor, because the cell transistors are isolated from one another by the grooves in a channel direction.
- (4) It is possible to reduce the capacitance of the word line, because the capacitance of the word line is reduced by the thickness of the insulator film corresponding to the depth of the groove.
- The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.
Claims (17)
Applications Claiming Priority (2)
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JP14431298A JP3180951B2 (en) | 1998-05-26 | 1998-05-26 | Semiconductor storage device and method of manufacturing the same |
JP10-144312 | 1998-05-26 |
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US20020000625A1 true US20020000625A1 (en) | 2002-01-03 |
US6376887B2 US6376887B2 (en) | 2002-04-23 |
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US09/318,734 Expired - Fee Related US6376887B2 (en) | 1998-05-26 | 1999-05-26 | Semiconductor memory having buried digit lines |
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US (1) | US6376887B2 (en) |
JP (1) | JP3180951B2 (en) |
KR (1) | KR19990088551A (en) |
TW (1) | TW415099B (en) |
Cited By (1)
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EP2139191A1 (en) | 2008-06-25 | 2009-12-30 | Nokia Siemens Networks Oy | Method and device for processing data and system comprising such device |
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US6136662A (en) * | 1999-05-13 | 2000-10-24 | Lsi Logic Corporation | Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same |
US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
KR101075490B1 (en) | 2009-01-30 | 2011-10-21 | 주식회사 하이닉스반도체 | Semiconductor device with buried gate and method for fabricating the same |
US9401363B2 (en) | 2011-08-23 | 2016-07-26 | Micron Technology, Inc. | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices |
US8502294B1 (en) * | 2012-05-15 | 2013-08-06 | Nanya Technology Corporation | Semiconductor process and semiconductor structure for memory array with buried digit lines (BDL) |
CN105990433A (en) * | 2015-03-04 | 2016-10-05 | 和舰科技(苏州)有限公司 | Low resistance trench type metal oxide semiconductor field effect transistor and self-alignment process thereof |
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JPH053303A (en) | 1991-06-24 | 1993-01-08 | Hitachi Ltd | Semiconductor integrated circuit |
JPH05102436A (en) | 1991-10-09 | 1993-04-23 | Ricoh Co Ltd | Semiconductor memory device and manufacture thereof |
JPH05259410A (en) | 1992-03-13 | 1993-10-08 | Toshiba Corp | Mask rom |
JP2795107B2 (en) * | 1992-11-26 | 1998-09-10 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH0846024A (en) | 1994-07-26 | 1996-02-16 | Toshiba Microelectron Corp | Manufacture of semiconductor device |
KR100234697B1 (en) * | 1996-11-06 | 1999-12-15 | 김영환 | Manufacture of semiconductor device |
US5846865A (en) * | 1996-11-12 | 1998-12-08 | United Microelectronics Corp. | Method of fabricating flat-cell mask read-only memory (ROM) devices |
TW377496B (en) * | 1997-01-15 | 1999-12-21 | United Microelectronics Corp | Method of manufacturing read-only memory structure |
TW360954B (en) * | 1997-01-16 | 1999-06-11 | United Microelectronics Corp | Read-only memory structure and method of fabricating the same |
KR19980084469A (en) * | 1997-05-23 | 1998-12-05 | 문정환 | Mask ROM and Manufacturing Method |
US6057195A (en) * | 1998-05-22 | 2000-05-02 | Texas Instruments - Acer Incorporated | Method of fabricating high density flat cell mask ROM |
-
1998
- 1998-05-26 JP JP14431298A patent/JP3180951B2/en not_active Expired - Fee Related
-
1999
- 1999-05-26 TW TW088108792A patent/TW415099B/en not_active IP Right Cessation
- 1999-05-26 US US09/318,734 patent/US6376887B2/en not_active Expired - Fee Related
- 1999-05-26 KR KR1019990018967A patent/KR19990088551A/en not_active Application Discontinuation
Cited By (1)
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EP2139191A1 (en) | 2008-06-25 | 2009-12-30 | Nokia Siemens Networks Oy | Method and device for processing data and system comprising such device |
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KR19990088551A (en) | 1999-12-27 |
JPH11340341A (en) | 1999-12-10 |
JP3180951B2 (en) | 2001-07-03 |
TW415099B (en) | 2000-12-11 |
US6376887B2 (en) | 2002-04-23 |
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