JPH05259410A - Mask rom - Google Patents

Abstract

PURPOSE:To obtain a high speed flat NOR type memory wherein propagation delay time of word line or bit line is shortened by isolating a source.drain region from a word line through a dielectric layer filling a groove. CONSTITUTION:Boron is diffused on the surface of an N type semiconductor substrate 101 to form a P type diffusion layer 103 and a thin thermal oxide layer 105. Photoresist 107 is then applied on the entire surface and patterned in stripe and then the thermal oxide film 105 is removed through etching to form a groove 109. Arsenic ions are then injected while rotating the substrate and the photoresist is removed and then an N type diffusion layer 111 is formed through heat treatment. Thereafter, an oxide film 113 is deposited entirely on the surface of the substrate and then it is etched back until the semiconductor substrate is exposed. A gate oxide film 115 is then formed on the semiconductor substrate through thermal oxidation and a word line 117 is formed of silicon. According to the constitution, propagation delay time of word line is shortened without causing parasitic capacitance resulting in a high speed mask ROM.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a mask ROM.
In particular, a mask RO made up of flat NOR type memory cells
Regarding M.

[0002]

2. Description of the Related Art In a conventional mask ROM, an element isolation region and a contact hole by selective oxidation occupy a considerable area in a memory cell array. It is expected that the capacity will be increased by eliminating these in the memory cell array. This is realized by the NAND type mask ROM. However, since ion implantation after gate formation is difficult, the period from the time when data is obtained from the user until the product is shipped (hereinafter,
There is a drawback that TAT (abbreviated as Turn Around Time) becomes long. Further, since a plurality of memory cells are connected in series, there is a drawback that it is difficult to increase the speed. In the NOR-type mask ROM, ion implantation after forming the gate is easy, and since a plurality of memory cells are connected in parallel, the speed can be increased.

In the NOR type mask ROM, there is a flat NOR type memory (Sharp Technical Report No. 40, 1988).
Year P71-P75). This is a mask ROM having a contactless structure in which the element isolation region by the selective oxidation method is eliminated from the memory cell array. Below [Figure 9]
The structure of the flat NOR memory will be described with reference to FIG.

As shown in FIG. 9, the P-type semiconductor substrate 2
A parallel striped N-type diffusion layer 201 is provided on the gate electrode 00, and a word line 203 is provided with polycide in a direction perpendicular to the striped N-type diffusion layer 201 with a gate insulating film 208 interposed. [FIG. 10] is A to [FIG. 9]
A'section is shown. Word line 2 of N type diffusion layer 201
A source / drain region 204 is formed at the intersection with 03, and a channel 205 is formed immediately below the word line 203 between them. The inter-layer insulating film 210 is sandwiched, and the metal wiring 20 is formed on top of this.
9 is provided. In this way, a flat cell memory array having no element isolation region is realized.

FIG. 11 shows a part of the circuit configuration of a mask ROM using such a memory array. In such a flat cell structure, since the N type diffusion layer is used as a bit line and a ground line, their resistance and junction capacitance are large. Here, in order to reduce the propagation delay time of the bit line, the memory cell array is divided into several banks to form a bank selection structure. [FIG. 11] mainly shows the i-th bank. Each bank consists of two types of bank select transistors connected to both ends of the bit line. One is the even column select transistor 2
25, and the other is the odd column select transistor 226.
Is. D, E, F and G in FIG. 11 correspond to D, E, F and G in FIG.

For example, when accessing the memory cells 222 of even columns, WL15 and SEi are activated,
Then, H is activated to activate the column selection transistor 22.
Turn on 7. Then, the data of the memory cell is output to the sense amplifier 229. Odd column memory cells 224
When accessing, WL15 and SOi are activated, and H is activated.

The flat NOR memory has been described above.
With such a structure, there is no element isolation region by the selective oxidation method and no contact hole in the memory cell array, so that high integration is possible. Further, since it is the NOR type, ion implantation after forming the gate is easy, and since a plurality of memory cells are connected in parallel, the speed can be increased.

However, since the word line 203 is formed on the N type diffusion layer 201 with the thin gate oxide film 208 sandwiched in the flat NOR type memory as described above, the word line 203 is formed.
Since a parasitic capacitance is generated between the N-type diffusion layer 201 and the N-type diffusion layer 201, the propagation delay time of the word line 203 increases.

Further, in order to prevent the inversion of the channel 205, boron is generally ion-implanted at a low acceleration after the gate is formed. However, since this ion implantation is performed on the entire surface of the cell, there is a drawback that the resistance of the N-type diffusion layer 201 increases and the propagation delay time of the bit line increases.

In the case of a mask ROM, user data is written during the manufacturing process. After the word line 203 is formed, the flat NOR type cell is patterned with a photoresist, and boron is ion-implanted into the channel to change the threshold value of the cell transistor to write data, as shown in FIG. Since this photolithography is performed using the mask 230 in which the alignment margin is taken into consideration, boron, which is a P-type impurity, is partially implanted into the N-type diffusion layer 201. Therefore, the resistance of the N-type diffusion layer 201 further increases and the propagation delay time of the bit line further increases.

[0011]

As described above, in the conventional flat NOR type memory, since the parasitic capacitance is generated between the word line and the N type diffusion layer, the propagation delay time of the word line increases. Since boron, which is a P-type impurity, is injected into the type diffusion layer, there is a drawback that the resistance of the N-type diffusion layer increases and the propagation delay time of the bit line increases. An object of the present invention is to eliminate the above drawbacks, shorten the propagation delay time of word lines and bit lines, and provide a high-speed flat NOR type memory.

[0012]

In order to achieve the above object, according to the present invention, there is provided a substrate having a semiconductor layer of the first conductivity type on the surface thereof and a plurality of grooves in the semiconductor layer, and a bottom portion and a side wall of the groove. Second-conductivity-type diffusion layer formed in the portion, an insulating layer filling the groove, an insulating film formed on the surface of the semiconductor layer, and formed on the insulating layer and on the insulating film. And a masked conductive layer. Further, there is provided a mask ROM, wherein the impurity concentration at the groove bottom portion of the diffusion layer is higher than the impurity concentration at the groove sidewall portion. A mask ROM characterized in that the junction depth of the diffusion layer at the groove bottom is deeper than the junction depth at the groove sidewall.
I will provide a.

A substrate having a semiconductor layer of the first conductivity type on its surface and a plurality of grooves running parallel to the surface of the semiconductor layer, and a second conductivity type formed on the bottom and side walls of the groove. Formed of a diffusion layer, an insulator layer filling the groove, a gate insulating film formed on the surface of the semiconductor layer, and a conductor formed on the insulator layer and the gate insulating film. A mask ROM comprising: a memory cell transistor having a word line arranged in parallel to be orthogonal to the groove and having the diffusion layer as a source / drain region and the word line as a gate electrode. I will provide a. Further, there is provided a mask ROM, wherein the impurity concentration at the groove bottom portion of the diffusion layer is higher than the impurity concentration at the groove sidewall portion. Also provided is a mask ROM in which the junction depth of the diffusion layer at the groove bottom is deeper than the junction depth at the groove sidewall.

[0014]

When the means provided by the present invention is used, the bottom and side walls of the groove are the bit line / ground line and the source / drain region,
The insulating film on the semiconductor substrate functions as a gate insulating film, and the conductor layer on the insulating film functions as a gate electrode to form a memory cell transistor. In addition, the insulator layer filling the groove is the source
Since the drain region and the word line are separated, no parasitic capacitance is generated and the propagation delay time of the word line is shortened. Further, the insulative layer filling the groove at the time of preventing channel inversion and writing data prevents the implantation of impurities into the bit line. Therefore, the resistance of the bit line is not increased and the propagation delay time is shortened.

[0015]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 6.

As shown in FIG. 1, an N-type semiconductor substrate 1
On the surface 01, boron is diffused to form a P type diffusion layer (hereinafter abbreviated as P well) 103. Then, a thin thermal oxide film 105 is formed on the surface of the N-type semiconductor substrate 101 by thermal oxidation, and a photoresist 107 is applied on the entire surface. Then, the photoresist is patterned into stripes.

Next, as shown in FIG. 2, the thermal oxide film 10 is formed by RIE using the photoresist 107 as a mask.
5 is removed by etching, and the N-type semiconductor substrate 101 is 1 μm
The groove 109 is formed. Then, arsenic is ion-implanted. At this time, in order to implant arsenic not only in the bottom portion of the groove 109 but also in the sidewall portion, the implantation angle is set to about 30 degrees, and ion implantation is performed while rotating the substrate. Then, the photoresist is removed and heat treatment is performed to form the N-type diffusion layer 111.

Next, as shown in FIG. 3, an oxide film 113 is deposited on the entire surface of the substrate by the CVD method. continue,
As shown in FIG. 4, etchback is performed until the semiconductor substrate is exposed. The trench 109 is filled with an oxide film 113.

Next, as shown in FIG. 5, a gate oxide film 115 is formed on the semiconductor substrate by thermal oxidation. Then, as shown in FIG. 6, the word line 11 is made of polysilicon.
Form 7. The circuit configuration of the mask ROM using the memory cell described in this embodiment is the same as that shown in FIGS. 9 and 11.

In the flat NOR type mask ROM thus formed, the N type diffusion layer 111 functions as a source / drain region, a bit line and a ground line, and the gate oxide film 115.
The upper word line 117 acts as a gate electrode. Data writing is the same as in the conventional method, and after the word line 117 is formed, [FIG.
2], patterning with photoresist,
Data is written by ion-implanting boron into the channel and changing the threshold value of the cell transistor.

In the memory cell thus formed, the insulating layer filling the groove separates the source / drain region from the word line, so that parasitic capacitance is not generated and the propagation delay time of the word line is shortened. Therefore, the speed of the mask ROM can be increased. Further, the number of columns of memory cells in one bank can be increased without increasing the propagation delay time, and high integration can be achieved.

Further, the insulator layer filling the groove at the time of preventing channel inversion and writing data prevents the impurity from being injected into the bit line. Therefore, the resistance of the bit line is not increased and the propagation delay time is shortened. Therefore, the speed of the mask ROM can be increased. Further, the number of rows of memory cells in one bank can be increased without increasing the propagation delay time, and high integration can be achieved.

In addition, since the insulator layer filling the groove at the time of data writing prevents the impurity from being injected into the bit line, it is possible to make the alignment margin of the data writing mask larger than ever.

The embodiment in which the P well is formed in the N type semiconductor substrate and the N channel cell transistor is formed in the P well has been described above, but this is for stabilizing the back gate voltage of the cell transistor. If this is not necessary, N-channel cell transistors may be formed directly on the P-type semiconductor substrate. Further, an N well may be formed on the P type semiconductor substrate and a P channel cell transistor may be formed on the N well. Further, P-channel cell transistors may be formed directly on the N-type semiconductor substrate.

Although the word line is formed of polysilicon, the word line is not limited to this, and silicide or polycide may be used. The word line may be made of metal such as aluminum as long as data is written before forming the word line.

In the example, arsenic was obliquely ion-implanted when the diffusion layer was formed on the groove bottom and sidewalls. By making the junction depth of the diffusion layer at the bottom of the groove deeper than the side wall of the groove,
The resistance of the bit line can be reduced. Ion implantation is performed in two steps. First, arsenic is obliquely ion-implanted, and phosphorus is almost vertically ion-implanted. When heat-treated, the diffusion coefficient of phosphorus is larger than that of arsenic, so that the profile of the N-type diffusion layer becomes as shown in FIG. The N-type diffusion layer spreads largely in the deep portion of the substrate and wraps around under the gate, but there is no problem because the channel is formed near the substrate surface. In this way, by making the junction depth of the diffusion layer at the bottom of the groove deeper than the sidewall of the groove, the resistance of the bit line can be reduced.

Further, the resistance of the bit line can be further reduced by making the impurity concentration at the bottom of the groove higher than that at the side wall. A desired profile can be realized by performing ion implantation in two times, but it can also be realized by using ion implantation and solid phase diffusion. As shown in FIG. 8, after the groove is formed, phosphorus is vertically ion-implanted at a high concentration, and when an oxide film filling the groove is deposited, arsenic is doped at a high concentration in the oxide film, and then etched back. Solid phase diffusion. By thus increasing the impurity concentration at the bottom of the groove as compared with that at the side wall, the resistance of the bit line can be further reduced.

[0028]

By using the present invention, the flat N
In the OR-type mask ROM, since the parasitic capacitance of the word line is reduced, the propagation delay time of the word line can be shortened. Moreover, since the resistance of the bit line is reduced, the propagation delay time of the bit line can be shortened.

[Brief description of drawings]

FIG. 1 is a perspective view showing an embodiment.

FIG. 2 is a perspective view showing an embodiment.

FIG. 3 is a perspective view showing an embodiment.

FIG. 4 is a perspective view showing an embodiment.

FIG. 5 is a perspective view showing an embodiment.

FIG. 6 is a perspective view showing an embodiment.

FIG. 7 is a perspective view showing an embodiment.

FIG. 8 is a perspective view showing an embodiment.

FIG. 9 is a plan view showing a conventional example.

FIG. 10 is a sectional view showing a conventional example.

FIG. 11 is a circuit diagram showing a conventional example.

FIG. 12 is a sectional view showing a conventional example.

[Explanation of symbols]

 101 N-type semiconductor substrate 103 P-well 105 Thermal oxide film 107, 230 Photoresist 109 Grooves 111, 201, 202 N-type diffusion layer 113 Oxide film 115 Gate oxide film 117, 203 Word line 200 P-type semiconductor substrate 204 Source / drain region 205 channel 206 even column selection line 207 odd column selection line 209 metal wiring 210 interlayer insulating film 212 even column memory cell 224 odd column memory cell 225 even column selection transistor 226 odd column selection transistor 227 column selection transistor

Claims (6)

[Claims] 1. A substrate having a semiconductor layer of the first conductivity type on its surface and a plurality of grooves in the semiconductor layer, and a diffusion layer of the second conductivity type formed on the bottom and side walls of the groove. A mask comprising: an insulating layer filling the groove; an insulating film formed on the surface of the semiconductor layer; and a conductive layer formed on the insulating layer and the insulating film. ROM. 2. The mask ROM according to claim 1, wherein the impurity concentration at the groove bottom portion of the diffusion layer is higher than the impurity concentration at the groove sidewall portion. 3. The mask ROM according to claim 1, wherein a junction depth of the diffusion layer at the groove bottom portion is deeper than a junction depth at the groove sidewall portion. 4. A substrate having a semiconductor layer of the first conductivity type on its surface and having a plurality of grooves running parallel to the surface of the semiconductor layer; and a second conductivity type formed on the bottom and side walls of the groove. Formed of a diffusion layer, an insulator layer filling the groove, a gate insulating film formed on the surface of the semiconductor layer, and a conductor formed on the insulator layer and the gate insulating film. A mask ROM comprising: a memory cell transistor having a word line arranged in parallel to be orthogonal to the groove and having the diffusion layer as a source / drain region and the word line as a gate electrode. .. 5. The mask ROM according to claim 4, wherein the impurity concentration at the groove bottom portion of the diffusion layer is higher than the impurity concentration at the groove side wall portion. 6. The mask ROM according to claim 4, wherein a junction depth of the diffusion layer at the groove bottom portion is deeper than a junction depth at the groove sidewall portion.