US20010015931A1 - Semiconductor memory device having a plurality of banks sharing a column control unit - Google Patents

Semiconductor memory device having a plurality of banks sharing a column control unit Download PDF

Info

Publication number
US20010015931A1
US20010015931A1 US09/750,228 US75022800A US2001015931A1 US 20010015931 A1 US20010015931 A1 US 20010015931A1 US 75022800 A US75022800 A US 75022800A US 2001015931 A1 US2001015931 A1 US 2001015931A1
Authority
US
United States
Prior art keywords
data
memory device
bank
global
data bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/750,228
Other versions
US6385121B2 (en
Inventor
Byung Jae Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. reassignment HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, BYUNG JAE
Publication of US20010015931A1 publication Critical patent/US20010015931A1/en
Application granted granted Critical
Publication of US6385121B2 publication Critical patent/US6385121B2/en
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD.
Assigned to 658868 N.B. INC. reassignment 658868 N.B. INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HYNIX SEMICONDUCTOR INC.
Assigned to ROYAL BANK OF CANADA reassignment ROYAL BANK OF CANADA U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM Assignors: 658276 N.B. LTD., 658868 N.B. INC., MOSAID TECHNOLOGIES INCORPORATED
Assigned to CONVERSANT IP N.B. 868 INC. reassignment CONVERSANT IP N.B. 868 INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: 658868 N.B. INC.
Assigned to CONVERSANT IP N.B. 868 INC., CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CONVERSANT IP N.B. 276 INC. reassignment CONVERSANT IP N.B. 868 INC. RELEASE OF SECURITY INTEREST Assignors: ROYAL BANK OF CANADA
Assigned to ROYAL BANK OF CANADA, AS LENDER, CPPIB CREDIT INVESTMENTS INC., AS LENDER reassignment ROYAL BANK OF CANADA, AS LENDER U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: CONVERSANT IP N.B. 868 INC.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CONVERSANT IP N.B. 868 INC.
Assigned to CPPIB CREDIT INVESTMENTS, INC. reassignment CPPIB CREDIT INVESTMENTS, INC. AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: ROYAL BANK OF CANADA, AS LENDER
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CPPIB CREDIT INVESTMENTS INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

  • the present invention relates in general to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device having a plurality of banks sharing a column control unit.
  • FIG. 1 is a block diagram of a semiconductor memory device constructed by four banks in accordance with a conventional art.
  • the semiconductor memory device comprises four banks 1 a - 1 d and column control units 2 a - 2 d , each arranged at an one end of the corresponding bank, for controlling the banks 1 a - 1 d .
  • Each of the column control units 2 a - 2 d include 32 write drivers (not shown) and 32 data bus sense amplifiers (not shown).
  • Each of the banks 1 a - 1 d includes the corresponding row decoders 3 a - 3 d , which are arranged to the center of each bank, and 32 pairs of global data bus (not shown).
  • FIG. 2 is a block diagram illustrating column control units 2 a and 2 b for controlling two adjacent banks 1 a and 1 b in the block diagram of FIG. 1. There are a number pairs of write driver WD and data bus sense amplifier DBSA.
  • Each write driver WD drives data loaded to a global write input/output line GWIO being shared by four banks 1 a - 1 d and then outputs the data to a pair of global data buses GDB and /GDB of the respective banks 1 a - 1 d
  • each data bus sense amplifier DBSA amplifies data loaded to a pair of global data buses GDB and /GDB of the respective banks 1 a - 1 d and outputs the data to a pair of global read input/output lines GRIO and /GRIO being shared by four banks 1 a - 1 d.
  • FIG. 3 is a detailed circuit diagram of the data bus sense amplifier DBSA of the column control units 2 a and 2 b .
  • the data bus sense amplifier DBSA includes differential amplifiers 4 a and 4 b , enabled by a data bus sense amplifier enable signal DBSAEN for sensing data loaded to a pair of global data buses GDB and /GDB.
  • a cross-coupled amplifier 5 senses and amplifies the data enabled by the data bus sense amplifier enable signal DBSAEN and then sensed by the differential amplifiers 4 a and 4 b and then transmits the sensed and amplified data to a pair of global read input/output lines GRIO and /GRIO.
  • Data bus sense amplifier DBSA includes a PMOS transistor PM 1 for equalizing output lines of the differential amplifiers 4 a and 4 b when the data bus sense amplifier enable signal DBSAEN is disabled.
  • PMOS transistors PM 2 -PM 4 pre-charge and equalize the output terminal of the cross-coupled amplifier 5 with a constant level when the data bus sense amplifier enable signal DBSAEN is disabled.
  • FIG. 4 is a detailed circuit diagram of the write driver WD of the column control units 2 a and 2 b .
  • the write driver WD includes decoding units 6 a and 6 b for decoding the data loaded to a global write input/output line GWIO shared by four banks 4 a - 4 d when a pre-charge enable signal PCGEN is disabled and a write drive enable signal WDEN is enabled.
  • Latch units 7 a and 7 b latch the decoded data from decoding units 6 a and 6 b .
  • Drive units 8 a and 8 b transmit the latched data from the latch unit 7 a and 7 b to a pair of global data busses GDB and /GDB of each bank.
  • the write driver WD further includes a PMOS transistor PM 21 for equalizing the global data busses GDB and /GDB.
  • PMOS transistors PM 22 and PM 23 pre-charge the global data busses GDB and /GDB with a constant level.
  • the conventional semiconductor memory device has 32 pairs of write drivers WD and data bus sense amplifiers DBSA having MOS devices of very large size in order to promote a transmission efficiency of banks of 1 a - 1 b , respectively.
  • 128 write driver units WD and data bus sense amplifiers DBSA should be equipped, in the entire the semiconductor memory device. This is disadvantageous in that the chip area must be made to be very large and a current consumption increases.
  • the claimed inventions feature, at least in part, a semiconductor memory device in which a plurality of banks, which are adjacent to each other, share one column control unit, thereby reducing a chip area and decreasing current consumption.
  • a write driver in the present invention is constructed by using a cross-coupled amplifier, thereby reducing a layout area.
  • the column control unit is selectively connected with a plurality of banks by using a switching unit which is controlled by a control signal assembled with bank addresses. Therefore, the number of a data bus sense amplifiers and a drivers needed in the column control unit is decreased. Consequently, chip area can be reduced, speed is enhanced, and current consumption is decreased.
  • An exemplary embodiment of a semiconductor memory device according to the inventions herein includes a plurality of memory banks wherein each memory bank has multiple pairs of global data bus for transferring data from or to itself.
  • a plurality of column control means controls input and output of data between the memory bank and the outside devices. Each column control means is arranged between adjacent ones of the plurality of memory banks, and controls the input or output of data of the adjacent ones.
  • Each column control means includes: 1) a plurality of write drivers, each assigned to one pair of global data bus, for transferring the data inputted from the outside devices into the memory bank; 2) a plurality of data bus sense amplifiers, each assigned to one pair of global data bus, for sensing and amplifying data from the memory bank and then outputting the amplified data toward the outside devices; and 3) a plurality of switching means for connecting one of the adjacent ones with the outside devices with the plurality of write drivers and data bus sense amplifiers.
  • FIG. 1 is a block diagram of a semiconductor memory device having a conventional bank structure
  • FIG. 2 is a detailed block diagram of a column control unit shown in FIG. 1;
  • FIG. 3 is a detailed circuit diagram of a data bus sense amplifier shown in FIG. 2;
  • FIG. 4 is a detailed circuit diagram of a write driver shown in FIG. 2.
  • FIG. 5 is a detailed block diagram of a semiconductor memory device having a bank structure in accordance with the present invention.
  • FIG. 6 is a detailed circuit diagram of a column control unit shown in FIG. 5.
  • FIG. 5 is a detailed block diagram of a semiconductor memory device having a bank structure in accordance with the present invention.
  • two adjacent banks 10 a and 10 b share a column control unit 20 .
  • two adjacent banks 10 a and 10 b share one column control unit 20 .
  • Data bus sense amplifier DBSA and a write driver WD of the column control unit 20 are shared by two adjacent banks 10 a and 10 b .
  • the column control unit 20 includes a plurality of unit column control parts 30 a and 30 b , which are controlled by a pre-charge enable signal PCGEN, a data bus sense amplifier enable signal DBSAEN, a write driver enable signal WDEN and a bank address BANKENi.
  • Each unit column control parts 30 a and 30 b includes a data bus sense amplifier DBSA and a write driver WD.
  • FIG. 6 is a detailed circuit diagram of a unit column control parts, such as part 30 a or 30 b .
  • Unit column control part 30 a includes transfer gates TG 11 -TG 14 controlled by signal that is a logical combination of data bus sense amplifier enable signal DBSAEN and bank address signals BANKEN 0 and BANKEN 1 , combined by NAND gates ND 11 and ND 12 , for selectively connecting a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of a bank 10 a or 10 b to a data bus sense amplifier DBSA.
  • DBSAEN data bus sense amplifier enable signal
  • BANKEN 0 and BANKEN 1 bank address signals
  • ND 11 and ND 12 for selectively connecting a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of a bank 10 a or 10 b to a data bus sense amplifier DBSA.
  • Data bus sense amplifier DBSA is enabled by a data bus sense amplifier enable signal DBSAEN and amplifies the data loaded to a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of a bank 10 a or 10 b by the transfer gates TG 11 -TG 14 and then transmits the amplified data to a pair of global read input/output lines GRIO and /GRIO.
  • Transfer gates TG 21 -TG 24 are controlled by a logical combination of a write driver enable signal WDEN and bank address signals BANKEN 0 and BANKEN 1 , combined by NAND gates ND 13 and ND 14 .
  • Transfer gates selectively connect a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of a bank 10 a or 10 b to a write driver WD.
  • Write driver WD drives data loaded to a global write input/output line GWIO and selectively transmits data to a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of a bank 10 a or 10 b by the transfer gates TG 21 -TG 24 .
  • PMOS transistors PM 31 and PM 32 controlled by a pre-charge enable signal PCGEN, equalizes a pair of the global data busses GDB 1 and /GDB 1 of the bank 10 a and a pair of the global data busses GDB 2 and /GDB 2 of the bank 10 b .
  • PMOS transistors PM 33 -PM 36 controlled by the pre-charge enable signal PCGEN, pre-charge a pair of the global data busses GDB 1 and /GDB 1 of the bank 10 a and a pair of the global data busses GDB 2 and /GDB 2 of the bank 10 b.
  • the write driver WD includes cross-coupled PMOS transistors PM 41 and PM 42 .
  • An NMOS transistors NM 41 receive data loaded to the global write input/output line GWIO.
  • An NMOS transistor NM 43 enables the write driver WD when the pre-charge enable signal PCGEN is disabled.
  • a PMOS transistor PM 43 controlled by the pre-charge enable signal PCGEN, equalizes an output terminal of the write driver WD.
  • Transfer gates TG 11 and TG 12 are controlled by the NAND signal and its inverted signal from an NAND gate 11 for NANDing the data bus sense amplifier enable signal DBSAEN and the bank address signal BANKEN 0 , and connect selectively a pair of global data busses GDB 1 and /GDB 1 of a bank 10 a to the data bus sense amplifier DBSA, respectively.
  • Transfer gates TG 13 and TG 14 are controlled by the NAND signal and its inverted signal from an NAND gate 12 for NANDing the data bus sense amplifier enable signal DBSAEN and the bank address signal BANKEN 1 , and connect selectively a pair of global data busses GDB 2 and /GDB 2 of a bank 10 b to the data bus sense amplifier DBSA, respectively.
  • Transfer gates TG 21 and TG 22 are controlled by the NAND signal and its inverted signal from an NAND gate 13 for NANDing the write driver enable signal WDEN and the bank address signal BANKEN 0 , and connect selectively a pair of global data busses GDB 1 and /GDB 1 of a bank 10 a to the write driver WD, respectively.
  • the transfer gates TG 23 and TG 24 are controlled by NAND signal and its inverted signal from an NAND gate 14 for NANDing the write driver enable signal WDEN and the bank address signal BANKEN 1 , and connect selectively a pair of global data busses GDB 2 and /GDB 2 of a bank 10 b to the write driver WD, respectively.
  • a pair of Global data busses GDB 1 and /GDB 1 of a bank 10 a or a pair of global data busses GDB 2 and /GDB 2 of a bank 10 b which are loaded with high, are cut by the transfer gates TG 15 and TG 18 so that only an output terminal of the write driver WD, which is loaded with low, reaches a high level or a low level and thereafter the transfer gates TG 15 and TG 18 are turned on by a control signal delayed with a constant time and produced by bank address signals BANKEN 0 and BANKEN 1 and then the data is transmitted to a global data bus of the selected bank 10 a or 10 b.
  • PMOS transistors PM 33 -PM 36 are turned on, thereby pre-charging the global data busses GDB and /GDB at a constant level.
  • PMOS transistors PM 31 and PM 32 are turned on, thereby equalizing a pair of global data busses GDB 1 and /GDB 1 of the bank 10 a and a pair of global data busses GDB 2 and /GDB 2 of the bank 10 b .
  • a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 of the selected bank 10 a or 10 b are driven, a pair of global data busses GDB 2 and /GDB 2 or GDB 1 and /GDB 2 of the non-selected bank 10 b or 10 a are equalized so that a current consumption in pre-charging can be reduced and a pre-charge time can be reduced.
  • the data bus sense amplifier DBSA and the write driver WD of the column control unit 20 are selectively connected a pair of global data busses GDB 1 and /GDB 1 or GDB 2 and /GDB 2 and shared by using transfer gates TG 11 - 18 controlled by a control signal generated by bank addresses BANKEN 0 and BANKEN 1 so that the number of the data bus sense amplifier DBSA and the write driver WD can be reduced, thereby reducing a chip area and a current consumption.
  • a switching unit is used in order to selectively connect a plurality of banks to a column control unit to by a control signal generated through a bank address signal so that the number of a data bus sense amplifier DBSA and a write driver WD can be reduced, thereby reducing a chip area and a current consumption.
  • a global data bus, which is selected and then driven, and a global data bus, which is not selected and then is not driven, are equalized, as a result, there is an advantage in that a current consumption is reduced in pre-charging and a pre-charge time is reduced.

Abstract

The present invention discloses a semiconductor memory device having a plurality of banks sharing a column control unit. One column control unit is constructed to share a plurality of banks, which are adjacent with each other, thereby reducing a chip area and decreasing current consumption, and a write driver is constructed by using a cross-coupled amplifier, thereby reducing a layout area. A switching unit selectively connects a plurality of banks to a column control unit to by a control signal generated through a bank address signal and so the number of a data bus sense amplifier DBSA and a write driver WD can be reduced, thereby reducing a chip area and a current consumption. A global data bus, which is selected and then driven, and a global data bus, which is not selected and then is not driven, are equalized, as a result, there is an advantage that a current consumption is reduced in pre-charging and a pre-charge time is reduced.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates in general to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device having a plurality of banks sharing a column control unit. [0002]
  • 2. General Background and Related Art [0003]
  • FIG. 1 is a block diagram of a semiconductor memory device constructed by four banks in accordance with a conventional art. [0004]
  • The semiconductor memory device comprises four [0005] banks 1 a-1 d and column control units 2 a-2 d, each arranged at an one end of the corresponding bank, for controlling the banks 1 a-1 d. Each of the column control units 2 a-2 d include 32 write drivers (not shown) and 32 data bus sense amplifiers (not shown).
  • Each of the [0006] banks 1 a-1 d includes the corresponding row decoders 3 a-3 d, which are arranged to the center of each bank, and 32 pairs of global data bus (not shown).
  • FIG. 2 is a block diagram illustrating [0007] column control units 2 a and 2 b for controlling two adjacent banks 1 a and 1 b in the block diagram of FIG. 1. There are a number pairs of write driver WD and data bus sense amplifier DBSA. Each write driver WD drives data loaded to a global write input/output line GWIO being shared by four banks 1 a-1 d and then outputs the data to a pair of global data buses GDB and /GDB of the respective banks 1 a-1 d, and each data bus sense amplifier DBSA amplifies data loaded to a pair of global data buses GDB and /GDB of the respective banks 1 a-1 d and outputs the data to a pair of global read input/output lines GRIO and /GRIO being shared by four banks 1 a-1 d.
  • FIG. 3 is a detailed circuit diagram of the data bus sense amplifier DBSA of the [0008] column control units 2 a and 2 b. The data bus sense amplifier DBSA includes differential amplifiers 4 a and 4 b, enabled by a data bus sense amplifier enable signal DBSAEN for sensing data loaded to a pair of global data buses GDB and /GDB. A cross-coupled amplifier 5 senses and amplifies the data enabled by the data bus sense amplifier enable signal DBSAEN and then sensed by the differential amplifiers 4 a and 4 b and then transmits the sensed and amplified data to a pair of global read input/output lines GRIO and /GRIO. Data bus sense amplifier DBSA includes a PMOS transistor PM1 for equalizing output lines of the differential amplifiers 4 a and 4 b when the data bus sense amplifier enable signal DBSAEN is disabled. PMOS transistors PM2-PM4 pre-charge and equalize the output terminal of the cross-coupled amplifier 5 with a constant level when the data bus sense amplifier enable signal DBSAEN is disabled.
  • FIG. 4 is a detailed circuit diagram of the write driver WD of the [0009] column control units 2 a and 2 b. The write driver WD includes decoding units 6 a and 6 b for decoding the data loaded to a global write input/output line GWIO shared by four banks 4 a-4 d when a pre-charge enable signal PCGEN is disabled and a write drive enable signal WDEN is enabled. Latch units 7 a and 7 b latch the decoded data from decoding units 6 a and 6 b. Drive units 8 a and 8 b transmit the latched data from the latch unit 7 a and 7 b to a pair of global data busses GDB and /GDB of each bank.
  • The write driver WD further includes a PMOS transistor PM[0010] 21 for equalizing the global data busses GDB and /GDB. PMOS transistors PM22 and PM23 pre-charge the global data busses GDB and /GDB with a constant level.
  • The conventional semiconductor memory device has 32 pairs of write drivers WD and data bus sense amplifiers DBSA having MOS devices of very large size in order to promote a transmission efficiency of banks of [0011] 1 a-1 b, respectively. As a result, 128 write driver units WD and data bus sense amplifiers DBSA should be equipped, in the entire the semiconductor memory device. This is disadvantageous in that the chip area must be made to be very large and a current consumption increases.
    • SUMMARY
  • The claimed inventions feature, at least in part, a semiconductor memory device in which a plurality of banks, which are adjacent to each other, share one column control unit, thereby reducing a chip area and decreasing current consumption. A write driver in the present invention is constructed by using a cross-coupled amplifier, thereby reducing a layout area. [0012]
  • The column control unit is selectively connected with a plurality of banks by using a switching unit which is controlled by a control signal assembled with bank addresses. Therefore, the number of a data bus sense amplifiers and a drivers needed in the column control unit is decreased. Consequently, chip area can be reduced, speed is enhanced, and current consumption is decreased. An exemplary embodiment of a semiconductor memory device according to the inventions herein includes a plurality of memory banks wherein each memory bank has multiple pairs of global data bus for transferring data from or to itself. A plurality of column control means controls input and output of data between the memory bank and the outside devices. Each column control means is arranged between adjacent ones of the plurality of memory banks, and controls the input or output of data of the adjacent ones. Each column control means includes: 1) a plurality of write drivers, each assigned to one pair of global data bus, for transferring the data inputted from the outside devices into the memory bank; 2) a plurality of data bus sense amplifiers, each assigned to one pair of global data bus, for sensing and amplifying data from the memory bank and then outputting the amplified data toward the outside devices; and 3) a plurality of switching means for connecting one of the adjacent ones with the outside devices with the plurality of write drivers and data bus sense amplifiers. [0013]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The claimed inventions will be explained in terms of exemplary embodiments that are described in detail with reference to the accompanying drawings, which are given only by way of illustration and thus are not limitative of the present invention, wherein: [0014]
  • FIG. 1 is a block diagram of a semiconductor memory device having a conventional bank structure; [0015]
  • FIG. 2 is a detailed block diagram of a column control unit shown in FIG. 1; [0016]
  • FIG. 3 is a detailed circuit diagram of a data bus sense amplifier shown in FIG. 2; [0017]
  • FIG. 4 is a detailed circuit diagram of a write driver shown in FIG. 2. [0018]
  • FIG. 5 is a detailed block diagram of a semiconductor memory device having a bank structure in accordance with the present invention; [0019]
  • FIG. 6 is a detailed circuit diagram of a column control unit shown in FIG. 5. [0020]
    • DETAILED DESCRIPTION
  • A semiconductor memory device in accordance with an exemplary preferred embodiment of the present invention will now be described with reference to the accompanying drawings. [0021]
  • FIG. 5 is a detailed block diagram of a semiconductor memory device having a bank structure in accordance with the present invention. In our arrangement, two [0022] adjacent banks 10 a and 10 b share a column control unit 20. In general, for semiconductor memory arrangements including a plurality of banks, two adjacent banks 10 a and 10 b share one column control unit 20.
  • Data bus sense amplifier DBSA and a write driver WD of the [0023] column control unit 20 are shared by two adjacent banks 10 a and 10 b. The column control unit 20 includes a plurality of unit column control parts 30 a and 30 b, which are controlled by a pre-charge enable signal PCGEN, a data bus sense amplifier enable signal DBSAEN, a write driver enable signal WDEN and a bank address BANKENi. Each unit column control parts 30 a and 30 b includes a data bus sense amplifier DBSA and a write driver WD.
  • FIG. 6 is a detailed circuit diagram of a unit column control parts, such as [0024] part 30 a or 30 b. For the sake of discussion, we will describe the detail of part 30 a. Unit column control part 30 a includes transfer gates TG11-TG14 controlled by signal that is a logical combination of data bus sense amplifier enable signal DBSAEN and bank address signals BANKEN0 and BANKEN1, combined by NAND gates ND11 and ND12, for selectively connecting a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 of a bank 10 a or 10 b to a data bus sense amplifier DBSA. Data bus sense amplifier DBSA is enabled by a data bus sense amplifier enable signal DBSAEN and amplifies the data loaded to a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 of a bank 10 a or 10 b by the transfer gates TG11-TG14 and then transmits the amplified data to a pair of global read input/output lines GRIO and /GRIO. Transfer gates TG21-TG24 are controlled by a logical combination of a write driver enable signal WDEN and bank address signals BANKEN0 and BANKEN1, combined by NAND gates ND13 and ND14. These transfer gates selectively connect a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 of a bank 10 a or 10 b to a write driver WD. Write driver WD drives data loaded to a global write input/output line GWIO and selectively transmits data to a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 of a bank 10 a or 10 b by the transfer gates TG21-TG24. PMOS transistors PM31 and PM32, controlled by a pre-charge enable signal PCGEN, equalizes a pair of the global data busses GDB1 and /GDB1 of the bank 10 a and a pair of the global data busses GDB2 and /GDB2 of the bank 10 b. PMOS transistors PM33-PM36, controlled by the pre-charge enable signal PCGEN, pre-charge a pair of the global data busses GDB1 and /GDB1 of the bank 10 a and a pair of the global data busses GDB2 and /GDB2 of the bank 10 b.
  • The write driver WD includes cross-coupled PMOS transistors PM[0025] 41 and PM42. An NMOS transistors NM41 receive data loaded to the global write input/output line GWIO. An NMOS transistor NM43 enables the write driver WD when the pre-charge enable signal PCGEN is disabled. A PMOS transistor PM43, controlled by the pre-charge enable signal PCGEN, equalizes an output terminal of the write driver WD.
  • The construction of the data bus sense amplifier DBSA according to the present invention is the same as that of the conventional art and so an explanation of its construction and operation will be omitted. [0026]
  • Transfer gates TG[0027] 11 and TG12 are controlled by the NAND signal and its inverted signal from an NAND gate 11 for NANDing the data bus sense amplifier enable signal DBSAEN and the bank address signal BANKEN0, and connect selectively a pair of global data busses GDB1 and /GDB1 of a bank 10 a to the data bus sense amplifier DBSA, respectively. Transfer gates TG13 and TG14 are controlled by the NAND signal and its inverted signal from an NAND gate 12 for NANDing the data bus sense amplifier enable signal DBSAEN and the bank address signal BANKEN1, and connect selectively a pair of global data busses GDB2 and /GDB2 of a bank 10 b to the data bus sense amplifier DBSA, respectively.
  • Transfer gates TG[0028] 21 and TG22 are controlled by the NAND signal and its inverted signal from an NAND gate 13 for NANDing the write driver enable signal WDEN and the bank address signal BANKEN0, and connect selectively a pair of global data busses GDB1 and /GDB1 of a bank 10 a to the write driver WD, respectively. The transfer gates TG23 and TG24 are controlled by NAND signal and its inverted signal from an NAND gate 14 for NANDing the write driver enable signal WDEN and the bank address signal BANKEN1, and connect selectively a pair of global data busses GDB2 and /GDB2 of a bank 10 b to the write driver WD, respectively.
  • The operation of the unit [0029] column control parts 30 a and 30 b will be now described. First, in a write operation, when a pre-charge enable signal PCGEN is disabled at a high level, an NMOS transistor NM43 of a write driver WD is turned on and the write driver WD is enabled so that data loaded to a global write input/output line GWIO drive NMOS transistors NM41 and NM42 and thereby causes the output terminal of the write driver WD to be a logic high level or a logic low level according to the inputted data.
  • At the beginning of operation of the write driver WD, a pair of Global data busses GDB[0030] 1 and /GDB1 of a bank 10 a or a pair of global data busses GDB2 and /GDB2 of a bank 10 b, which are loaded with high, are cut by the transfer gates TG15 and TG18 so that only an output terminal of the write driver WD, which is loaded with low, reaches a high level or a low level and thereafter the transfer gates TG15 and TG18 are turned on by a control signal delayed with a constant time and produced by bank address signals BANKEN0 and BANKEN1 and then the data is transmitted to a global data bus of the selected bank 10 a or 10 b.
  • In a pre-charge operation, if a pre-charge enable signal PCGEN is enabled at a low level, the output terminal of the write driver WD is equalized by the PMOS transistor [0031] 43 of the write driver WD and the NMOS transistor NM43 is turned off so that the write driver WD is not operated any more.
  • Successively, PMOS transistors PM[0032] 33-PM36 are turned on, thereby pre-charging the global data busses GDB and /GDB at a constant level. In addition, PMOS transistors PM31 and PM32 are turned on, thereby equalizing a pair of global data busses GDB1 and /GDB1 of the bank 10 a and a pair of global data busses GDB2 and /GDB2 of the bank 10 b. Here, after a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 of the selected bank 10 a or 10 b are driven, a pair of global data busses GDB2 and /GDB2 or GDB1 and /GDB2 of the non-selected bank 10 b or 10 a are equalized so that a current consumption in pre-charging can be reduced and a pre-charge time can be reduced.
  • The data bus sense amplifier DBSA and the write driver WD of the [0033] column control unit 20 are selectively connected a pair of global data busses GDB1 and /GDB1 or GDB2 and /GDB2 and shared by using transfer gates TG11-18 controlled by a control signal generated by bank addresses BANKEN0 and BANKEN1 so that the number of the data bus sense amplifier DBSA and the write driver WD can be reduced, thereby reducing a chip area and a current consumption.
  • According to the present invention, a switching unit is used in order to selectively connect a plurality of banks to a column control unit to by a control signal generated through a bank address signal so that the number of a data bus sense amplifier DBSA and a write driver WD can be reduced, thereby reducing a chip area and a current consumption. [0034]
  • A global data bus, which is selected and then driven, and a global data bus, which is not selected and then is not driven, are equalized, as a result, there is an advantage in that a current consumption is reduced in pre-charging and a pre-charge time is reduced. [0035]
  • As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims. [0036]

Claims (18)

What is claimed is:
1. A semiconductor memory device, comprising:
a plurality of memory banks wherein each memory bank has multiple pairs of global data bus for transferring data from or to itself, and;
a plurality of column control means for controlling input and output of data between the memory bank and the outside devices,
wherein each column control means is arranged between adjacent ones of the plurality of memory banks, and controls the input or output of data of the adjacent ones.
2. The memory device according to
claim 1
, wherein each column control means comprising:
a plurality of write drivers, each assigned to one pair of global data bus, for transferring the data inputted from the outside devices into the memory bank;
a plurality of data bus sense amplifiers, each assigned to one pair of global data bus, for sensing and amplifying data from the memory bank and then outputting the amplified data toward the outside devices; and
a plurality of switching means for connecting one of the adjacent ones with the outside devices with the plurality of write drivers and data bus sense amplifiers.
3. The memory device according to
claim 1
, wherein each switching means comprises:
a plurality of first transfer means, controlled by signal that is a logical combination of a data bus sense amplifier enable signal and a bank address, for selectively connecting a pair of global data busses of the selected bank to a data bus sense amplifier; and
a plurality of second transfer means, controlled by signal that is a logical combination of a write driver enable signal with a bank address, for selectively connecting a pair of global data busses of the selected bank to a write driver.
4. The memory device according to
claim 2
, wherein the first and the second transfer means are transfer gates.
5. The memory device according to
claim 1
, wherein the column control means comprises:
a plurality of equalizing means for equalizing a pair of global data busses of a plurality of banks, which are controlled by a pre-charge enable signal and share each column control means; and
a plurality of pre-charge means for pre-charging a pair of global data busses of a bank, which are controlled by a pre-charge enable signal and share each column control means.
6. The memory device according to
claim 4
, wherein the equalizing means comprises a MOS transistor.
7. The memory device according to
claim 1
, wherein the write driver is a cross-coupled amplifier, which senses and amplifies data loaded to a global write input/output line and its inverted signal.
8. The memory device according to
claim 6
, wherein the cross-coupled amplifier comprises:
cross-coupled first and a second MOS transistors;
a third MOS transistor being inputted data loaded to the global write input/output line;
a fourth MOS transistor being inverted and then inputted data loaded to the global write input/output line;
a fifth MOS transistor for enabling a write driver when disabling a pre-charge signal;
a sixth MOS transistor controlled by the pre-charge enable signal and for equalizing an output terminal of the write driver.
9. The memory device according to
claim 7
, wherein the fifth and sixth MOS transistors are turned on alternately.
10. A semiconductor memory device, comprising:
a plurality of memory banks wherein each memory bank has multiple pairs of global data bus for transferring data from or to itself, and;
a plurality of column controls constructed and arranged to control input and output of data between the memory bank and the outside devices,
wherein each column control is arranged between adjacent ones of the plurality of memory banks, and controls the input or output of data of the adjacent ones.
11. The memory device according to
claim 10
, wherein each column control comprises:
a plurality of write drivers, each assigned to one pair of global data bus, for transferring the data inputted from the outside devices into the memory bank;
a plurality of data bus sense amplifiers, each assigned to one pair of global data bus, for sensing and amplifying data from the memory bank and then outputting the amplified data toward the outside devices; and
a plurality of switches each constructed and arranged to connect one of the adjacent ones with the outside devices with the plurality of write drivers and data bus sense amplifiers.
12. The memory device according to
claim 10
, wherein each switch comprises:
a plurality of first transfer devices constructed and arranged to be controlled by a signal combining a data bus sense amplifier enable signal with a bank address and to selectively connect a pair of global data busses of the selected bank to a data bus sense amplifier; and
a plurality of second transfer devices constructed and arranged to be controlled by a signal combining a write driver enable signal with a bank address and to selectively connect a pair of global data busses of the selected bank to a write driver.
13. The memory device according to
claim 11
, wherein the first and the second transfer devices are transfer gates.
14. The memory device according to
claim 10
, wherein the column control comprises:
a plurality of equalizers constructed and arranged to equalize a pair of global data busses of a plurality of banks, which are controlled by a pre-charge enable signal and share each column control; and
a plurality of pre-chargers each being constructed and arranged to pre-charge a pair of global data busses of a bank, which are controlled by a pre-charge enable signal and share each column control.
15. The memory device according to
claim 4
, wherein each equalizer comprises a MOS transistor.
16. The memory device according to
claim 10
, wherein the write driver is a cross-coupled amplifier, which senses and amplifies data loaded to a global write input/output line and its inverted signal.
17. The memory device according to
claim 6
, wherein the cross-coupled amplifier comprises:
cross-coupled first and a second MOS transistors;
a third MOS transistor receiving data loaded to the global write input/output line;
a fourth MOS transistor being inverted and then inputted data loaded to the global write input/output line;
a fifth MOS transistor for enabling a write driver when disabling a pre-charge signal;
a sixth MOS transistor controlled by the pre-charge enable signal and for equalizing an output terminal of the write driver.
18. The memory device according to
claim 16
, wherein the fifth and sixth MOS transistors are turned on alternately.
US09/750,228 1999-12-30 2000-12-29 Semiconductor memory device having a plurality of banks sharing a column control unit Expired - Lifetime US6385121B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR99-66395 1999-12-30
KR10-1999-0066395A KR100520179B1 (en) 1999-12-30 1999-12-30 IO structure of semiconductor memory device
KR1999-66395 1999-12-30

Publications (2)

Publication Number Publication Date
US20010015931A1 true US20010015931A1 (en) 2001-08-23
US6385121B2 US6385121B2 (en) 2002-05-07

Family

ID=19633533

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/750,228 Expired - Lifetime US6385121B2 (en) 1999-12-30 2000-12-29 Semiconductor memory device having a plurality of banks sharing a column control unit

Country Status (2)

Country Link
US (1) US6385121B2 (en)
KR (1) KR100520179B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070014171A1 (en) * 2005-07-12 2007-01-18 Hynix Semiconductor Inc. Semiconductor memory device

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3977027B2 (en) * 2001-04-05 2007-09-19 セイコーエプソン株式会社 Semiconductor memory device
KR100642636B1 (en) 2004-07-30 2006-11-10 삼성전자주식회사 Semiconductor memory device and methode of arranging data lines thereof
KR100720260B1 (en) * 2004-11-15 2007-05-22 주식회사 하이닉스반도체 Local input output line precharge circuit of semiconductor memory device
JP2006216136A (en) * 2005-02-02 2006-08-17 Toshiba Corp Semiconductor memory device
US7428168B2 (en) * 2005-09-28 2008-09-23 Hynix Semiconductor Inc. Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size
KR100668513B1 (en) * 2005-09-28 2007-01-12 주식회사 하이닉스반도체 Semiconductor memory device
US7489585B2 (en) * 2005-09-29 2009-02-10 Hynix Semiconductor Inc. Global signal driver for individually adjusting driving strength of each memory bank
US7778089B2 (en) 2006-09-29 2010-08-17 Hynix Semiconductor Inc. Semiconductor memory device including write driver control circuit and write driver control method
KR100855269B1 (en) * 2007-02-14 2008-09-01 주식회사 하이닉스반도체 Semiconductor memory device including write driver control circuit
KR100935720B1 (en) * 2007-05-17 2010-01-08 주식회사 하이닉스반도체 Input output line sense amplifier and semiconductor device
KR101393309B1 (en) 2008-02-18 2014-05-09 삼성전자주식회사 Semiconductor device including a plurality of bus lines
KR101046703B1 (en) * 2009-03-25 2011-07-05 주식회사 하이닉스반도체 Data write circuit and semiconductor memory device using same
KR101039863B1 (en) * 2009-09-02 2011-06-09 주식회사 하이닉스반도체 Semiconductor memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057747B2 (en) * 1990-11-01 2000-07-04 日本電気株式会社 Semiconductor memory device
US5835436A (en) * 1995-07-03 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Dynamic type semiconductor memory device capable of transferring data between array blocks at high speed
JPH1173763A (en) * 1997-08-28 1999-03-16 Toshiba Corp Semiconductor integrated circuit device
KR100266750B1 (en) * 1997-11-20 2000-09-15 윤종용 High density semiconductor memory device capable of reducing row precharge time
KR100261219B1 (en) * 1997-12-08 2000-07-01 윤종용 Semiconductor memory device having isolation gates operating independently
KR100363079B1 (en) * 1999-02-01 2002-11-30 삼성전자 주식회사 Multi-bank memory device having shared IO sense amplifier by adjacent memory banks
KR100322540B1 (en) * 1999-07-14 2002-03-18 윤종용 Memory device for minimizing the layout area occupied by input and output sense amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070014171A1 (en) * 2005-07-12 2007-01-18 Hynix Semiconductor Inc. Semiconductor memory device
US7443752B2 (en) * 2005-09-28 2008-10-28 Hynix Semiconductor Inc. Semiconductor memory device amplifying data

Also Published As

Publication number Publication date
KR100520179B1 (en) 2005-10-10
KR20010059017A (en) 2001-07-06
US6385121B2 (en) 2002-05-07

Similar Documents

Publication Publication Date Title
US10121523B2 (en) Memory bank signal coupling buffer and method
US8699281B2 (en) Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
US6985394B2 (en) Integrated circuit devices including input/output line pairs and precharge circuits and related memory devices
US6094375A (en) Integrated circuit memory devices having multiple data rate mode capability and methods of operating same
US7035161B2 (en) Semiconductor integrated circuit
US6385121B2 (en) Semiconductor memory device having a plurality of banks sharing a column control unit
US6327214B1 (en) Multi-bank memory device having input and output amplifier shared by adjacent memory banks
US6614710B2 (en) Semiconductor memory device and data read method thereof
US20080316840A1 (en) Input/output line sense amplifier and semiconductor memory device using the same
JP2004079099A (en) Semiconductor memory
US20040047404A1 (en) Semiconductor memory device having repeaters located at the global input/output line
TWI253083B (en) Multi-port memory device
US20060221757A1 (en) Multi-port memory device
US7269041B2 (en) Multi-port memory device
JP3792800B2 (en) Semiconductor memory device
US7911818B2 (en) Content addressable memory having bidirectional lines that support passing read/write data and search data
KR100388217B1 (en) Semiconductor Memory
TW200537523A (en) Bus connection circuit for read operation of multi-port memory device
JP3599963B2 (en) Semiconductor integrated circuit
US7133303B2 (en) Dynamic type semiconductor memory apparatus
US6445604B2 (en) Channel driving circuit of virtual channel DRAM
KR100732287B1 (en) A semiconductor memory device driver by a packet command
US7969800B2 (en) Semiconductor memory apparatus
KR20010059962A (en) Semiconductor memory device
JP2002251882A (en) Semiconductor memory and pre-charge method for its bit line

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, BYUNG JAE;REEL/FRAME:011670/0785

Effective date: 20010321

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: CHANGE OF NAME;ASSIGNOR:HYUNDAI ELECTRONICS INDUSTRIES CO., LTD.;REEL/FRAME:026828/0688

Effective date: 20010329

AS Assignment

Owner name: 658868 N.B. INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:027233/0644

Effective date: 20110822

AS Assignment

Owner name: ROYAL BANK OF CANADA, CANADA

Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196

Effective date: 20111223

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: CONVERSANT IP N.B. 868 INC., CANADA

Free format text: CHANGE OF NAME;ASSIGNOR:658868 N.B. INC.;REEL/FRAME:032439/0547

Effective date: 20140101

AS Assignment

Owner name: CONVERSANT IP N.B. 868 INC., CANADA

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

Owner name: CONVERSANT IP N.B. 276 INC., CANADA

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344

Effective date: 20140611

AS Assignment

Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA

Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001

Effective date: 20140611

Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA

Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001

Effective date: 20140611

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:036159/0386

Effective date: 20150514

AS Assignment

Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA

Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136

Effective date: 20180731

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424

Effective date: 20180731

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424

Effective date: 20180731

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054371/0684

Effective date: 20201028