US20010009304A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20010009304A1 US20010009304A1 US09/780,461 US78046101A US2001009304A1 US 20010009304 A1 US20010009304 A1 US 20010009304A1 US 78046101 A US78046101 A US 78046101A US 2001009304 A1 US2001009304 A1 US 2001009304A1
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- insulating film
- silicon oxide
- interconnection layer
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Definitions
- the present invention relates to a semiconductor device and more specifically to a semiconductor device ensuring the planarity of an interlayer insulating film and preventing displacement of an interconnection thereby achieving a high degree of integration.
- a semiconductor device including an MOS transistor will be described with reference to the drawings.
- a plurality of gate electrode portions 55 including a polycrystalline silicon film 55 a , a tungsten silicide film 55 b and a silicon oxide film 55 c are formed on the surface of a silicon semiconductor substrate 51 with a gate insulating film 54 interposed therebetween.
- a pair of impurity diffusion layers 56 a , 56 b are formed at the surface of silicon semiconductor substrate 51 with one gate electrode portion 55 sandwiched therebetween.
- a pair of impurity diffusion layers 56 c , 56 d are formed at the surface of silicon semiconductor substrate 51 with another gate electrode portion 55 sandwiched therebetween.
- a sidewall insulating film 57 is formed on the both side surfaces of gate electrode portion 55 .
- Gate electrode portion 55 and a pair of impurity diffusion layers 56 a , 56 b constitute one MOS transistor. Further, gate electrode portion 55 and a pair of impurity diffusion layers 56 c , 56 d constitute another MOS transistor.
- Gate electrode portion 55 of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separating oxide film 53 that is formed in an element separating trench 52 at the surface of silicon semiconductor substrate 51 .
- a silicon oxide film 58 is formed on silicon semiconductor substrate 51 to cover gate electrode portion 55 .
- a silicon oxide film doped with boron and phosphorous that is, a BPSG (Boro-Phospho-Silicate-Glass) film 59 is formed.
- a silicon oxide film 60 is formed on BPSG film 59 .
- a plurality of second interconnection layers 62 including a polycrystalline silicon film 62 a , a tungsten silicide film 62 b and a silicon oxide film 62 c are formed on silicon oxide film 60 .
- One second interconnection layer 62 is electrically connected to gate electrode portion 55 as a first interconnection layer by a polycrystalline silicon film filled in contact hole 61 a that is formed in BPSG film 59 and silicon oxide films 60 , 58 .
- Another second interconnection layer 62 is electrically connected to impurity diffusion layer 56 b by a polycrystalline silicon film filled in a contact hole 61 b that is formed in BPSG film 59 and silicon oxide films 60 , 58 .
- a silicon oxide film 63 is formed on silicon oxide film 60 to cover second interconnection layer 62 .
- a BPSG film 64 is also formed on silicon oxide film 63 .
- a plurality of third interconnection layers 67 are formed on BPSG film 64 .
- Third interconnection layers 67 are electrically connected to gate electrode portion 55 and impurity diffusion layers 56 c , 56 d by plugs 66 a , 66 b , 66 c e.g. of tungsten filled in contact holes 65 a , 65 b , 65 c that are formed in BPSG films 59 , 64 and silicon oxide films 63 , 60 , 58 .
- Third interconnection layer 67 is also electrically connected to second interconnection layer 62 by a plug 66 d filled in a contact hole 65 d that is formed in BPSG film 64 and silicon oxide film 63 .
- the conventional semiconductor device has such a configuration.
- element separating trench 52 is formed at the surface of silicon semiconductor substrate 51 by prescribed photolithography and RIE (Reactive Ion Etching) methods.
- RIE Reactive Ion Etching
- a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is then formed on silicon semiconductor substrate 51 by the CVD method.
- the silicon oxide film is polished by the CMP (Chemical Mechanical Polishing) method to form separating oxide film 53 in element separating trench 52 .
- Gate oxide film 54 having a film thickness of 5 to 15 nm is then formed on the surface of silicon semiconductor substrate 51 by the thermal oxidation method.
- gate oxide film 54 On gate oxide film 54 , a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed.
- RIE methods By implanting an impurity of a prescribed conductive type into silicon semiconductor substrate 51 using gate electrode portion 55 as a mask, a region (not shown) of a comparatively low impurity concentration is formed.
- a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is then formed on silicon semiconductor substrate 51 by the CVD method.
- the silicon oxide film is etched by the RIE method to form sidewall insulating film 57 on the both side surfaces of gate electrode portion 55 .
- a region (not shown) of a comparatively high impurity concentration is formed.
- a pair of impurity diffusion layers 56 a , 56 b and a pair of impurity diffusion layers 56 c , 56 d are respectively formed at the surface of silicon semiconductor substrate 51 with gate electrode potions 55 sandwiched therebetween.
- comparatively thin silicon oxide film 58 is formed on silicon semiconductor substrate 51 by the CVD method to cover gate electrode portion 55 .
- BPSG film 59 is formed on silicon oxide film 58 by the CVD method.
- BPSG film 59 is heated at a temperature of approximately 850° C. to locally planarize the surface of BPSG film 59 .
- BPSG film 59 is reflowed.
- Locally planarizeed BPSG film 59 is etched by the RIE method or a hydrofluoric acid solution to make BPSG film 59 thinner.
- comparatively thin silicon oxide film 60 is formed on BPSG film 59 by the CVD method.
- contact hole 61 a exposing the surface of tungsten silicide film 55 b of gate electrode portion 55 and contact hole 61 b exposing the surface of impurity diffusion layer 56 b are formed in BPSG film 59 and silicon oxide films 60 , 58 by the prescribed photolithography and RIE methods.
- a polycrystalline silicon film, a tungsten silicide film and a silicon oxide film (they are not shown) are then formed on silicon oxide film 60 by the CVD method.
- Second interconnection layer 62 including polycrystalline silicon film 62 a , tungsten silicide film 62 b and silicon oxide film 62 c is then formed by the prescribed photolithography and RIE methods.
- comparatively thin silicon oxide film 63 is formed on silicon oxide film 60 by the CVD method to cover second interconnection layer 62 .
- BPSG film 64 is then formed on silicon oxide film 63 by the CVD method.
- BPSG film 64 is heated at a temperature of approximately 800° C. to locally planarize the surface of BPSG film 64 . Thereafter, BPSG film 64 is etched by the RIE method or a hydrofluoric acid solution , if necessary, to further planarize the surface of BPSG film 64 .
- contact hole 65 a exposing the surface of tungsten silicide film 55 b of gate electrode portion 55
- contact holes 65 b , 65 c exposing the surfaces of impurity diffusion layers 56 c , 56 d
- contact hole 65 d exposing the surface of tungsten silicide film 62 b of second interconnection layer 62
- BPSG film 64 is formed in BPSG film 64 by the prescribed photolithography and RIE methods.
- an impurity of a prescribed conductive type is implanted in contact holes 65 a , 65 b , 65 c , 65 d .
- the impurity is activated by heating at a temperature of 750° C. lower than the heating temperature for locally planaiizing BPSG film 64 .
- a tungsten thin film (not shown) is formed on BPSG film 64 by the CVD method using WF 6 , for example, as a material.
- the tungsten thin film is etched by the RIE method to form tungsten plugs (not shown) in contact holes 65 a , 65 b , 65 c , 65 d .
- An aluminum copper alloy film (not shown) is formed on BPSG film 64 by the sputtering method.
- the third interconnection layers electrically connected to gate electrode portion 55 , impurity diffusion layers 56 c , 56 d and the like are formed by the prescribed photolithography and RIE methods to complete the semiconductor device shown in FIG. 47.
- the conventional semiconductor device is manufactured as described above.
- the NA value (Numerical Aperture) of a lens used for an exposing device is set at a higher value to improve resolution in photolithography.
- the NA value of a lens is set at a higher value, it is difficult to ensure the depth of focus.
- the polycrystalline silicon or tungsten may be left without being etched at the step portions of BPSG films 59 , 64 . Therefore, more planarized surface shapes are required for BPSG film 59 serving as the base of second interconnection layer 62 and BPSG film 64 serving as the base of third interconnection layer 67 .
- the step portions of the BPSG films are locally planarized by heating.
- the degree of planarization depends on the concentration of boron and phosphorous contained in the BPSG films, the heating temperature and the like, and the BPSG films are locally planarized to a greater extent as the concentration of boron and phosphorous is higher or as the temperature is higher.
- the displacement can be suppressed to approximately 1 ⁇ m by setting lower the heating temperature for upper layer BPSG film 64 .
- the lower temperature of the heating for the upper layer BPSG film is approaching a limit.
- suppressing displacement of second interconnection layer 62 to approximately 0.1 ⁇ m is required. Therefore, simultaneously ensuring the planarity of the base of the second interconnection layer and the like and preventing displacement of the second interconnection layer are expected to be extremely difficult in the conventional semiconductor device. As a result, easy miniaturization of LSIs is expected to be difficult.
- the present invention aims at solving the expected problems above and its object is to provide a semiconductor device ensuring the planarity of the base of each interconnection layer and suppressing displacement of the interconnection layer in the process of manufacturing the semiconductor device thereby achieving a high degree of integration.
- a semiconductor device in one aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and a second interlayer insulating film.
- the semiconductor substrate has a main surface.
- the first interconnection layer is formed on the semiconductor substrate.
- the first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer.
- the second interconnection layer is formed on the first interlayer insulating film.
- the second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer.
- the first interlayer insulating film has a polished top surface, or a film having a polished top surface is laminated on the first interlayer insulating film.
- the first interlayer insulating film is polished according to the configuration, the surface of the first interlayer insulating film is planarized over the entire wafer surface in the manufacturing process.
- the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film.
- heat from the process is applied to the first interlayer insulating film.
- the surface of the first interlayer insulating film is planarized over the entire wafer surface at this time, transformation of the first interlayer insulating film is suppressed compared with the case in which the surface is rough.
- displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the first interlayer insulating film as its base can be suppressed.
- a semiconductor device having a higher degree of integration can be obtained.
- the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed, and the reflowed impurity-doped insulating film has the polished top surface.
- polishing is provided for the impurity-doped insulating film of which roughness of the surface is locally eased by reflow. Therefore, compared with a film of which roughness of the surface is not eased, variation in the degree of polishing in a wafer surface, and variation in the film thickness of the impurity-doped insulating film in the wafer surface can be reduced in polishing the impurity-doped insulating film.
- the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed and an impurity-non-doped insulating film that is formed on the reflowed impurity-doped insulating film and does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
- the impurity-doped insulating film is covered by the impurity-non-doped insulating film. Even if the impurity-doped insulating film is reflowed and transformed by heat in forming the second interlayer insulating film, therefore, the transformation is suppressed. As a result, displacement of the second interconnection layer can be further suppressed.
- the first interlayer insulating film includes an impurity-non-doped insulating film that does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
- the impurity-non-doped insulating film does not contain the prescribed impurities. Therefore, the impurity-non-doped insulating film is not reflowed and transformed by heat in forming the second interlayer insulating film. Thus, the second interconnection layer is not displaced.
- the first interlayer insulating film includes a first dipped insulating film formed on the semiconductor substrate by the Spin-On-Glass method to fill a space between the first interconnection layers, and the impurity-non-doped insulating film is formed on the first dipped insulating films.
- the first dipped insulating film eases the roughness of the surface of the impurity-non-doped insulating film before it is polished.
- variation in the degree of polishing in the wafer surface can be reduced in polishing the impurity-non-doped insulating film.
- the second interlayer insulating film includes an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
- the second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film.
- the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can further be suppressed.
- the second interlayer insulating film includes a second dipped insulating film formed on the first interlayer insulating film by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
- the second interconnection layer is fixed more strongly on the first interlayer insulating film by the second dipped insulating film.
- the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can be suppressed effectively.
- the roughness of the wafer surface can also be eased by the second dipped insulating film.
- the planarity of a film formed on the second dipped insulating film can be ensured easily.
- the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the second dipped insulating film.
- a semiconductor device in another aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and second interlayer insulating film.
- the semiconductor substrate has a main surface.
- the first interconnection layer is formed on the semiconductor substrate.
- the first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer.
- the second interconnection layer is formed on the first interlayer insulating film.
- the second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer.
- the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed.
- the second interlayer insulating film has an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
- the surface of the first interlayer insulating film is locally planarized by the impurity-doped insulating film in the manufacturing process.
- the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film.
- the second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film.
- displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the impurity-doped insulating film can be suppressed.
- a semiconductor device having a higher degree of integration can be obtained.
- the interconnection coating insulating film has a thickness of at least the thickness of the second interconnection layer.
- the second interconnection layer is fixed more reliably on the first interlayer insulating film by the interconnection coating insulating film.
- displacement of the second interconnection layer can be suppressed more reliably.
- the second interlayer insulating film is polished or reflowed.
- the interconnection coating insulating film includes a third dipped insulating film formed by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
- the roughness of the wafer surface is eased by the third dipped insulating film, and thereafter the planarity of a film formed on the third dipped insulating film can easily be ensured.
- the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the third dipped insulating film.
- an insulating film that does not contain prescribed impurities is formed on the top surface or the bottom surface of the impurity-doped insulating film.
- the first interlayer insulating film includes a substrate coating insulating film covering the semiconductor substrate.
- At least one species of impurities selected from the group of boron, phosphorous and arsenic can be applied as the prescribed impurities.
- FIG. 1 is a cross sectional view showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 1 in the first embodiment.
- FIGS. 3 to 8 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 2 to 7 in the first embodiment.
- FIGS. 9 and 10 are cross sectional views showing first and second variations of the semiconductor device in the first embodiment.
- FIG. 11 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 10 in the first embodiment.
- FIG. 12 is a cross sectional view showing a step performed after the step shown in FIG. 11 in the first embodiment.
- FIG. 13 is a cross sectional view showing a semiconductor device according to a second embodiment of the present invention.
- FIG. 14 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 13 in the second embodiment.
- FIG. 15 is a cross sectional view showing a step performed after the step shown in FIG. 14 in the second embodiment.
- FIG. 16 is a cross sectional view showing a semiconductor device according to a third embodiment of the present invention.
- FIG. 17 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 16 in the third embodiment.
- FIG. 18 is a cross sectional view showing a step performed after the step shown in FIG. 17 in the third embodiment.
- FIG. 19 is a cross sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 20 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 19 in the fourth embodiment.
- FIG. 21 is a cross sectional view showing a step performed after the step shown in FIG. 20 in the fourth embodiment.
- FIG. 22 is a cross sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
- FIG. 23 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 22 in the fifth embodiment.
- FIG. 24 is a cross sectional view showing a step performed after the step shown in FIG. 23 in the fifth embodiment.
- FIG. 25 is a cross sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
- FIG. 26 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 25 in the sixth embodiment.
- FIG. 27 is a cross sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
- FIG. 28 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 27 in the seventh embodiment.
- FIG. 29 is a cross sectional view showing a semiconductor device according to an eighth embodiment of the present invention.
- FIG. 30 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 29 in the eighth embodiment.
- FIGS. 31 and 32 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 30 and 31 in the eighth embodiment.
- FIG. 33 is a cross sectional view showing a semiconductor device according to a ninth embodiment of the present invention.
- FIG. 34 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 33 in the ninth embodiment.
- FIGS. 35 and 36 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 34 and 35 in the ninth embodiment.
- FIG. 37 is a cross sectional view showing a semiconductor device according to a tenth embodiment of the present invention.
- FIG. 38 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 37 in the tenth embodiment.
- FIG. 39 is a cross sectional view showing a step performed after the step shown in FIG. 38 in the tenth embodiment.
- FIG. 40 is a cross sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.
- FIG. 41 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 40 in the eleventh embodiment.
- FIG. 42 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 41 in the eleventh embodiment.
- FIG. 43 is a cross sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.
- FIG. 44 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 43 in the twelfth embodiment.
- FIG. 45 is a cross sectional view showing a semiconductor device according to a thirteenth embodiment of the present invention.
- FIG. 46 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 45 in the thirteenth embodiment.
- FIG. 47 is a cross sectional view showing a conventional semiconductor device.
- FIG. 48 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 47.
- FIGS. 49 to 53 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 48 to 52 .
- a semiconductor device will be described with reference to the drawings.
- a plurality of gate electrode portions 5 including a polycrystalline silicon film 5 a , a tungsten silicide film 5 b and a silicon oxide film 5 c are formed on the surface of a silicon semiconductor substrate 1 with a gate insulating film 4 interposed therebetween.
- a pair of impurity diffusion layers 6 a , 6 b are formed at the surface of silicon semiconductor substrate 1 with one gate electrode portion 5 sandwiched therebetween.
- a pair of impurity diffusion layers 6 c , 6 d are formed at the surface of silicon semiconductor substrate 1 with another gate electrode portion 5 sandwiched therebetween.
- a sidewall insulating film 7 is formed on the both side surfaces of gate electrode portion 5 .
- Gate electrode portion 5 and a pair of impurity diffusion layers 6 a , 6 b constitute one MOS transistor.
- Gate electrode portion 5 and a pair of impurity diffusion layers 6 c , 6 d constitute another MOS transistor.
- Gate electrode portion 5 of each MOS transistor serves as a first interconnection layer.
- MOS transistors are electrically insulated from one another by a separating oxide film 3 that is formed in an element separating trench 2 at the surface of silicon semiconductor substrate 1 .
- a silicon oxide film 8 is formed on silicon semiconductor substrate 1 to cover gate electrode portion 5 .
- a BPSG film 9 is formed on silicon oxide film 8 .
- a silicon oxide film 10 is formed on polished BPSG film 9 .
- a plurality of second interconnection layers 12 including a polycrystalline silicon film 12 a , a tungsten silicide film 12 b and a silicon oxide film 12 c are formed on silicon oxide film 10 .
- One second interconnection layer 12 is electrically connected to gate electrode portion 5 as the first interconnection layer by a polycrystalline silicon film filled in a contact hole 11 a that is formed in BPSG film 9 and silicon oxide films 10 , 8 .
- Another second interconnection layer 12 is electrically connected to impurity diffusion layer 6 b by a polycrystalline silicon film filled in a contact hole 11 b that is formed in BPSG film 9 and silicon oxide films 10 , 8 .
- a silicon oxide film 13 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- Silicon oxide film 13 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness of polycrystalline silicon film 12 a + thickness of tungsten silicide film 12 b ) as the thickness allowing fixing and holding of second interconnection layer 12 on silicon oxide film 10 .
- a BPSG film 14 is also formed on the silicon oxide film 13 .
- BPSG film 14 is reflowd by heating and its surface is planarized.
- a plurality of third interconnection layers 17 including an aluminum copper alloy film are formed on BPSG film 14 .
- Third interconnection layers 17 are electrically connected to gate electrode portion 5 and impurity diffusion layers 6 c , 6 d by plugs 16 a , 16 b , 16 c filled in contact holes 15 a , 15 b , 15 c that are formed in BPSG films 14 , 9 and silicon oxide films 13 , 10 , 8 .
- Third interconnection layer 17 is electrically connected to second interconnection layer 12 by a plug 16 d filled in a contact hole 15 d that is formed in BPSG film 14 and silicon oxide film 13 .
- the semiconductor device according to the embodiment has such a configuration.
- an element separating trench 2 is formed at the surface of silicon semiconductor substrate 1 by prescribed photolithography and RIE methods.
- a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is formed on silicon semiconductor substrate 1 by the CVD method.
- the silicon film is polished by the CMP method to form a separating oxide film 3 in element separating trench 2 .
- gate oxide film 4 having a film thickness of 5 to 15 nm is formed on the surface of silicon semiconductor substrate 1 by the thermal oxidation method.
- gate oxide film 4 On gate oxide film 4 , a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed.
- a plurality of gate electrode portions 5 as the first interconnection layers including polycrystalline silicon film 5 a , tungsten silicide film 5 b and silicon oxide film 5 c are formed by the prescribed photolithography and RIE methods.
- a region (not shown) of a comparatively low impurity concentration is formed.
- a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is formed on silicon semiconductor substrate 1 by the CVD method.
- the silicon oxide film is etched by the RIE method to form sidewall insulating film 7 on the both side surfaces of gate electrode portion 5 .
- a pair of impurity diffusion layers 6 a , 6 b and a pair of impurity diffusion layers 6 c , 6 d are formed at the surface of silicon semiconductor substrate 1 with gate electrode portions 5 interposed therebetween.
- silicon oxide film 8 having a film thickness of approximately 10 nm is then formed on silicon semiconductor substrate 1 by the CVD method.
- BPSG film 9 is formed on silicon oxide film 8 by the CVD method.
- BPSG film 9 is heated at a temperature of approximately 800° C. to locally planarize the surface of BPSG film 9 .
- BPSG film 9 is reflowed. While the local roughness of the wafer surface is eased at this time, a, step cannot be eased by the BPSG film and an “absolute step” is caused at a boarder portion, for example, between a memory cell region in which MOS transistors are integrated and a region like a periphery region in which elements such as transistors are not so integrated as in the memory cell region.
- locally planarized BPSG film 9 is polished by approximately 150 nm by the CMP method. This polishing removes the absolute step in BPSG film 9 , and the surface of BPSG film 9 is planarized over the entire wafer surface.
- silicon oxide film 10 having a film thickness of approximately 100 nm is formed on polished BPSG film 9 by the CVD method. Then, contact hole 11 a exposing the surface of tungsten silicide film 5 b of gate electrode portion 5 and contact hole 11 b exposing the surface of impurity diffusion layer 6 b are formed by the prescribed photolithography and RIE methods. To fill contact holes 1 a and 11 b , a polycrystalline silicon film (not shown) is formed on silicon oxide film 10 . Then, a tungsten silicide film and a silicon oxide film (they are not shown) are formed by the CVD method.
- second interconnection layers 12 including polycrystalline silicon film 12 a , tungsten silicide film 12 b and silicon oxide film 12 c are formed by the prescribed photolithography and RIE method. It is noted that a polycrystalline silicon plugs are formed in contact holes 11 a and 11 b at this time.
- silicon oxide film 13 is then formed on silicon oxide film 10 by the CVD method. Silicon oxide film 13 has a thickness of at least the substantial thickness of the second interconnection layer (thickness of polycrystalline silicon film 12 a + thickness of tungsten silicide film 12 b ) as the thickness allowing fixing and holding of second interconnection layer 12 on silicon oxide film 10 .
- BPSG film 14 is formed on silicon oxide film 13 by the CVD method.
- BPSG film 14 is heated at a temperature of approximately 800° C. to reflow and locally planarize the surface.
- the reflowed surface of BPSG film 14 may be etched and made thinner by the RIE method or a hydrofluoric acid solution, if necessary, so as to make a smoother surface.
- the reflowed surface of BPSG film 14 may also be polished by the CMP method.
- contact hole 15 a exposing the surface of tungsten silicide film 5 b of gate electrode portion 5
- contact hole 15 b exposing the surface of impurity diffusion layer 6 c
- contact hole 15 c exposing the surface of impurity diffusion layer 6 d
- contact hold 15 d exposing the surface of tungsten silicide film 12 b of second interconnection layer 12 are formed by the prescribed photolithography and RIE methods. Then, an impurity of a prescribed conductive type is implanted into contact holes 15 a , 15 b , 15 c , 15 d , and prescribed heating is performed to activate the impurity.
- the heating temperature at this time is lower than the heating temperature for reflowing BPSG film 14 .
- tungsten plugs are formed in contact holes 15 a , 15 b , 15 c , 15 d by the CVD method using WF 6 or the like as a material.
- An aluminum copper alloy film is formed on BPSG film 14 by the sputtering method.
- the third interconnection layer is formed by the prescribed photolithography and RIE methods. The semiconductor device shown in FIG. 1 is completed in this matter.
- BPSG film 9 is polished in the step shown in FIG. 4.
- the BPSG film is planarized over the entire wafer surface. Since BPSG film 9 is planarized, halation or the like is suppressed in patterning second interconnection layer 12 in the step shown in FIG. 5, and second interconnection layer 12 with high dimensional precision is formed.
- BPSG film 14 is heated and reflowed. At this time, BPSG film 9 is also about to reflow due to the heating. Since BPSG film 9 is planarized over the entire wafer surface, however, transformation due to reflowing of BPSG film 9 is suppressed compared with the case where the surface of the BPSG film is rough and stepped. Thus, displacement of second interconnection layer 12 causing second interconnection layer 12 to be moved due to deformation of BPSG film 9 can be suppressed.
- silicon oxide film 13 formed to cover second interconnection layer 12 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness of polycrystalline silicon film 12 a + thickness of tungsten silicide film 12 b ).
- second interconnection layer 12 is fixed more strongly on silicon oxide film 10 by silicon oxide film 13 , and displacement of second interconnection layer 12 can be further suppressed.
- a semiconductor device having a high degree of integration can be obtained.
- silicon oxide films 8 , 10 can be patterned advantageously. Silicon oxide film 10 has the effect of improving adhesion of a resist in patterning second interconnection layer 12 . Silicon oxide film 13 can prevent diffusion of boron or phosphorous in BPSG film 14 to second interconnection layer 12 .
- silicon oxide film 13 can prevent oxidation of second interconnection layer 12 when BPSG film 14 is heated in the atmosphere of water vapor.
- FIG. 9 A first variation of the semiconductor device shown in FIG. 1 will be described in the following with reference to the drawing.
- a silicon oxide film 18 having a film thickness of approximately 100 nm is formed on BPSG film 14 .
- a third interconnection layer 17 is formed on silicon oxide film 18 Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1, the same elements have the same reference characters and their description will not be repeated.
- silicon oxide film 18 can also prevent formation of particles on the surface of BPSG film 14 when BPSG film 14 absorbs moisture. Thus, the reliability of third interconnection layer 17 can be prevented from lowering due to the particles. Silicon oxide film 18 also has the effect of improving adhesion of a resist in patterning third interconnection layer 17 .
- a film formed on BPSG film 14 a laminate film of a silicon oxynitride film or a silicon nitride film and a silicon oxide film may be employed in addition to a silicon oxide film.
- silicon oxide film 18 can also serve as a film for preventing reflection in the lithography for forming contact holes 15 a , 15 b , 15 c . Approximately 40 nm is preferred for a film thickness in this case.
- FIG. 10 A second variation of the semiconductor device shown in FIG. 1 will be described in the following with reference to the drawing.
- a PSG (Phospho Silicate Glass) film 20 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- BPSG film 14 is formed on PSG film 20 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1, the same elements have the same reference characters and their description will not be repeated.
- steps before formation of second interconnection layer 12 on silicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 .
- PSG film 20 is formed on silicon oxide film 10 by the CVD method.
- PSG film 20 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness of polycrystalline silicon film 12 a +thickness of tungsten silicide film 12 b ).
- steps similar to the steps shown in FIGS. 6 to 8 are performed to form contact holes 15 a , 15 b , 15 c , 15 d .
- tungsten plugs for filling contact holes 15 a , 15 b , 15 c , 15 d are formed and the third interconnection layer such as an aluminum copper alloy film is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 10.
- second interconnection layer 12 is covered by PSG film 20 . Since PSG film 20 is not softened by heating for reflowing BPSG film 14 , second interconnection layer 12 can be fixed more strongly on silicon oxide film 10 . Thus, even if PSG film 20 is applied in stead of silicon oxide film 13 shown in FIG. 1, displacement of second interconnection layer 12 can be suppressed.
- a semiconductor device will be described with reference to the drawings.
- a comparatively thick PSG film 22 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- PSG film 22 is polished by the CMP method.
- Silicon oxide film 18 is formed on PSG film 22 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- steps before formation of second interconnection layer 12 on silicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment.
- comparatively thick PSG film 22 is then formed on silicon oxide film 10 by the CVD method.
- PSG film 22 is polished by the CMP method to planarize PSG film 22 over the entire wafer surface.
- Silicon oxide film 18 is formed on polished PSG film 22 by the CVD method.
- contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods.
- tungsten plugs are filled in contact holes 15 a , 15 b , 15 c , 15 d and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 13.
- second interconnection layer 12 is covered by comparatively thick PSG film 22 , second interconnection layer 12 can be fixed more strongly on silicon oxide film 10 . As a result, displacement of second interconnection layer 12 can be further suppressed. Since the surface of PSG film 22 is polished by the CMP method, the surface is planarized over the entire wafer surface. Thus, third interconnection layer 17 with high dimensional precision can easily be formed. As described above, a semiconductor device having a high degree of integration can be obtained.
- a semiconductor device will be described with reference to the drawings.
- PSG film 20 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- PSG film 20 has a thickness of at least the substantial thickness of second interconnection layer 12 .
- a comparatively thick silicon oxide film 23 is formed on PSG film 20 .
- Silicon oxide film 23 is polished by the CMP method.
- Third interconnection layer 17 is formed on silicon oxide film 23 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- steps before formation of second interconnection layer 12 on silicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment.
- PSG film 20 is then formed on silicon oxide film 10 by the CVD method.
- Comparatively thick silicon oxide film 23 is formed on PSG film 20 by the CVD method.
- PSG film 23 is polished by the CMP method to planarize the surface of PSG film 23 over the entire wafer surface. Then, contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are formed in contact holes 15 a , 15 b , 15 c , 15 d and the third interconnection layer is formed on silicon oxide film 23 to complete the semiconductor device shown in FIG. 16.
- second interconnection layer 12 is fixed more strongly on silicon oxide film 10 by PSG film 20 , displacement of second interconnection layer 12 is further suppressed. Further, silicon oxide film 23 can prevent diffusion of phosphorous contained in PSG film 20 to third interconnection layer 17 . Since the surface of silicon oxide film 23 is polished by the CMP method, the surface is planarized over the entire wafer surface. Thus, third interconnection layer 17 with higher dimensional precision can easily be formed.
- a semiconductor device will be described with reference to the drawings.
- an insulating film (hereinafter referred to as an “SOG film”) 24 is formed on silicon oxide film 10 by a dipping method (Spin-On-Glass method)to fill a space between second interconnection layers 12 .
- BPSG film 21 is formed on SOG film 24 .
- BPSG film 21 is reflowed by heating.
- Silicon oxide film 18 is formed on reflowed BPSG film 21 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- steps before formation of second interconnection layer 12 on silicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment 1.
- SOG film 24 is then formed on silicon oxide film 10 by the dipping method.
- BPSG film 21 is formed on SOG film 24 by the CVD method.
- BPSG film 21 is heated to reflow BPSG film 21 .
- Silicon oxide film 18 is formed on reflowed BPSG film 21 .
- contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed lithography and RIE methods. Tungsten plugs are filled in contact holes 15 a , 15 b , 15 c , 15 d and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 19.
- Second interconnection layer 12 is fixed more strongly on silicon oxide film 10 by SOG film 24 .
- SOG film 24 Since the roughness of the wafer surface is eased by SOG film 24 , the roughness of the surface of BPSG film 21 formed on SOG film 24 is eased. Accordingly, the surface of BPSG film 21 after it is reflowed is further planarized. Therefore, third interconnection layer 17 with high dimensional precision can easily be formed.
- a semiconductor device will be described with reference to the drawings.
- SOG film 24 is formed on silicon oxide film 10 to fill a space between second interconnection layers 12 .
- a silicon oxide film 25 is formed on SOG film 24 .
- Silicon oxide film 25 is polished by the CMP method.
- Third interconnection layer 17 is formed on silicon oxide film 25 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- comparatively thick silicon oxide film 25 is formed on SOG film 24 by the CVD method after the step shown in FIG. 20 described in the fourth embodiment.
- silicon oxide film 25 is polished by the CMP method. Thus, the surface of silicon oxide film 25 is planarized over the entire wafer surface. Then, contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a , 15 b , 15 c , 15 d and the third interconnection layer is formed on silicon oxide film 25 to complete the semiconductor device shown in FIG. 22.
- Second interconnection layer 12 is fixed more strongly on silicon oxide film 10 by SOG film 24 .
- displacement of silicon interconnection layer 12 can be suppressed effectively.
- the roughness of the wafer surface is eased by SOG film 24
- the roughness of the surface of silicon oxide film 25 formed on SOG film 24 is eased. Accordingly, variation in the degree of polishing can be suppressed in polishing silicon oxide film 25 by the CMP method.
- silicon oxide film 25 is formed on SOG film 24 , a PSG film may be formed instead.
- a semiconductor device will be described with reference to the drawings.
- an SOG film 26 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- SOG film 26 is polished by the CMP method.
- Third interconnection layer 17 is formed on SOG film 26 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- Steps before formation of second interconnection layer 12 on silicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment.
- comparatively thick SOG film 26 is then formed on silicon oxide film 10 .
- SOG film 26 is polished by the CMP method
- contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a , 15 b , 15 c , 15 d and the third interconnection layer is formed on SOG film 26 to complete the semiconductor device shown in FIG. 25.
- Second interconnection layer 12 is fixed strongly on silicon oxide film 10 by comparatively thick SOG film 26 . Therefore, BPSG film 9 is planarized over the entire wafer surface and displacement of second interconnection layer 12 can be further suppressed. Since SOG film 26 is polished and planarized over the entire wafer surface, third interconnection layer 17 with high dimensional precision can be formed more easily.
- a semiconductor device will be described with reference to the drawings.
- a comparatively thin silicon oxide film 27 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- SOG film 24 is formed on silicon oxide film 27 .
- BPSG film 21 is formed on SOG film 24 .
- BPSG film 21 is reflowed by heating.
- Silicon oxide film 18 is formed on reflowed BPSG film 21 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- second interconnection layer 12 is formed on silicon oxide film 10 , and comparatively thin silicon oxide film 27 is then formed on silicon oxide film 10 by the CVD method to cover second interconnection layer 12 .
- SOG film 24 is formed on silicon oxide film 27 . Thereafter, steps similar to the steps shown in FIG. 21 described in the fourth embodiment are performed to complete the semiconductor device shown in FIG. 27.
- Silicon oxide film 27 is formed to cover second interconnection layer 12 .
- diffusion of an impurity such as hydrogen contained in SOG film 24 to second interconnection layer 12 and the like can be prevented.
- silicon oxide film 27 is applied, as a film for protecting second interconnection layer 12 , to the semiconductor device shown in FIG. 19 in this embodiment, the similar effects can be attained even if the film is applied to the semiconductor devices shown in FIGS. 22 and 25.
- a semiconductor device will be described with reference to the drawings.
- a BPSG film 28 is formed on silicon oxide film 8 .
- BPSG film 28 is reflowed by heating.
- a silicon oxide film 29 is formed on reflowed BPSG film 28 .
- Silicon oxide film 29 is polished by the CMP method.
- Second interconnection layer 12 is formed on silicon oxide film 29 .
- a silicon oxide film 30 is formed on silicon oxide film 29 to cover second interconnection layer 12 .
- BPSG film 14 is formed on silicon oxide film 30 .
- BPSG film 14 is reflowed by heating.
- Silicon oxide film 18 is formed on reflowed BPSG film 14 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- BPSG film 28 having a film thickness of approximately 300 nm is formed on silicon oxide film 8 by the CVD method.
- BPSG film 28 is heated at a temperature of approximately 800° C. to reflow BPSG film 28 .
- Silicon oxide film 29 having a film thickness of approximately 600 nm is formed on reflowed BPSG film 28 by the CVD method.
- silicon oxide film 29 is polished by the CMP method.
- the surface of silicon oxide film 29 is planarized over the entire wafer surface.
- second interconnection layer 12 is formed on silicon oxide film 29 .
- Silicon oxide film 30 is formed on silicon oxide film 29 to cover second interconnection layer 12 .
- Silicon oxide film 30 has a thickness of at least the substantial thickness of second interconnection layer 12 .
- BPSG film 14 is formed on silicon oxide film 30 by the CVD method.
- BPSG film 14 is heated to reflow BPSG film 14 .
- Silicon oxide film 18 is formed on reflowed BPSG film 14 by the CVD method.
- contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a , 15 b , 15 d , 15 d and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 29.
- BPSG film 28 is fixed by silicon oxide film 29 . Since silicon oxide film 29 is polished, silicon oxide film 29 is planarized over the entire wafer surface. Further, second interconnection layer 12 is fixed strongly on silicon oxide film 29 by silicon oxide film 30 . Thus, even if BPSG film 28 is transformed when BPSG film 14 is reflowed by heating, displacement of second interconnection layer 12 can be suppressed more effectively.
- silicon oxide film 29 is formed on reflowed BPSG film 28 , the roughness of the surface is eased. Thus, variation in the degree of polishing silicon oxide film 29 can be reduced.
- BPSG film 28 is formed on silicon oxide film 8 .
- BPSG film 28 is reflowed by heating.
- Silicon oxide film 10 is formed on reflowed BPSG film 28 .
- Second interconnection layer 12 is formed on silicon oxide film 10 .
- Silicon oxide film 20 is formed on silicon oxide film 10 to cover second interconnection layer 12 .
- BPSG film 14 is formed on silicon oxide film 20 .
- BPSG film 14 is reflowed by heating.
- Silicon oxide film 18 is formed on reflowed BPSG film 14 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG.
- the same elements have the same reference characters and their description will not be repeated.
- the semiconductor device according to this embodiment is similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment without polishing by the CMP method for BPSG film 9 .
- BPSG film 28 having a film thickness of approximately 600 nm is formed on silicon oxide film 8 by the CVD method.
- BPSG film 28 is heated at a temperature of 800° C. to reflow BPSG film 28 .
- silicon oxide film 10 having a film thickness of 100 nm is formed on reflowed BPSG film 28 by the CVD method.
- Second interconnection layer 12 is formed on silicon oxide film 10 .
- Silicon oxide film 20 is formed on silicon oxide film 10 by the CVD method to cover second interconnection layer 12 .
- Silicon oxide film 20 has a thickness of at least the substantial thickness of second interconnection layer 12 .
- BPSG film 14 having a film thickness of approximately 1000 nm is formed on silicon oxide film 20 by the CVD method.
- BPSG film 14 is heated to reflow BPSG film 14 .
- the planarity of BPSG film 14 may be improved by etching reflowed BPSG film 14 by the RIE method or a hydrofluoric acid solution. The planarity may also be ensured by polishing reflowed BPSG film 14 by the CMP method.
- silicon oxide film 18 is formed on BPSG film 14 by the CVD method.
- Contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Contact holes 15 a , 15 b , 15 c , 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 33.
- Second interconnection layer 12 is fixed strongly on silicon oxide film 10 by silicon oxide film 20 .
- BPSG film 28 is transformed by the heating for reflowing BPSG film 14 , displacement of second interconnection layer 12 can be suppressed.
- a semiconductor device according to a tenth embodiment will be described with reference to the drawings.
- a PSG film 33 is formed on silicon oxide film 8 .
- a silicon oxide film 34 is formed on PSG film 33 .
- Silicon oxide film 34 is polished by the CMP method.
- Second interconnection layer 12 is formed on silicon oxide film 34 .
- Silicon oxide film 30 is formed on silicon oxide film 34 to cover second interconnection layer 12 .
- Silicon oxide film 30 has a thickness of at least the substantial thickness of second interconnection layer 12 .
- BPSG film 21 is formed on silicon oxide film 30 .
- BPSG film 21 is reflowed by heating.
- Silicon oxide film 18 is formed on BPSG film 21 .
- Third interconnection layer 17 is formed on silicon oxide film 18 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- a method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings.
- steps before formation of silicon oxide film 8 are similar to the steps shown in FIG. 2 described in the first embodiment.
- PSG film 33 having a film thickness of approximately 600 nm is formed on silicon oxide film 8 by the CVD method.
- a comparatively thick silicon oxide film (not shown) is formed on PSG film 33 .
- the silicon oxide film is polished by the CMP method.
- silicon oxide film 34 is planarized over the entire wafer surface.
- second interconnection layer 12 is formed on silicon oxide film 34 .
- Silicon oxide film 30 is formed on silicon oxide film 34 by the CVD method to cover second interconnection layer 12 .
- BPSG film 21 is formed on silicon oxide film 30 by the CVD method.
- BPSG film 21 is heated at a temperature of approximately 800° C. to reflow BPSG film 21 .
- reflowed BPSG film 21 may be further planarized, if necessary, by etching BPSG film 21 by the RIE method or a hydrofluoric acid solution.
- the reflowed BPSG film 21 may also be polished by the CMP method.
- Silicon oxide film 18 having a film thickness of approximately 100 nm is formed on BPSG film 21 by the CVD method.
- contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods.
- Contact holes 15 a , 15 b , 15 c , 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 37.
- a semiconductor device according to an eleventh embodiment will be described with reference to the drawings.
- an SOG film 35 is formed on silicon oxide film 8 .
- a silicon oxide film 36 is formed on SOG film 35 .
- Silicon oxide film 36 is polished by the CMP method. Since other parts are similar to the semiconductor device shown in FIG. 37 described in the tenth embodiment, the same elements have the same reference characters and their description will not be repeated.
- a method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings.
- steps before formation of silicon oxide film 8 are similar to the steps shown in FIG. 2 described in the first embodiment.
- SOG film 35 having a film thickness of approximately 600 nm is formed on silicon oxide film 8 .
- a comparatively thick silicon oxide film (not shown) is formed on SOG film 35 by the CVD method.
- the silicon oxide film is polished by the CMP method to form silicon oxide film 36 .
- silicon oxide film 36 is planarized over the entire wafer surface.
- second interconnection layer 12 is formed on silicon oxide film 36 .
- Silicon oxide film 30 is formed on silicon oxide film 36 to cover second interconnection layer 12 .
- BPSG film 21 is formed on silicon oxide film 30 by the CVD method.
- BPSG film 21 is heated to reflow BPSG film 21 .
- Silicon oxide film 18 is formed on reflowed BPSG film 21 by the CVD method.
- Contact holes 15 a , 15 b , 15 c , 15 d are formed by the prescribed photolithography and RIE methods. Contact holes 15 a , 15 b , 15 c , 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed on silicon oxide film 18 to complete the semiconductor device shown in FIG. 40.
- second interconnection layer 12 silicon oxide film 36 , SOG film 35 and the like are formed and a BPSG film is not formed. Even if BPSG film 21 is heated to be reflowed, therefore, silicon oxide film 36 , SOG film 35 and the like are not transformed. Thus, displacement of second interconnection layer 12 can easily be prevented.
- silicon oxide film 36 is formed on SOG film 35 . Therefore, the roughness of surface of the silicon oxide film 36 before it is polished is eased. Thus, variation in the degree of polishing in polishing silicon oxide film 36 can be reduced.
- a semiconductor device will be described with reference to the drawings.
- a silicon oxide film 37 is formed on the surface of silicon semiconductor substrate 1 and on the both side surfaces of gate electrode potion 5 .
- Sidewall insulating film 7 is formed on silicon oxide film 37 that is formed on the both side surfaces of gate electrode portion 5 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- gate electrode portion 5 and impurity diffusion layers 6 a , 6 b , 6 c , 6 d are formed on and in silicon semiconductor substrate 1 in a similar manner to the steps shown in FIG. 2 described in the first embodiment.
- silicon oxide film 37 is formed on the both side surfaces of gate electrode portion 5 and on impurity diffusion layers 6 a , 6 b , 6 c , Gd by the thermal oxidation method.
- a silicon oxide film (not shown) having a film thickness of 10 to 50 nm is formed on silicon oxide film 37 by the CVD method.
- the silicon oxide film is etched by the RIE method to form sidewall insulating film 7 .
- the steps shown in FIGS. 2 to 8 described in the first embodiment are performed to complete the semiconductor device shown in FIG. 43.
- the contact holes may be formed by the self align contact method so as not to etch gate electrode portion 5 .
- a laminate structure of a silicon oxide film and a silicon nitride film is applied as an insulating film formed on the both side surfaces of gate electrode portion 5 .
- the contact hole by the self align contact method can be formed by applying silicon oxide film 37 as the silicon oxide film and applying a silicon nitride film to sidewall insulating film 7 .
- a corresponding configuration of the semiconductor devices in the above described embodiments may be applied to the configuration above gate electrode portion 5 as a variation of the semiconductor device according to this embodiment.
- a semiconductor device will be described with reference to the drawings.
- a silicon oxide film 38 is formed on impurity diffusion layers 6 a , 6 b , 6 c , 6 d that are formed at silicon semiconductor substrate 1 .
- BPSG film 9 is formed on silicon oxide film 38 and gate electrode portion 5 . Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated.
- gate electrode portion 5 , sidewall insulating film 7 and impurity diffusion layers 6 a , 6 b , 6 c , 6 d are formed on and in silicon semiconductor substrate 1 in a similar manner to the steps shown in FIG. 2 described in the first embodiment.
- silicon oxide film 38 is formed on impurity diffusion layers 6 a , 6 b , 6 c , 6 d by the thermal oxidation method.
- steps similar to the steps shown in FIGS. 2 to 8 described in the first embodiment are performed to complete the semiconductor device shown in FIG. 45.
- a corresponding configuration of the semiconductor devices in the above described embodiments may be applied to the configuration above gate electrode portion 5 as a variation of the semiconductor device according to this embodiment.
- the method of forming the separating oxide films, the silicon oxide films, the silicon nitride films, the interconnection layers, the plugs and the like described in the embodiments above is one example, and they may be formed by other suitable methods.
- a polycrystalline silicon film and tungsten are exemplified as a material of the plugs, aluminum or copper may also be applied.
- the BPSG film is applied as a film for reflowing and planarizing a surface by heating, a silicon oxide film containing at least one species of impurities such as phosphorous, boron and arsenic can also be applied.
- the impurities are not limited to the ones mentioned above. Any impurities can be used if it lowers the temperature at which a silicon oxide film softens.
Abstract
On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and more specifically to a semiconductor device ensuring the planarity of an interlayer insulating film and preventing displacement of an interconnection thereby achieving a high degree of integration.
- 2. Description of the Background Art
- As one example of conventional semiconductor devices, a semiconductor device including an MOS transistor will be described with reference to the drawings. Referring to FIG. 47, a plurality of
gate electrode portions 55 including apolycrystalline silicon film 55 a, atungsten silicide film 55 b and asilicon oxide film 55 c are formed on the surface of asilicon semiconductor substrate 51 with agate insulating film 54 interposed therebetween. A pair ofimpurity diffusion layers silicon semiconductor substrate 51 with onegate electrode portion 55 sandwiched therebetween. A pair ofimpurity diffusion layers silicon semiconductor substrate 51 with anothergate electrode portion 55 sandwiched therebetween. Asidewall insulating film 57 is formed on the both side surfaces ofgate electrode portion 55.Gate electrode portion 55 and a pair ofimpurity diffusion layers gate electrode portion 55 and a pair ofimpurity diffusion layers Gate electrode portion 55 of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separatingoxide film 53 that is formed in anelement separating trench 52 at the surface ofsilicon semiconductor substrate 51. - A
silicon oxide film 58 is formed onsilicon semiconductor substrate 51 to covergate electrode portion 55. Onsilicon oxide film 58, a silicon oxide film doped with boron and phosphorous, that is, a BPSG (Boro-Phospho-Silicate-Glass)film 59 is formed. Asilicon oxide film 60 is formed on BPSGfilm 59. A plurality ofsecond interconnection layers 62 including apolycrystalline silicon film 62 a, atungsten silicide film 62 b and asilicon oxide film 62 c are formed onsilicon oxide film 60. Onesecond interconnection layer 62 is electrically connected togate electrode portion 55 as a first interconnection layer by a polycrystalline silicon film filled incontact hole 61 a that is formed inBPSG film 59 andsilicon oxide films second interconnection layer 62 is electrically connected toimpurity diffusion layer 56 b by a polycrystalline silicon film filled in acontact hole 61 b that is formed inBPSG film 59 andsilicon oxide films silicon oxide film 63 is formed onsilicon oxide film 60 to coversecond interconnection layer 62. A BPSGfilm 64 is also formed onsilicon oxide film 63. A plurality ofthird interconnection layers 67 are formed onBPSG film 64. -
Third interconnection layers 67 are electrically connected togate electrode portion 55 andimpurity diffusion layers plugs contact holes BPSG films silicon oxide films Third interconnection layer 67 is also electrically connected tosecond interconnection layer 62 by aplug 66 d filled in acontact hole 65 d that is formed inBPSG film 64 andsilicon oxide film 63. The conventional semiconductor device has such a configuration. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 48,
element separating trench 52 is formed at the surface ofsilicon semiconductor substrate 51 by prescribed photolithography and RIE (Reactive Ion Etching) methods. To fillelement separating trench 52, a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is then formed onsilicon semiconductor substrate 51 by the CVD method. The silicon oxide film is polished by the CMP (Chemical Mechanical Polishing) method to form separatingoxide film 53 inelement separating trench 52.Gate oxide film 54 having a film thickness of 5 to 15 nm is then formed on the surface ofsilicon semiconductor substrate 51 by the thermal oxidation method. Ongate oxide film 54, a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed. A plurality ofgate electrode portions 55 as the first interconnection layers includingpolycrystalline silicon film 55 a,tungsten silicide film 55 b andsilicon oxide film 55 c are formed by the prescribed photolithography and RIE methods. By implanting an impurity of a prescribed conductive type intosilicon semiconductor substrate 51 usinggate electrode portion 55 as a mask, a region (not shown) of a comparatively low impurity concentration is formed. - To cover
gate electrode portion 55, a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is then formed onsilicon semiconductor substrate 51 by the CVD method. The silicon oxide film is etched by the RIE method to formsidewall insulating film 57 on the both side surfaces ofgate electrode portion 55. By implanting an impurity of a prescribed conductive type intosilicon semiconductor substrate 51 usingsidewall insulating film 57 andgate electrode portion 55 as a mask, a region (not shown) of a comparatively high impurity concentration is formed. Thus, a pair ofimpurity diffusion layers impurity diffusion layers silicon semiconductor substrate 51 withgate electrode potions 55 sandwiched therebetween. Thereafter, comparatively thinsilicon oxide film 58 is formed onsilicon semiconductor substrate 51 by the CVD method to covergate electrode portion 55. BPSGfilm 59 is formed onsilicon oxide film 58 by the CVD method. - Referring to FIG. 49, BPSG
film 59 is heated at a temperature of approximately 850° C. to locally planarize the surface ofBPSG film 59. In other words, BPSGfilm 59 is reflowed. Locallyplanarizeed BPSG film 59 is etched by the RIE method or a hydrofluoric acid solution to makeBPSG film 59 thinner. - Referring to FIG. 50, comparatively thin
silicon oxide film 60 is formed onBPSG film 59 by the CVD method. Then,contact hole 61 a exposing the surface oftungsten silicide film 55 b ofgate electrode portion 55 andcontact hole 61 b exposing the surface ofimpurity diffusion layer 56 b are formed inBPSG film 59 andsilicon oxide films silicon oxide film 60 by the CVD method.Second interconnection layer 62 includingpolycrystalline silicon film 62 a,tungsten silicide film 62 b andsilicon oxide film 62 c is then formed by the prescribed photolithography and RIE methods. - Referring to FIG. 51, comparatively thin
silicon oxide film 63 is formed onsilicon oxide film 60 by the CVD method to coversecond interconnection layer 62. BPSGfilm 64 is then formed onsilicon oxide film 63 by the CVD method. - Referring to FIG. 52, BPSG
film 64 is heated at a temperature of approximately 800° C. to locally planarize the surface ofBPSG film 64. Thereafter, BPSGfilm 64 is etched by the RIE method or a hydrofluoric acid solution , if necessary, to further planarize the surface ofBPSG film 64. - Referring to FIG. 53,
contact hole 65 a exposing the surface oftungsten silicide film 55 b ofgate electrode portion 55,contact holes impurity diffusion layers contact hole 65 d exposing the surface oftungsten silicide film 62 b ofsecond interconnection layer 62 are formed inBPSG film 64 by the prescribed photolithography and RIE methods. Thereafter, an impurity of a prescribed conductive type is implanted incontact holes BPSG film 64. - Then, a tungsten thin film (not shown) is formed on
BPSG film 64 by the CVD method using WF6, for example, as a material. The tungsten thin film is etched by the RIE method to form tungsten plugs (not shown) incontact holes BPSG film 64 by the sputtering method. Then, the third interconnection layers electrically connected togate electrode portion 55,impurity diffusion layers - As LSIs miniaturize in recent, years, processing of
contact holes second interconnection layer 62 andthird interconnection layer 67 with high dimensional precision is becoming difficult. Especially, in order to ensure prescribed dimensional precision in a lateral direction, the NA value (Numerical Aperture) of a lens used for an exposing device is set at a higher value to improve resolution in photolithography. When the planarity of a film surface to be applied with a resist is poor, however, halation makes it difficult to form a pattern that is highly dimensionally precise. Since the NA value of a lens is set at a higher value, it is difficult to ensure the depth of focus. In filling polycrystalline silicon, tungsten or the like incontact holes BPSG films BPSG films BPSG film 59 serving as the base ofsecond interconnection layer 62 andBPSG film 64 serving as the base ofthird interconnection layer 67. - Here, the step portions of the BPSG films are locally planarized by heating. The degree of planarization depends on the concentration of boron and phosphorous contained in the BPSG films, the heating temperature and the like, and the BPSG films are locally planarized to a greater extent as the concentration of boron and phosphorous is higher or as the temperature is higher.
- When the concentration of boron and phosphorous in lower
layer BPSG film 59 is made almost the same as the concentration of boron and phosphorous in upperlayer BPSG film 64 so as to ensure the planarity of the base ofsecond interconnection layer 62, lowerlayer BPSG film 59 is also reflowed and transformed in heating upperlayer BPSG film 64. Therefore,second interconnection layer 62 formed onBPSG film 59 might be displaced asBPSG film 59 is transformed. Thus,second interconnection layer 62, for example, might come into contact withtungsten plug 66 b, causing an electrical short. - In order to suppress such displacement of
second interconnection layer 62, the displacement can be suppressed to approximately 1 μm by setting lower the heating temperature for upperlayer BPSG film 64. In order to cope with the requirement for the heating at a lower temperature as LSIs are miniaturized, however, the lower temperature of the heating for the upper layer BPSG film is approaching a limit. As the LSIs are further miniaturized, suppressing displacement ofsecond interconnection layer 62 to approximately 0.1 μm is required. Therefore, simultaneously ensuring the planarity of the base of the second interconnection layer and the like and preventing displacement of the second interconnection layer are expected to be extremely difficult in the conventional semiconductor device. As a result, easy miniaturization of LSIs is expected to be difficult. - The present invention aims at solving the expected problems above and its object is to provide a semiconductor device ensuring the planarity of the base of each interconnection layer and suppressing displacement of the interconnection layer in the process of manufacturing the semiconductor device thereby achieving a high degree of integration.
- A semiconductor device in one aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and a second interlayer insulating film. The semiconductor substrate has a main surface. The first interconnection layer is formed on the semiconductor substrate. The first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer. The second interconnection layer is formed on the first interlayer insulating film. The second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer. The first interlayer insulating film has a polished top surface, or a film having a polished top surface is laminated on the first interlayer insulating film.
- Since the first interlayer insulating film is polished according to the configuration, the surface of the first interlayer insulating film is planarized over the entire wafer surface in the manufacturing process. Thus, the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film. When the second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer, heat from the process is applied to the first interlayer insulating film. Since the surface of the first interlayer insulating film is planarized over the entire wafer surface at this time, transformation of the first interlayer insulating film is suppressed compared with the case in which the surface is rough. Thus, displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the first interlayer insulating film as its base can be suppressed. As a result, a semiconductor device having a higher degree of integration can be obtained.
- Preferably, the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed, and the reflowed impurity-doped insulating film has the polished top surface.
- In this case, polishing is provided for the impurity-doped insulating film of which roughness of the surface is locally eased by reflow. Therefore, compared with a film of which roughness of the surface is not eased, variation in the degree of polishing in a wafer surface, and variation in the film thickness of the impurity-doped insulating film in the wafer surface can be reduced in polishing the impurity-doped insulating film.
- Preferably, the first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed and an impurity-non-doped insulating film that is formed on the reflowed impurity-doped insulating film and does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
- In this case, the impurity-doped insulating film is covered by the impurity-non-doped insulating film. Even if the impurity-doped insulating film is reflowed and transformed by heat in forming the second interlayer insulating film, therefore, the transformation is suppressed. As a result, displacement of the second interconnection layer can be further suppressed.
- Preferably, the first interlayer insulating film includes an impurity-non-doped insulating film that does not contain prescribed impurities, and the impurity-non-doped insulating film has the polished top surface.
- In this case, the impurity-non-doped insulating film does not contain the prescribed impurities. Therefore, the impurity-non-doped insulating film is not reflowed and transformed by heat in forming the second interlayer insulating film. Thus, the second interconnection layer is not displaced.
- More preferably, the first interlayer insulating film includes a first dipped insulating film formed on the semiconductor substrate by the Spin-On-Glass method to fill a space between the first interconnection layers, and the impurity-non-doped insulating film is formed on the first dipped insulating films.
- In this case, the first dipped insulating film eases the roughness of the surface of the impurity-non-doped insulating film before it is polished. Thus, variation in the degree of polishing in the wafer surface can be reduced in polishing the impurity-non-doped insulating film.
- Preferably, the second interlayer insulating film includes an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
- In this case, the second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film. Thus, even if the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can further be suppressed.
- Preferably, the second interlayer insulating film includes a second dipped insulating film formed on the first interlayer insulating film by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
- In this case, the second interconnection layer is fixed more strongly on the first interlayer insulating film by the second dipped insulating film. Thus, even if the first interlayer insulating film is transformed by heat in a subsequent manufacturing process, displacement of the second interconnection layer can be suppressed effectively. The roughness of the wafer surface can also be eased by the second dipped insulating film. Thus, the planarity of a film formed on the second dipped insulating film can be ensured easily.
- More preferably, the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the second dipped insulating film.
- In this case, diffusion of an impurity such as hydrogen contained in the second dipped insulating film to the second interconnection layer can be prevented.
- A semiconductor device in another aspect of the present invention includes a semiconductor substrate, a first interconnection layer, a first interlayer insulating film, a second interconnection layer, and second interlayer insulating film. The semiconductor substrate has a main surface. The first interconnection layer is formed on the semiconductor substrate. The first interlayer insulating film is formed on the semiconductor substrate to cover the first interconnection layer. The second interconnection layer is formed on the first interlayer insulating film. The second interlayer insulating film is formed on the first interlayer insulating film to cover the second interconnection layer. The first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed. The second interlayer insulating film has an interconnection coating insulating film that has a thickness allowing fixing and holding of the second interconnection layer and covers the second interconnection layer.
- According to the configuration, the surface of the first interlayer insulating film is locally planarized by the impurity-doped insulating film in the manufacturing process. Thus, the second interconnection layer that is highly dimensionally precise can easily be formed on the first interlayer insulating film. The second interconnection layer is fixed more strongly on the first interlayer insulating film by the interconnection coating insulating film. Thus, even if the impurity-doped insulating film is reflowed and transformed by heat in a sequent manufacturing process, displacement of the second interconnection layer causing the second interconnection layer to be moved due to the transformation of the impurity-doped insulating film can be suppressed. As a result, a semiconductor device having a higher degree of integration can be obtained.
- Preferably, the interconnection coating insulating film has a thickness of at least the thickness of the second interconnection layer.
- In this case, the second interconnection layer is fixed more reliably on the first interlayer insulating film by the interconnection coating insulating film. Thus, displacement of the second interconnection layer can be suppressed more reliably.
- Preferably, the second interlayer insulating film is polished or reflowed.
- In this case, a pattern that is highly dimensionally precise can easily be formed on the second interlayer insulating film.
- Preferably, the interconnection coating insulating film includes a third dipped insulating film formed by the Spin-On-Glass method to fill a space between the second interconnection layers or to cover the second interconnection layers.
- In this case, the roughness of the wafer surface is eased by the third dipped insulating film, and thereafter the planarity of a film formed on the third dipped insulating film can easily be ensured.
- More preferably, the second interlayer insulating film includes an interconnection protecting film formed between the second interconnection layer and the third dipped insulating film.
- In this case, diffusion of an impurity such as hydrogen contained in the third dipped insulating film to the second interconnection layer can be prevented.
- More preferably, an insulating film that does not contain prescribed impurities is formed on the top surface or the bottom surface of the impurity-doped insulating film.
- In this case, diffusion of the prescribed impurities contained in the impurity-doped insulating film upward or downward of the impurity-doped insulating film can be prevented by the insulating film.
- More preferably, the first interlayer insulating film includes a substrate coating insulating film covering the semiconductor substrate.
- In this case, diffusion of prescribed impurities contained in the impurity-doped insulating film to the semiconductor substrate can be prevented by the substrate coating insulating film.
- At least one species of impurities selected from the group of boron, phosphorous and arsenic can be applied as the prescribed impurities.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- FIG. 1 is a cross sectional view showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 1 in the first embodiment.
- FIGS.3 to 8 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 2 to 7 in the first embodiment.
- FIGS. 9 and 10 are cross sectional views showing first and second variations of the semiconductor device in the first embodiment.
- FIG. 11 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 10 in the first embodiment.
- FIG. 12 is a cross sectional view showing a step performed after the step shown in FIG. 11 in the first embodiment.
- FIG. 13 is a cross sectional view showing a semiconductor device according to a second embodiment of the present invention.
- FIG. 14 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 13 in the second embodiment.
- FIG. 15 is a cross sectional view showing a step performed after the step shown in FIG. 14 in the second embodiment.
- FIG. 16 is a cross sectional view showing a semiconductor device according to a third embodiment of the present invention.
- FIG. 17 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 16 in the third embodiment.
- FIG. 18 is a cross sectional view showing a step performed after the step shown in FIG. 17 in the third embodiment.
- FIG. 19 is a cross sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 20 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 19 in the fourth embodiment.
- FIG. 21 is a cross sectional view showing a step performed after the step shown in FIG. 20 in the fourth embodiment.
- FIG. 22 is a cross sectional view showing a semiconductor device according to a fifth embodiment of the present invention.
- FIG. 23 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 22 in the fifth embodiment.
- FIG. 24 is a cross sectional view showing a step performed after the step shown in FIG. 23 in the fifth embodiment.
- FIG. 25 is a cross sectional view showing a semiconductor device according to a sixth embodiment of the present invention.
- FIG. 26 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 25 in the sixth embodiment.
- FIG. 27 is a cross sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
- FIG. 28 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 27 in the seventh embodiment.
- FIG. 29 is a cross sectional view showing a semiconductor device according to an eighth embodiment of the present invention.
- FIG. 30 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 29 in the eighth embodiment.
- FIGS. 31 and 32 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 30 and 31 in the eighth embodiment.
- FIG. 33 is a cross sectional view showing a semiconductor device according to a ninth embodiment of the present invention.
- FIG. 34 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 33 in the ninth embodiment.
- FIGS. 35 and 36 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 34 and 35 in the ninth embodiment.
- FIG. 37 is a cross sectional view showing a semiconductor device according to a tenth embodiment of the present invention.
- FIG. 38 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 37 in the tenth embodiment.
- FIG. 39 is a cross sectional view showing a step performed after the step shown in FIG. 38 in the tenth embodiment.
- FIG. 40 is a cross sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.
- FIG. 41 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 40 in the eleventh embodiment.
- FIG. 42 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 41 in the eleventh embodiment.
- FIG. 43 is a cross sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.
- FIG. 44 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 43 in the twelfth embodiment.
- FIG. 45 is a cross sectional view showing a semiconductor device according to a thirteenth embodiment of the present invention.
- FIG. 46 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 45 in the thirteenth embodiment.
- FIG. 47 is a cross sectional view showing a conventional semiconductor device.
- FIG. 48 is a cross sectional view showing one step of the method of manufacturing the semiconductor device shown in FIG. 47.
- FIGS.49 to 53 are cross sectional views respectively showing steps performed after the steps shown in FIGS. 48 to 52.
- First Embodiment
- A semiconductor device according to a first embodiment will be described with reference to the drawings. Referring to FIG. 1, a plurality of
gate electrode portions 5 including apolycrystalline silicon film 5 a, atungsten silicide film 5 b and asilicon oxide film 5 c are formed on the surface of asilicon semiconductor substrate 1 with agate insulating film 4 interposed therebetween. A pair of impurity diffusion layers 6 a, 6 b are formed at the surface ofsilicon semiconductor substrate 1 with onegate electrode portion 5 sandwiched therebetween. A pair of impurity diffusion layers 6 c, 6 d are formed at the surface ofsilicon semiconductor substrate 1 with anothergate electrode portion 5 sandwiched therebetween. Asidewall insulating film 7 is formed on the both side surfaces ofgate electrode portion 5.Gate electrode portion 5 and a pair of impurity diffusion layers 6 a, 6 b constitute one MOS transistor.Gate electrode portion 5 and a pair of impurity diffusion layers 6 c, 6 d constitute another MOS transistor.Gate electrode portion 5 of each MOS transistor serves as a first interconnection layer. MOS transistors are electrically insulated from one another by a separatingoxide film 3 that is formed in anelement separating trench 2 at the surface ofsilicon semiconductor substrate 1. - A
silicon oxide film 8 is formed onsilicon semiconductor substrate 1 to covergate electrode portion 5. ABPSG film 9 is formed onsilicon oxide film 8. AfterBPSG film 9 is reflowed by heating, its surface is polished. Asilicon oxide film 10 is formed onpolished BPSG film 9. Onsilicon oxide film 10, a plurality of second interconnection layers 12 including apolycrystalline silicon film 12 a, atungsten silicide film 12 b and asilicon oxide film 12 c are formed. Onesecond interconnection layer 12 is electrically connected togate electrode portion 5 as the first interconnection layer by a polycrystalline silicon film filled in acontact hole 11 a that is formed inBPSG film 9 andsilicon oxide films second interconnection layer 12 is electrically connected toimpurity diffusion layer 6 b by a polycrystalline silicon film filled in acontact hole 11 b that is formed inBPSG film 9 andsilicon oxide films - A
silicon oxide film 13 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.Silicon oxide film 13 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness ofpolycrystalline silicon film 12 a+ thickness oftungsten silicide film 12 b) as the thickness allowing fixing and holding ofsecond interconnection layer 12 onsilicon oxide film 10. ABPSG film 14 is also formed on thesilicon oxide film 13.BPSG film 14 is reflowd by heating and its surface is planarized. A plurality of third interconnection layers 17 including an aluminum copper alloy film are formed onBPSG film 14. Third interconnection layers 17 are electrically connected togate electrode portion 5 and impurity diffusion layers 6 c, 6 d byplugs BPSG films silicon oxide films Third interconnection layer 17 is electrically connected tosecond interconnection layer 12 by aplug 16 d filled in acontact hole 15 d that is formed inBPSG film 14 andsilicon oxide film 13. The semiconductor device according to the embodiment has such a configuration. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring first to FIG. 2, an
element separating trench 2 is formed at the surface ofsilicon semiconductor substrate 1 by prescribed photolithography and RIE methods. To fillelement separating trench 2, a silicon oxide film (not shown) having a film thickness of approximately 300 to 800 nm is formed onsilicon semiconductor substrate 1 by the CVD method. The silicon film is polished by the CMP method to form a separatingoxide film 3 inelement separating trench 2. Then,gate oxide film 4 having a film thickness of 5 to 15 nm is formed on the surface ofsilicon semiconductor substrate 1 by the thermal oxidation method. Ongate oxide film 4, a polycrystalline silicon film containing phosphorous or arsenic, a tungsten silicide film and a silicon oxide film (they are not shown) are formed. A plurality ofgate electrode portions 5 as the first interconnection layers includingpolycrystalline silicon film 5 a,tungsten silicide film 5 b andsilicon oxide film 5 c are formed by the prescribed photolithography and RIE methods. - By implanting an impurity of a prescribed conductive type into
silicon semiconductor substrate 1 usinggate electrode portion 5 as a mask, a region (not shown) of a comparatively low impurity concentration is formed. To covergate electrode portion 5, a silicon oxide film (not shown) having a film thickness of approximately 10 to 50 nm is formed onsilicon semiconductor substrate 1 by the CVD method. The silicon oxide film is etched by the RIE method to form sidewall insulatingfilm 7 on the both side surfaces ofgate electrode portion 5. By implanting an impurity of a prescribed conductive type intosilicon semiconductor substrate 1 usingsidewall insulating film 7 andgate electrode portion 5 as a mask, a region (not shown) of a comparatively high impurity concentration is formed. Thus, a pair of impurity diffusion layers 6 a, 6 b and a pair of impurity diffusion layers 6 c, 6 d are formed at the surface ofsilicon semiconductor substrate 1 withgate electrode portions 5 interposed therebetween. To covergate electrode portion 5 and the like,silicon oxide film 8 having a film thickness of approximately 10 nm is then formed onsilicon semiconductor substrate 1 by the CVD method.BPSG film 9 is formed onsilicon oxide film 8 by the CVD method. - Referring to FIG. 3,
BPSG film 9 is heated at a temperature of approximately 800° C. to locally planarize the surface ofBPSG film 9. In other words,BPSG film 9 is reflowed. While the local roughness of the wafer surface is eased at this time, a, step cannot be eased by the BPSG film and an “absolute step” is caused at a boarder portion, for example, between a memory cell region in which MOS transistors are integrated and a region like a periphery region in which elements such as transistors are not so integrated as in the memory cell region. Referring to FIG. 4, locally planarizedBPSG film 9 is polished by approximately 150 nm by the CMP method. This polishing removes the absolute step inBPSG film 9, and the surface ofBPSG film 9 is planarized over the entire wafer surface. - Referring to FIG. 5,
silicon oxide film 10 having a film thickness of approximately 100 nm is formed onpolished BPSG film 9 by the CVD method. Then, contacthole 11 a exposing the surface oftungsten silicide film 5 b ofgate electrode portion 5 andcontact hole 11 b exposing the surface ofimpurity diffusion layer 6 b are formed by the prescribed photolithography and RIE methods. To fillcontact holes 1 a and 11 b, a polycrystalline silicon film (not shown) is formed onsilicon oxide film 10. Then, a tungsten silicide film and a silicon oxide film (they are not shown) are formed by the CVD method. Thereafter, a plurality of second interconnection layers 12 includingpolycrystalline silicon film 12 a,tungsten silicide film 12 b andsilicon oxide film 12 c are formed by the prescribed photolithography and RIE method. It is noted that a polycrystalline silicon plugs are formed in contact holes 11 a and 11 b at this time. To coversecond interconnection layer 12,silicon oxide film 13 is then formed onsilicon oxide film 10 by the CVD method.silicon oxide film 13 has a thickness of at least the substantial thickness of the second interconnection layer (thickness ofpolycrystalline silicon film 12 a+ thickness oftungsten silicide film 12 b) as the thickness allowing fixing and holding ofsecond interconnection layer 12 onsilicon oxide film 10. - Referring to FIG. 6,
BPSG film 14 is formed onsilicon oxide film 13 by the CVD method.BPSG film 14 is heated at a temperature of approximately 800° C. to reflow and locally planarize the surface. As shown in FIG. 7, the reflowed surface ofBPSG film 14 may be etched and made thinner by the RIE method or a hydrofluoric acid solution, if necessary, so as to make a smoother surface. The reflowed surface ofBPSG film 14 may also be polished by the CMP method. - Referring to FIG. 8,
contact hole 15 a exposing the surface oftungsten silicide film 5 b ofgate electrode portion 5,contact hole 15 b exposing the surface ofimpurity diffusion layer 6 c,contact hole 15 c exposing the surface ofimpurity diffusion layer 6 d, and contact hold 15 d exposing the surface oftungsten silicide film 12 b ofsecond interconnection layer 12 are formed by the prescribed photolithography and RIE methods. Then, an impurity of a prescribed conductive type is implanted into contact holes 15 a, 15 b, 15 c, 15 d, and prescribed heating is performed to activate the impurity. Desirably, the heating temperature at this time is lower than the heating temperature for reflowingBPSG film 14. Then, tungsten plugs are formed in contact holes 15 a, 15 b, 15 c, 15 d by the CVD method using WF6 or the like as a material. An aluminum copper alloy film is formed onBPSG film 14 by the sputtering method. Thereafter, the third interconnection layer is formed by the prescribed photolithography and RIE methods. The semiconductor device shown in FIG. 1 is completed in this matter. - According to the above described semiconductor device,
BPSG film 9 is polished in the step shown in FIG. 4. Thus, the BPSG film is planarized over the entire wafer surface. SinceBPSG film 9 is planarized, halation or the like is suppressed in patterningsecond interconnection layer 12 in the step shown in FIG. 5, andsecond interconnection layer 12 with high dimensional precision is formed. - In the step shown in FIG. 6,
BPSG film 14 is heated and reflowed. At this time,BPSG film 9 is also about to reflow due to the heating. SinceBPSG film 9 is planarized over the entire wafer surface, however, transformation due to reflowing ofBPSG film 9 is suppressed compared with the case where the surface of the BPSG film is rough and stepped. Thus, displacement ofsecond interconnection layer 12 causingsecond interconnection layer 12 to be moved due to deformation ofBPSG film 9 can be suppressed. - Moreover,
silicon oxide film 13 formed to coversecond interconnection layer 12 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness ofpolycrystalline silicon film 12 a+ thickness oftungsten silicide film 12 b). Thus,second interconnection layer 12 is fixed more strongly onsilicon oxide film 10 bysilicon oxide film 13, and displacement ofsecond interconnection layer 12 can be further suppressed. As a result, a semiconductor device having a high degree of integration can be obtained. - In addition to this effect, the following effects can be attained in the above described semiconductor device. Since displacement of
second interconnection layer 12 is suppressed, an electrical short caused whensecond interconnection layer 12 electrically comes into contact with plug 10 a is suppressed, for example. Further, since the BPSG film is planarized over the entire wafer surface, occurrence of a residue of a polycrystalline silicon film due to etching can be prevented in filling a polycrystalline silicon film in contact holes 11 a, 11 b that are formed inBPSG film 9,silicon oxide film 10 and the like. - Further, diffusion of boron or phosphorous in
BPSG film 9 togate electrode portion 5 as the first interconnection layer or thesecond interconnection layer 12 and the like can be prevented bysilicon oxide films silicon oxide film 10 formed on the surface ofBPSG film 9 can also prevent formation of particles on the surface whenBPSG film 9 absorbs moisture.Second interconnection layer 12 can be patterned advantageously.Silicon oxide film 10 has the effect of improving adhesion of a resist in patterningsecond interconnection layer 12.Silicon oxide film 13 can prevent diffusion of boron or phosphorous inBPSG film 14 tosecond interconnection layer 12. - In the step shown in FIG. 6,
silicon oxide film 13 can prevent oxidation ofsecond interconnection layer 12 whenBPSG film 14 is heated in the atmosphere of water vapor. - A first variation of the semiconductor device shown in FIG. 1 will be described in the following with reference to the drawing. Referring to FIG. 9, a
silicon oxide film 18 having a film thickness of approximately 100 nm is formed onBPSG film 14. Athird interconnection layer 17 is formed onsilicon oxide film 18 Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1, the same elements have the same reference characters and their description will not be repeated. - According to the semiconductor device, diffusion of boron or phosphorous in
BPSG film 14 tothird interconnection layer 17 can be prevented bysilicon oxide film 18.Silicon oxide film 18 can also prevent formation of particles on the surface ofBPSG film 14 whenBPSG film 14 absorbs moisture. Thus, the reliability ofthird interconnection layer 17 can be prevented from lowering due to the particles.Silicon oxide film 18 also has the effect of improving adhesion of a resist in patterningthird interconnection layer 17. As a film formed onBPSG film 14, a laminate film of a silicon oxynitride film or a silicon nitride film and a silicon oxide film may be employed in addition to a silicon oxide film. In this case,silicon oxide film 18 can also serve as a film for preventing reflection in the lithography for forming contact holes 15 a, 15 b, 15 c. Approximately 40 nm is preferred for a film thickness in this case. - A second variation of the semiconductor device shown in FIG. 1 will be described in the following with reference to the drawing. Referring to FIG. 10, a PSG (Phospho Silicate Glass)
film 20 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.BPSG film 14 is formed onPSG film 20. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the semiconductor device shown in FIG. 10 will be briefly described in the following. Referring to FIG. 11, steps before formation of
second interconnection layer 12 onsilicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5. To coversecond interconnection layer 12,PSG film 20 is formed onsilicon oxide film 10 by the CVD method.PSG film 20 has a thickness of at least the substantial thickness of second interconnection layer 12 (thickness ofpolycrystalline silicon film 12 a+thickness oftungsten silicide film 12 b). - Referring to FIG. 12, steps similar to the steps shown in FIGS.6 to 8 are performed to form contact holes 15 a, 15 b, 15 c, 15 d. Then, tungsten plugs for filling contact holes 15 a, 15 b, 15 c, 15 d are formed and the third interconnection layer such as an aluminum copper alloy film is formed on
silicon oxide film 18 to complete the semiconductor device shown in FIG. 10. - In the above described semiconductor device,
second interconnection layer 12 is covered byPSG film 20. SincePSG film 20 is not softened by heating for reflowingBPSG film 14,second interconnection layer 12 can be fixed more strongly onsilicon oxide film 10. Thus, even ifPSG film 20 is applied in stead ofsilicon oxide film 13 shown in FIG. 1, displacement ofsecond interconnection layer 12 can be suppressed. - Second Embodiment
- A semiconductor device according to a second embodiment will be described with reference to the drawings. Referring to FIG. 13, a comparatively
thick PSG film 22 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.PSG film 22 is polished by the CMP method.Silicon oxide film 18 is formed onPSG film 22.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 14, steps before formation of
second interconnection layer 12 onsilicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment. To coversecond interconnection layer 12, comparativelythick PSG film 22 is then formed onsilicon oxide film 10 by the CVD method. - Referring to FIG. 15,
PSG film 22 is polished by the CMP method to planarizePSG film 22 over the entire wafer surface.Silicon oxide film 18 is formed onpolished PSG film 22 by the CVD method. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Thereafter, tungsten plugs are filled in contact holes 15 a, 15 b, 15 c, 15 d and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 13. - Especially, the following effects are attained in the above described semiconductor device. Since
second interconnection layer 12 is covered by comparativelythick PSG film 22,second interconnection layer 12 can be fixed more strongly onsilicon oxide film 10. As a result, displacement ofsecond interconnection layer 12 can be further suppressed. Since the surface ofPSG film 22 is polished by the CMP method, the surface is planarized over the entire wafer surface. Thus,third interconnection layer 17 with high dimensional precision can easily be formed. As described above, a semiconductor device having a high degree of integration can be obtained. - Third Embodiment
- A semiconductor device according to a third embodiment will be described with reference to the drawings. Referring to FIG. 16,
PSG film 20 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.PSG film 20 has a thickness of at least the substantial thickness ofsecond interconnection layer 12. A comparatively thicksilicon oxide film 23 is formed onPSG film 20.Silicon oxide film 23 is polished by the CMP method.Third interconnection layer 17 is formed onsilicon oxide film 23. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 17, steps before formation of
second interconnection layer 12 onsilicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment. To coversecond interconnection layer 12,PSG film 20 is then formed onsilicon oxide film 10 by the CVD method. Comparatively thicksilicon oxide film 23 is formed onPSG film 20 by the CVD method. - Referring to FIG. 18,
PSG film 23 is polished by the CMP method to planarize the surface ofPSG film 23 over the entire wafer surface. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are formed in contact holes 15 a, 15 b, 15 c, 15 d and the third interconnection layer is formed onsilicon oxide film 23 to complete the semiconductor device shown in FIG. 16. - Especially, the following effects are attained in the above described semiconductor device. Since
second interconnection layer 12 is fixed more strongly onsilicon oxide film 10 byPSG film 20, displacement ofsecond interconnection layer 12 is further suppressed. Further,silicon oxide film 23 can prevent diffusion of phosphorous contained inPSG film 20 tothird interconnection layer 17. Since the surface ofsilicon oxide film 23 is polished by the CMP method, the surface is planarized over the entire wafer surface. Thus,third interconnection layer 17 with higher dimensional precision can easily be formed. - Fourth Embodiment
- A semiconductor device according to a fourth embodiment will be described with reference to the drawings. Referring to FIG. 19, an insulating film (hereinafter referred to as an “SOG film”)24 is formed on
silicon oxide film 10 by a dipping method (Spin-On-Glass method)to fill a space between second interconnection layers 12.BPSG film 21 is formed onSOG film 24.BPSG film 21 is reflowed by heating.Silicon oxide film 18 is formed on reflowedBPSG film 21.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 20, steps before formation of
second interconnection layer 12 onsilicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in thefirst embodiment 1. To fill a space between second interconnection layers 12,SOG film 24 is then formed onsilicon oxide film 10 by the dipping method. - Referring to FIG. 21,
BPSG film 21 is formed onSOG film 24 by the CVD method.BPSG film 21 is heated to reflowBPSG film 21.Silicon oxide film 18 is formed on reflowedBPSG film 21. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed lithography and RIE methods. Tungsten plugs are filled in contact holes 15 a, 15 b, 15 c, 15 d and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 19. - Especially, the following effects are attained in the above described semiconductor device.
Second interconnection layer 12 is fixed more strongly onsilicon oxide film 10 bySOG film 24. Thus, even ifBPSG film 9 is transformed by the heating for reflowingBPSG film 21, displacement ofsecond interconnection layer 12 can be suppressed effectively. Since the roughness of the wafer surface is eased bySOG film 24, the roughness of the surface ofBPSG film 21 formed onSOG film 24 is eased. Accordingly, the surface ofBPSG film 21 after it is reflowed is further planarized. Therefore,third interconnection layer 17 with high dimensional precision can easily be formed. - Fifth Embodiment
- A semiconductor device according to a fifth embodiment will be described with reference to the drawings. Referring to FIG. 22,
SOG film 24 is formed onsilicon oxide film 10 to fill a space between second interconnection layers 12. Asilicon oxide film 25 is formed onSOG film 24.Silicon oxide film 25 is polished by the CMP method.Third interconnection layer 17 is formed onsilicon oxide film 25. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 23, comparatively thick
silicon oxide film 25 is formed onSOG film 24 by the CVD method after the step shown in FIG. 20 described in the fourth embodiment. - Referring to FIG. 24,
silicon oxide film 25 is polished by the CMP method. Thus, the surface ofsilicon oxide film 25 is planarized over the entire wafer surface. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a, 15 b, 15 c, 15 d and the third interconnection layer is formed onsilicon oxide film 25 to complete the semiconductor device shown in FIG. 22. - Especially, the following effects are attained in the above described semiconductor device.
Second interconnection layer 12 is fixed more strongly onsilicon oxide film 10 bySOG film 24. Thus, displacement ofsilicon interconnection layer 12 can be suppressed effectively. Since the roughness of the wafer surface is eased bySOG film 24, the roughness of the surface ofsilicon oxide film 25 formed onSOG film 24 is eased. Accordingly, variation in the degree of polishing can be suppressed in polishingsilicon oxide film 25 by the CMP method. Althoughsilicon oxide film 25 is formed onSOG film 24, a PSG film may be formed instead. - Sixth Embodiment
- A semiconductor device according to a sixth embodiment will be described with reference to the drawings. Referring to FIG. 25, an
SOG film 26 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.SOG film 26 is polished by the CMP method.Third interconnection layer 17 is formed onSOG film 26. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - One example of the method of manufacturing the above described semiconductor device will be described in the following with reference to the drawing. Steps before formation of
second interconnection layer 12 onsilicon oxide film 10 are similar to the steps shown in FIGS. 2 to 5 described in the first embodiment. To coversecond interconnection layer 12, comparativelythick SOG film 26 is then formed onsilicon oxide film 10.SOG film 26 is polished by the CMP method Thereafter, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a, 15 b, 15 c, 15 d and the third interconnection layer is formed onSOG film 26 to complete the semiconductor device shown in FIG. 25. - Especially, the following effects are attained in the above described semiconductor device.
Second interconnection layer 12 is fixed strongly onsilicon oxide film 10 by comparativelythick SOG film 26. Therefore,BPSG film 9 is planarized over the entire wafer surface and displacement ofsecond interconnection layer 12 can be further suppressed. SinceSOG film 26 is polished and planarized over the entire wafer surface,third interconnection layer 17 with high dimensional precision can be formed more easily. - Seventh Embodiment
- A semiconductor device according to a seventh embodiment will be described with reference to the drawings. Referring to FIG. 27, a comparatively thin
silicon oxide film 27 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.SOG film 24 is formed onsilicon oxide film 27.BPSG film 21 is formed onSOG film 24.BPSG film 21 is reflowed by heating.Silicon oxide film 18 is formed on reflowedBPSG film 21.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawing. Referring to FIG. 28,
second interconnection layer 12 is formed onsilicon oxide film 10, and comparatively thinsilicon oxide film 27 is then formed onsilicon oxide film 10 by the CVD method to coversecond interconnection layer 12.SOG film 24 is formed onsilicon oxide film 27. Thereafter, steps similar to the steps shown in FIG. 21 described in the fourth embodiment are performed to complete the semiconductor device shown in FIG. 27. - Especially, the following effects are attained in the above described semiconductor device.
Silicon oxide film 27 is formed to coversecond interconnection layer 12. Thus, in addition to the effect of further suppressing displacement ofsecond interconnection layer 12 described in the fourth embodiment, diffusion of an impurity such as hydrogen contained inSOG film 24 tosecond interconnection layer 12 and the like can be prevented. - Although
silicon oxide film 27 is applied, as a film for protectingsecond interconnection layer 12, to the semiconductor device shown in FIG. 19 in this embodiment, the similar effects can be attained even if the film is applied to the semiconductor devices shown in FIGS. 22 and 25. - Eighth Embodiment
- A semiconductor device according to an eighth embodiment will be described with reference to the drawings. Referring to FIG. 29, a
BPSG film 28 is formed onsilicon oxide film 8.BPSG film 28 is reflowed by heating. Asilicon oxide film 29 is formed on reflowedBPSG film 28.Silicon oxide film 29 is polished by the CMP method.Second interconnection layer 12 is formed onsilicon oxide film 29. Asilicon oxide film 30 is formed onsilicon oxide film 29 to coversecond interconnection layer 12.BPSG film 14 is formed onsilicon oxide film 30.BPSG film 14 is reflowed by heating.Silicon oxide film 18 is formed on reflowedBPSG film 14.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 30, steps before formation of
silicon oxide films 8 are similar to the steps shown in FIGS. 2 and 3 described in the first embodiment. Then,BPSG film 28 having a film thickness of approximately 300 nm is formed onsilicon oxide film 8 by the CVD method.BPSG film 28 is heated at a temperature of approximately 800° C. to reflowBPSG film 28.Silicon oxide film 29 having a film thickness of approximately 600 nm is formed on reflowedBPSG film 28 by the CVD method. - Referring to FIG. 31,
silicon oxide film 29 is polished by the CMP method. Thus, the surface ofsilicon oxide film 29 is planarized over the entire wafer surface. - Referring to FIG. 32,
second interconnection layer 12 is formed onsilicon oxide film 29.Silicon oxide film 30 is formed onsilicon oxide film 29 to coversecond interconnection layer 12.Silicon oxide film 30 has a thickness of at least the substantial thickness ofsecond interconnection layer 12.BPSG film 14 is formed onsilicon oxide film 30 by the CVD method.BPSG film 14 is heated to reflowBPSG film 14.Silicon oxide film 18 is formed on reflowedBPSG film 14 by the CVD method. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Plugs, for example, of tungsten are filled in contact holes 15 a, 15 b, 15 d, 15 d and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 29. - Especially, the following effects are attained in the above described semiconductor device.
Reflowed BPSG film 28 is fixed bysilicon oxide film 29. Sincesilicon oxide film 29 is polished,silicon oxide film 29 is planarized over the entire wafer surface. Further,second interconnection layer 12 is fixed strongly onsilicon oxide film 29 bysilicon oxide film 30. Thus, even ifBPSG film 28 is transformed whenBPSG film 14 is reflowed by heating, displacement ofsecond interconnection layer 12 can be suppressed more effectively. - Since
silicon oxide film 29 is formed on reflowedBPSG film 28, the roughness of the surface is eased. Thus, variation in the degree of polishingsilicon oxide film 29 can be reduced. - Even if a corresponding configuration of the semiconductor devices shown in FIGS. 10, 13,16, 19, 22, 25, 27 is applied to the configuration above
second interconnection layer 12 as a variation of this embodiment, the effect of suppressing displacement ofsecond interconnection layer 12, the effect of obtaining interconnection layers with high dimensional precision, and the like can be attained. - Ninth Embodiment
- A semiconductor device according to a ninth embodiment will be described with reference to the drawings. Referring to FIG. 33,
BPSG film 28 is formed onsilicon oxide film 8.BPSG film 28 is reflowed by heating.Silicon oxide film 10 is formed on reflowedBPSG film 28.Second interconnection layer 12 is formed onsilicon oxide film 10.Silicon oxide film 20 is formed onsilicon oxide film 10 to coversecond interconnection layer 12.BPSG film 14 is formed onsilicon oxide film 20.BPSG film 14 is reflowed by heating.Silicon oxide film 18 is formed on reflowedBPSG film 14.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. Especially, the semiconductor device according to this embodiment is similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment without polishing by the CMP method forBPSG film 9. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 34, steps before formation of
silicon oxide film 8 are similar to the steps shown in FIG. 2 described in the first embodiment.BPSG film 28 having a film thickness of approximately 600 nm is formed onsilicon oxide film 8 by the CVD method.BPSG film 28 is heated at a temperature of 800° C. to reflowBPSG film 28. - Referring to FIG. 35,
silicon oxide film 10 having a film thickness of 100 nm is formed on reflowedBPSG film 28 by the CVD method.Second interconnection layer 12 is formed onsilicon oxide film 10.Silicon oxide film 20 is formed onsilicon oxide film 10 by the CVD method to coversecond interconnection layer 12.Silicon oxide film 20 has a thickness of at least the substantial thickness ofsecond interconnection layer 12. - Referring to FIG. 36,
BPSG film 14 having a film thickness of approximately 1000 nm is formed onsilicon oxide film 20 by the CVD method.BPSG film 14 is heated to reflowBPSG film 14. At this time, the planarity ofBPSG film 14 may be improved by etching reflowedBPSG film 14 by the RIE method or a hydrofluoric acid solution. The planarity may also be ensured by polishing reflowedBPSG film 14 by the CMP method. Then,silicon oxide film 18 is formed onBPSG film 14 by the CVD method. Contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Contact holes 15 a, 15 b, 15 c, 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 33. - Especially, the following effects are attained in the above described semiconductor device.
Second interconnection layer 12 is fixed strongly onsilicon oxide film 10 bysilicon oxide film 20. Thus, even ifBPSG film 28 is transformed by the heating for reflowingBPSG film 14, displacement ofsecond interconnection layer 12 can be suppressed. - Even if a corresponding configuration of the semiconductor devices shown in FIGS. 10, 13,16, 19, 22, 25, 27 is applied to the configuration above
second interconnection layer 12 as a variation of the semiconductor device according to this embodiment, the effect of suppressing displacement ofsecond interconnection layer 12, the effect of forming interconnection layers with high dimensional precision, and the like can be attained. - Tenth Embodiment
- A semiconductor device according to a tenth embodiment will be described with reference to the drawings. Referring to FIG. 37, a
PSG film 33 is formed onsilicon oxide film 8. Asilicon oxide film 34 is formed onPSG film 33.Silicon oxide film 34 is polished by the CMP method.Second interconnection layer 12 is formed onsilicon oxide film 34.Silicon oxide film 30 is formed onsilicon oxide film 34 to coversecond interconnection layer 12.Silicon oxide film 30 has a thickness of at least the substantial thickness ofsecond interconnection layer 12.BPSG film 21 is formed onsilicon oxide film 30.BPSG film 21 is reflowed by heating.Silicon oxide film 18 is formed onBPSG film 21.Third interconnection layer 17 is formed onsilicon oxide film 18. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 38, steps before formation of
silicon oxide film 8 are similar to the steps shown in FIG. 2 described in the first embodiment. Then,PSG film 33 having a film thickness of approximately 600 nm is formed onsilicon oxide film 8 by the CVD method. A comparatively thick silicon oxide film (not shown) is formed onPSG film 33. The silicon oxide film is polished by the CMP method. Thus,silicon oxide film 34 is planarized over the entire wafer surface. - Referring to FIG. 39,
second interconnection layer 12 is formed onsilicon oxide film 34.Silicon oxide film 30 is formed onsilicon oxide film 34 by the CVD method to coversecond interconnection layer 12.BPSG film 21 is formed onsilicon oxide film 30 by the CVD method.BPSG film 21 is heated at a temperature of approximately 800° C. to reflowBPSG film 21. Then, reflowedBPSG film 21 may be further planarized, if necessary, by etchingBPSG film 21 by the RIE method or a hydrofluoric acid solution. The reflowedBPSG film 21 may also be polished by the CMP method.Silicon oxide film 18 having a film thickness of approximately 100 nm is formed onBPSG film 21 by the CVD method. Then, contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Contact holes 15 a, 15 b, 15 c, 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 37. - Especially, the following effects are attained in the above described semiconductor device. Below
second interconnection layer 12,PSG film 33 andsilicon oxide film 34 and the like are formed and a BPSG film is not formed. Thus, even ifBPSG film 21 is heated to be reflowed,PSG film 33,silicon oxide film 34 and the like are not transformed and displacement ofsecond interconnection layer 12 can easily be prevented. - Even if a corresponding configuration of the semiconductor devices shown in FIGS. 10, 13,16, 19, 22, 25, 27 is applied to the configuration above
second interconnection layer 12 as a variation of the semiconductor device of this embodiment, similar effects are attained. - Eleventh Embodiment
- A semiconductor device according to an eleventh embodiment will be described with reference to the drawings. Referring to FIG. 40, an
SOG film 35 is formed onsilicon oxide film 8. Asilicon oxide film 36 is formed onSOG film 35.Silicon oxide film 36 is polished by the CMP method. Since other parts are similar to the semiconductor device shown in FIG. 37 described in the tenth embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawings. Referring to FIG. 41, steps before formation of
silicon oxide film 8 are similar to the steps shown in FIG. 2 described in the first embodiment.SOG film 35 having a film thickness of approximately 600 nm is formed onsilicon oxide film 8. A comparatively thick silicon oxide film (not shown) is formed onSOG film 35 by the CVD method. The silicon oxide film is polished by the CMP method to formsilicon oxide film 36. Thus,silicon oxide film 36 is planarized over the entire wafer surface. - Referring to FIG. 42,
second interconnection layer 12 is formed onsilicon oxide film 36.Silicon oxide film 30 is formed onsilicon oxide film 36 to coversecond interconnection layer 12.BPSG film 21 is formed onsilicon oxide film 30 by the CVD method.BPSG film 21 is heated to reflowBPSG film 21.Silicon oxide film 18 is formed on reflowedBPSG film 21 by the CVD method. Contact holes 15 a, 15 b, 15 c, 15 d are formed by the prescribed photolithography and RIE methods. Contact holes 15 a, 15 b, 15 c, 15 d are filled with plugs, for example, of tungsten and the third interconnection layer is formed onsilicon oxide film 18 to complete the semiconductor device shown in FIG. 40. - Especially, the following effects are attained in the above described semiconductor device. Below
second interconnection layer 12,silicon oxide film 36,SOG film 35 and the like are formed and a BPSG film is not formed. Even ifBPSG film 21 is heated to be reflowed, therefore,silicon oxide film 36,SOG film 35 and the like are not transformed. Thus, displacement ofsecond interconnection layer 12 can easily be prevented. - Further,
silicon oxide film 36 is formed onSOG film 35. Therefore, the roughness of surface of thesilicon oxide film 36 before it is polished is eased. Thus, variation in the degree of polishing in polishingsilicon oxide film 36 can be reduced. - Even if a corresponding configuration of the semiconductor devices shown in FIGS. 10, 13,16, 19, 22, 25, 27 is applied to the configuration above
second interconnection layer 12 as a variation of the semiconductor device of this embodiment, similar effects are attained. - Twelfth Embodiment
- A semiconductor device according to a twelfth embodiment will be described with reference to the drawings. Referring to FIG. 43, a
silicon oxide film 37 is formed on the surface ofsilicon semiconductor substrate 1 and on the both side surfaces ofgate electrode potion 5. Sidewall insulatingfilm 7 is formed onsilicon oxide film 37 that is formed on the both side surfaces ofgate electrode portion 5. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawing. Referring to FIG. 44,
gate electrode portion 5 and impurity diffusion layers 6 a, 6 b, 6 c, 6 d are formed on and insilicon semiconductor substrate 1 in a similar manner to the steps shown in FIG. 2 described in the first embodiment. Then,silicon oxide film 37 is formed on the both side surfaces ofgate electrode portion 5 and on impurity diffusion layers 6 a, 6 b, 6 c, Gd by the thermal oxidation method. A silicon oxide film (not shown) having a film thickness of 10 to 50 nm is formed onsilicon oxide film 37 by the CVD method. The silicon oxide film is etched by the RIE method to form sidewall insulatingfilm 7. Then, the steps shown in FIGS. 2 to 8 described in the first embodiment are performed to complete the semiconductor device shown in FIG. 43. - According to the above described semiconductor device, in addition to the effects described in the first embodiment, diffusion of boron or phosphorous contained in
BPSG film 9 tosilicon semiconductor substrate 1 can be prevented bysilicon oxide film 37. Thus, variation in the impurity concentration of impurity diffusion layers 6 a, 6 b, 6 c, 6 d can be suppressed, for example. - Meanwhile, when contact holes11 b, 15 b, 15 c and the like are to be formed, the contact holes may be formed by the self align contact method so as not to etch
gate electrode portion 5. In this case, a laminate structure of a silicon oxide film and a silicon nitride film is applied as an insulating film formed on the both side surfaces ofgate electrode portion 5. In the case of the above described semiconductor device, the contact hole by the self align contact method can be formed by applyingsilicon oxide film 37 as the silicon oxide film and applying a silicon nitride film to sidewall insulatingfilm 7. - A corresponding configuration of the semiconductor devices in the above described embodiments may be applied to the configuration above
gate electrode portion 5 as a variation of the semiconductor device according to this embodiment. - Thirteenth Embodiment
- A semiconductor device according to a thirteenth embodiment will be described with reference to the drawings. Referring to FIG. 45, a
silicon oxide film 38 is formed on impurity diffusion layers 6 a, 6 b, 6 c, 6 d that are formed atsilicon semiconductor substrate 1.BPSG film 9 is formed onsilicon oxide film 38 andgate electrode portion 5. Since other parts are similar to the configuration of the semiconductor device shown in FIG. 1 described in the first embodiment, the same elements have the same reference characters and their description will not be repeated. - A method of manufacturing the above described semiconductor device will be described in the following with reference to the drawing. Referring to FIG. 46,
gate electrode portion 5,sidewall insulating film 7 and impurity diffusion layers 6 a, 6 b, 6 c, 6 d are formed on and insilicon semiconductor substrate 1 in a similar manner to the steps shown in FIG. 2 described in the first embodiment. Then,silicon oxide film 38 is formed on impurity diffusion layers 6 a, 6 b, 6 c, 6 d by the thermal oxidation method. Thereafter, steps similar to the steps shown in FIGS. 2 to 8 described in the first embodiment are performed to complete the semiconductor device shown in FIG. 45. - According to the above described semiconductor device, in addition to the effects described in the first embodiment, diffusion of boron or phosphorous contained in
BPSG film 9 tosemiconductor substrate 1 can be prevented bysilicon oxide film 38. Thus, variation in the impurity concentration of impurity diffusion layers 6 a, 6 b, 6 c, 6 d can be suppressed. Whensilicon oxide film 8 shown in FIG. 1 is further formed onsilicon oxide film 38 to covergate electrode portion 5 in the step shown in FIG. 46, diffusion of boron or phosphorous tosilicon semiconductor substrate 1 can be prevented more effectively. - A corresponding configuration of the semiconductor devices in the above described embodiments may be applied to the configuration above
gate electrode portion 5 as a variation of the semiconductor device according to this embodiment. - The method of forming the separating oxide films, the silicon oxide films, the silicon nitride films, the interconnection layers, the plugs and the like described in the embodiments above is one example, and they may be formed by other suitable methods. Although a polycrystalline silicon film and tungsten are exemplified as a material of the plugs, aluminum or copper may also be applied. Although the BPSG film is applied as a film for reflowing and planarizing a surface by heating, a silicon oxide film containing at least one species of impurities such as phosphorous, boron and arsenic can also be applied. The impurities are not limited to the ones mentioned above. Any impurities can be used if it lowers the temperature at which a silicon oxide film softens.
- Although the present invention has been described and illustrated in detail, it is dearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims (20)
1. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a first interconnection layer formed on said semiconductor substrate;
a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer;
a second interconnection layer formed on said first interlayer insulating film; and
a second interlayer insulating film formed on said first interlayer insulating film to cover said second interconnection layer;
said first interlayer insulating film has a polished top surface or a film having a polished top surface is laminated on said first interlayer insulating film.
2. The semiconductor device according to , wherein
claim 1
said first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed, and
said reflowed impurity-doped insulating film has said polished top surface.
3. The semiconductor device according to , wherein
claim 2
an insulating film that does not contain said prescribed impurities is formed over a top surface or under a bottom surface of said impurity-doped insulating film.
4. The semiconductor device according to , wherein
claim 2
said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.
5. The semiconductor device according to , wherein said first interlayer insulating film includes
claim 1
an impurity-doped insulating film that contains prescribed impurities and is reflowed, and
an impurity-non-doped insulating film that is formed on said reflowed impurity-doped insulating film and does not contain said prescribed impurities, and
said impurity-non-doped insulating film has said polished top surface.
6. The semiconductor device according to , wherein
claim 5
an insulating film that does not contain said prescribed impurities is formed over an top surface or under a bottom surface of said impurity-doped insulating film.
7. The semiconductor device according to , wherein
claim 5
said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.
8. The semiconductor device according to , wherein
claim 1
said first interlayer insulating film includes an impurity-non-doped insulating film that does not contain prescribed impurities, and
said impurity-non-doped insulating film has said polished top surface.
9. The semiconductor device according to , wherein
claim 8
said first interlayer insulating film includes a first dipped insulating film formed on said semiconductor substrate by a Spin-On-Glass method to fill a space between said first interconnection layers, and
said impurity-non-doped insulating film is formed on said first dipped insulating film.
10. The semiconductor device according to , wherein
claim 1
said second interlayer insulating film includes an interconnection coating insulating film that has a thickness allowing fixing and holding of said second interconnection layer and covers said second interconnection layer.
11. The semiconductor device according to , wherein
claim 1
said second interlayer insulating film includes a second dipped insulating film formed on said first interlayer insulating film by a Spin-On-Glass method to fill a space between said second interconnection layers or to cover said second interconnection layer.
12. The semiconductor device according to , wherein
claim 11
said second interlayer insulating film includes an interconnection protecting film formed between said second interconnection layer and said second dipped insulating film.
13. The semiconductor device according to , wherein
claim 1
said second interlayer insulating film includes a film having a top surface that is polished or reflowed.
14. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a first interconnection layer formed on said semiconductor substrate;
a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer;
a second interconnection layer formed on said first interlayer insulating film; and
a second interlayer insulating film formed on said fist interlayer insulating film to cover said second interconnection layer;
said first interlayer insulating film including an impurity-doped insulating film that contains prescribed impurities and is reflowed, and
said second interlayer insulating film having an interconnection coating insulating film that has a thickness allowing fixing and holding of said second interconnection layer and covers said second interconnection layer.
15. The semiconductor device according to , wherein
claim 14
said interconnection coating insulating film has a thickness of at least a thickness of said second interconnection layer.
16. The semiconductor device according to , wherein
claim 14
said second interlayer insulating film includes a film having a top surface that is polished or reflowed.
17. The semiconductor device according to , wherein
claim 14
said interconnection coating insulating film includes a third dipped insulating film formed by a Spin-On-Glass method to fill a space between said second interconnection layers or to cover said second interconnection layer.
18. The semiconductor device according to , wherein
claim 17
said second interlayer insulating film includes an interconnection protecting film formed between said second interconnection layer and the third dipped insulating film.
19. The semiconductor device according to , wherein
claim 14
an insulating film that does not contain said prescribed impurities is formed over a top surface or under a bottom surface of said impurity-doped insulating film.
20. The semiconductor device according to , wherein
claim 14
said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/780,461 US6368956B2 (en) | 1998-06-03 | 2001-02-12 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10-154384(P) | 1998-06-03 | ||
JP10154384A JPH11345877A (en) | 1998-06-03 | 1998-06-03 | Semiconductor device |
JP10-154384 | 1998-06-03 | ||
US09/198,363 US6207987B1 (en) | 1998-06-03 | 1998-11-24 | Semiconductor device having smooth surface for suppressing layer displacement |
US09/780,461 US6368956B2 (en) | 1998-06-03 | 2001-02-12 | Method of manufacturing a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/198,363 Continuation US6207987B1 (en) | 1998-06-03 | 1998-11-24 | Semiconductor device having smooth surface for suppressing layer displacement |
Publications (2)
Publication Number | Publication Date |
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US20010009304A1 true US20010009304A1 (en) | 2001-07-26 |
US6368956B2 US6368956B2 (en) | 2002-04-09 |
Family
ID=15582967
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US09/198,363 Expired - Fee Related US6207987B1 (en) | 1998-06-03 | 1998-11-24 | Semiconductor device having smooth surface for suppressing layer displacement |
US09/780,461 Expired - Fee Related US6368956B2 (en) | 1998-06-03 | 2001-02-12 | Method of manufacturing a semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/198,363 Expired - Fee Related US6207987B1 (en) | 1998-06-03 | 1998-11-24 | Semiconductor device having smooth surface for suppressing layer displacement |
Country Status (4)
Country | Link |
---|---|
US (2) | US6207987B1 (en) |
JP (1) | JPH11345877A (en) |
KR (1) | KR100326220B1 (en) |
TW (1) | TW434746B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040173845A1 (en) * | 2003-03-03 | 2004-09-09 | Denso Corporation | Semiconductor device having trench gate structure and method for manufacturing the same |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11345877A (en) * | 1998-06-03 | 1999-12-14 | Mitsubishi Electric Corp | Semiconductor device |
JP2000208728A (en) * | 1999-01-18 | 2000-07-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
JP4363716B2 (en) * | 1999-06-25 | 2009-11-11 | 株式会社東芝 | LSI wiring structure design method |
JP2001127169A (en) * | 1999-10-27 | 2001-05-11 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
KR100353531B1 (en) * | 1999-11-04 | 2002-09-19 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact |
KR20010061785A (en) * | 1999-12-29 | 2001-07-07 | 박종섭 | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact |
US6541866B1 (en) * | 2001-02-07 | 2003-04-01 | Advanced Micro Devices, Inc. | Cobalt barrier for nickel silicidation of a gate electrode |
US20030222320A1 (en) * | 2002-05-31 | 2003-12-04 | Junichi Nozaki | Prevention of defects in forming a metal silicide layer |
KR100481864B1 (en) * | 2002-10-29 | 2005-04-11 | 삼성전자주식회사 | Method of forming semiconductor devices |
US6979849B2 (en) * | 2003-12-31 | 2005-12-27 | Micron Technology, Inc. | Memory cell having improved interconnect |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2560623B2 (en) * | 1993-10-05 | 1996-12-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH07169833A (en) * | 1993-12-14 | 1995-07-04 | Nec Corp | Semiconductor device and manufacture thereof |
JPH0851108A (en) | 1994-05-31 | 1996-02-20 | Kawasaki Steel Corp | Semiconductor device and manufacture thereof |
JPH08316430A (en) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | Semiconductor storage device, its manufacture, and stacked capacitor |
KR0170312B1 (en) * | 1995-06-23 | 1999-02-01 | 김광호 | Large scale integrated dram cell and its fabrication |
JPH0936229A (en) * | 1995-07-25 | 1997-02-07 | Hitachi Ltd | Semiconductor integrated circuit device and its manufacture |
US5550076A (en) * | 1995-09-11 | 1996-08-27 | Vanguard International Semiconductor Corp. | Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby |
JPH09162144A (en) * | 1995-12-05 | 1997-06-20 | Toshiba Corp | Manufacture of semiconductor device |
US5792707A (en) * | 1997-01-27 | 1998-08-11 | Chartered Semiconductor Manufacturing Ltd. | Global planarization method for inter level dielectric layers of integrated circuits |
US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
JP3102409B2 (en) * | 1998-04-30 | 2000-10-23 | 日本電気株式会社 | Wiring forming method and plasma ashing apparatus |
JPH11345877A (en) * | 1998-06-03 | 1999-12-14 | Mitsubishi Electric Corp | Semiconductor device |
-
1998
- 1998-06-03 JP JP10154384A patent/JPH11345877A/en active Pending
- 1998-11-24 US US09/198,363 patent/US6207987B1/en not_active Expired - Fee Related
- 1998-11-26 TW TW087119622A patent/TW434746B/en not_active IP Right Cessation
-
1999
- 1999-02-08 KR KR1019990004333A patent/KR100326220B1/en not_active IP Right Cessation
-
2001
- 2001-02-12 US US09/780,461 patent/US6368956B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040173845A1 (en) * | 2003-03-03 | 2004-09-09 | Denso Corporation | Semiconductor device having trench gate structure and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
KR20000005585A (en) | 2000-01-25 |
US6368956B2 (en) | 2002-04-09 |
US6207987B1 (en) | 2001-03-27 |
TW434746B (en) | 2001-05-16 |
KR100326220B1 (en) | 2002-02-27 |
JPH11345877A (en) | 1999-12-14 |
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