JPH09162144A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the flattening technology of an inter-layer insulating film and an insulating material and to improve reliability in a semiconductor device using a CMP method at low cost. SOLUTION: The TEOS inter-layer insulating film 13 by a VVD method is formed on a base pattern where wirings 12 are formed on the semiconductor substrate 11, and a BPSG film 14 is formed on the film 13. As ions are implanted through a photoresist film 15 so that density profiles are given to projecting parts 141 which are flattened with the grinding of the BPSG film 14. Later, the photoresist film 15 is peeled off. The As ions in the projecting parts 141 enter into the mesh-like holes of the BPSG film 14. Glass hardness is lowered about 30%, the projecting parts 141 become soft compared to the other parts and grinding becomes facile. Thus, the grinding speed of the projecting parts 141 locally increases and an effect that a grinding selection ratio with the part except for the projecting parts 141 increases is obtained. Then, the grinding of the part except for the projecting parts 141 is suppressed to a minimum and dishing is eliminated.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a chemical / mechanical polishing method (hereinafter referred to as CMP).
Method) is used to planarize an interlayer insulating film and an insulator of a semiconductor device, and particularly to a method of manufacturing a semiconductor device in which the flatness and reliability of the semiconductor interlayer insulating film and the insulator are improved.

[0002]

2. Description of the Related Art In the CMP method of an interlayer film or a wiring of a wafer on which a semiconductor element is formed, there are mainly two types of variations in the polishing residual film. One is the variation within the wafer surface, which is largely due to hardware factors such as the polishing apparatus, and it is not easy to take countermeasures in the process. The other is variation in each pattern in the chip, which is mainly caused by the pattern density. For example, a dishing phenomenon in which a concave portion (a portion having a rough underlying pattern) of an interlayer film becomes thin occurs, and it is very difficult at present to finish a residual film having a desired flattening level on both the concave portion and the convex portion.

As a design / process countermeasure against the difficulty of flattening the interlayer film due to the above-mentioned pattern density in the chip, (1) a wide space (rough portion) of a certain value or more is formed on the pattern in the chip. To prevent this, a dummy pattern may be formed on the base, and (2) a film (stopper) having a slower polishing rate than the film to be polished may be formed in the pattern recess.

However, in any of the above cases (1) and (2), there is a secondary problem that an expensive lithography process and redundant processes before and after the process increase, leading to an increase in cost.
For this reason, it is difficult to planarize the inside of the chip or the wafer surface by using the current CMP method without increasing the number of steps, that is, increasing the cost.

[0005]

Conventionally, there has been a problem that cost increase is indispensable in order to obtain high precision in planarizing an interlayer insulating film or an insulator of a semiconductor device. In consideration of the above-mentioned circumstances, the present invention provides a semiconductor device which can be improved in the planarization technique of the interlayer insulating film and the insulator of the semiconductor device using the CMP method and the reliability of the semiconductor device at the lowest cost. It is intended to provide a manufacturing method.

[0006]

According to the present invention, there is provided a method of manufacturing a semiconductor device comprising a step of facing a semiconductor substrate having a predetermined film to be polished on a surface thereof to a wafer polishing apparatus and polishing the film to be polished. After the formation of the film-to-be-polished, the film-to-be-polished is polished and flattened after a step of selectively forming a region in which the original atomic structure of the film is deformed in the film. .

According to the present invention, if ionic species are distributed only in the convex portion of the interlayer film to be polished, the hardness of the film in this portion is reduced (softened). As a result, the polishing rate of the convex portion locally increases, and the polishing selectivity with respect to the portion other than the convex portion increases.

[0008]

1 is a sectional view showing the most characteristic part of an embodiment of a method for manufacturing a semiconductor device according to the present invention. A TEOS interlayer insulating film 13 is formed by a CVD method on a base pattern having a first wiring (gate wiring) 12 formed on a semiconductor substrate 11. BPSG is formed on the interlayer insulating film 13.
An interlayer insulating film 14 (also referred to as a BPSG film) is formed. The interlayer insulating film 14 has a convex portion 141 reflecting the underlying pattern step. At this convex portion 141, BPSG
The original atomic structure of the film 14 is artificially deformed, and the hardness is lowered so as to facilitate polishing as compared with other portions.

By doing so, the polishing rate of only the convex portion 141 is increased with respect to the CMP process.
The effect of increasing the polishing selectivity with the deposition region 142 other than 141 can be obtained. Therefore, it is possible to selectively polish and remove the convex portion 141 in a short time without shaving the region 142. As a result, the polishing residual film (BPSG film 14)
Non-uniformity is improved.

2 and 3 are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. First, as shown in FIG.
C on the underlying pattern on which the wiring (gate wiring) 12 is formed
The TEOS interlayer insulating film 13 by the VD method is formed into a layer of 150 to 200
Then, a BPSG interlayer insulating film 14 is deposited on the interlayer insulating film 13 in a thickness of 1000 to 1100 nm. At this time, a convex portion 141 is formed by reflecting the pattern difference of the base. As a result, the step difference on the outermost surface of the BPSG film 14 becomes 500 to 700 nm at the maximum. The BPSG interlayer insulating film 14 used here is an alkoxide-based [Si (OC ₂ H ₅ ) ₄ −
Organic glass _{B (OCH 3) 3 -PH 3} ].

Next, as shown in FIG. 3, a photoresist film 15 having self-planarity is applied as a sacrificial film on the BPSG film 14 by about 1000 nm and baked at 100 to 200.degree. After that, As ions are implanted through the photoresist film 15 so that the convex portion 141 desired to be flattened by polishing the BPSG film 14 has a concentration profile. The acceleration voltage for implanting As ions at this time is several tens keV to 2
00 keV, the dose amount is about 10 ¹⁵ to 10 ¹⁷ pieces / cm ² .

Thereafter, as shown in FIG. 1, the photoresist film 15 is selectively stripped by ashing and hydrogen peroxide treatment. As ions implanted in the convex portion 141 enter the holes 145 of the network structure (tetrahedra network structure) of the BPSG film 14 as shown in FIG. 4, and the network structure becomes an open structure, so that the hardness of the glass is 30%. It goes down. R ⁺ shown in the figure represents an As ion here.

FIG. 5 is a characteristic diagram showing changes in the polishing rate (polishing rate) with respect to the polishing time of the BPSG film 14. A curve R0 is a concave portion other than the convex portion 141 of the BPSG film 14, and a curve R1 is a BPS in which As ions are implanted.
This is the characteristic of the convex portion 141 of the G film 14. When polishing is started, the convex portion 141 having a high polish rate is removed in a short time, and eventually the BPSG film 14 other than the convex portion 141 having a different selectivity is polished together, and the polishing end point is reached at the point J1.

The curve R2 represents the conventional technique, that is, the polishing of the convex portion of the BPSG film 14 when ion implantation is not performed. The polishing rate is lower than that of the present invention, and the convex portion 14
Since there is no difference in the selection ratio from the BPSG film 14 other than 1, the convex portion
Other 141 BPSG films until completely removed
It is necessary to polish for a certain time even if it enters the polishing point where both are polished, and the polishing end point is reached at point J2.

FIG. 6 is a sectional view showing the structure of FIG. 1 polished and flattened by the method of the invention described above. Polishing residual film (BPSG film) without dishing depending on the underlying pattern
The non-uniformity of 14) is improved. Incidentally, FIG. 7 is a sectional view corresponding to FIG. 6 flattened by the conventional method. There is dishing in the pattern recess.

According to the method of the present invention, a good flattened shape can be obtained at the polishing end point J1 which is shorter than the conventional polishing end point J2 by making full use of the end point detection function. This has the advantages of improved throughput and increased productivity. Also,
High-quality products can be expected by producing reliability that the focus margin is not impaired in the photolithography performed in each process thereafter.

FIG. 8 is a sectional view showing a main part of a method of manufacturing a semiconductor device according to the second embodiment of the present invention. First
The process different from the embodiment is that when the photoresist film 15 having self-flatness is applied as a sacrificial film on the BPSG film 14, the concave portion of the BPSG film 14 is filled and the convex portion 141 is at least exposed. It is applied and baked at 100 to 200 ° C. After that, As ions are implanted through the photoresist film 15 so that the convex portion 141 desired to be flattened by polishing the BPSG film 14 has a concentration profile. Other steps are the same as those in the above-described first embodiment.

Also in the above-described embodiment, since the convex portion 145 of the BPSG film 14 is softer than the other portions, the convex portion
The polishing rate of 145 locally increases, and the polishing selectivity with the region other than the convex portion 145 increases. As a result, the BPSG film 14 can be uniformly flattened without depending on the underlying pattern density.

Although As was used for ion implantation in each of the above-mentioned embodiments, the implanted ion species are P, B (BF
₂ ), Ge, F, Ar or the like as long as it has an effect of partially changing the hardness of the interlayer film.

When a desired concentration profile of ionic species cannot be obtained by only ion implantation, annealing treatment may be performed for the purpose of solid-phase diffusion of ionic species after the photoresist film (15) is peeled off. Further, when the desired concentration profile cannot be obtained by only one ion implantation, the ion implantation step or CMP step can be repeated twice or more. The present invention can be applied to the interlayer films of all wiring layers, and the film to be polished is not limited to the BPSG film, and any glass having a mesh structure may be used.

[0021]

As described above, according to the present invention,
Non-uniformity of the polishing residual film (dishing phenomenon, etc.) mainly depending on the underlying pattern density is improved. In addition, since it is not necessary to include an expensive photolithography process for forming a base dummy pattern for preventing dishing and patterning a stopper film, redundant cost increase is unnecessary.

Further, since it is possible to increase the polishing rate of the film of the portion to be polished while optimizing the polishing rate in terms of the apparatus, it is possible to perform the polishing treatment which is significantly flattened in a short time as compared with the conventional method. Therefore, the throughput is improved. Further, even if the underlying mask pattern is changed, a large process change is not required, and a versatile and flexible semiconductor device manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the most characteristic part of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a first cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a second cross-sectional view following FIG. 2 showing the method of manufacturing the semiconductor device according to the first embodiment of the invention in the order of steps.

FIG. 4 is a schematic diagram of a tetrahedra network structure of alkoxide-based organic glass (BPSG).

FIG. 5 is a characteristic diagram showing changes in the polishing rate (polishing rate) with respect to the polishing time of the BPSG film 14.

FIG. 6 is a cross-sectional view of the structure of FIG. 1 polished and flattened by the method of the invention described above.

FIG. 7 is a sectional view corresponding to FIG. 6, which is flattened by a conventional method.

FIG. 8 is a sectional view showing an essential part of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... First wiring (gate wiring), 13 ...
TEOS interlayer insulating film, 14 ... BPSG interlayer insulating film (BPS
G film), 141 ... Convex portion where As is distributed in high concentration, 145 ...
Holes of network structure (tetrahedra network structure) of BPSG film, 15 ... Photoresist film

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the step of facing a semiconductor substrate having a predetermined film to be polished on a surface thereof to a wafer polishing apparatus and polishing the film to be polished, the method comprising: A method of manufacturing a semiconductor device, comprising the steps of forming a region in which the original atomic structure of the film is deformed, and then polishing and planarizing the film to be polished. 2. A method of manufacturing a semiconductor device, comprising the step of facing a semiconductor substrate having a predetermined film to be polished on a surface thereof to a wafer polishing apparatus and polishing the film to be polished, the method comprising: A step of forming a sacrificial film having self-flatness on the film, a step of implanting ions so that impurities are distributed to a predetermined region in the film to be polished through the sacrificial film; And a step of polishing and flattening the film to be polished after the film is peeled off. 3. A method of manufacturing a semiconductor device, comprising the step of facing a semiconductor substrate having a predetermined film to be polished on a surface thereof to a wafer polishing apparatus and polishing the film to be polished, the method comprising: Forming a sacrificial film having a self-flatness on the film to be polished and having a thickness such that the concave portions of the film to be polished are filled and the convex portions are exposed; A semiconductor device comprising: a step of implanting ions so that impurities are distributed in a region of a convex portion of a polishing film; and a step of removing the sacrificial film and then polishing and flattening the film to be polished. Production method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the ion implantation locally deforms an atomic structure in the film to be polished only in a region where impurities are distributed. 5. The ion implantation locally deforms the atomic structure in the film to be polished only in the region where the impurities are distributed, thereby lowering the mechanical hardness only in the region where the impurities are distributed in the film to be polished. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the polishing rate is selectively increased. 6. The method according to claim 2, further comprising the step of heat-treating after removing the sacrificial film in order to diffuse impurities in the film to be polished by the ion implantation.
The manufacturing method of the semiconductor device described in the above. 7. The method of manufacturing a semiconductor device according to claim 2, wherein the ion implantation and the polishing for the film to be polished are repeated twice or more.