KR970052613A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

The present invention provides a low cost realization of an improvement in the planarization technology of the interlayer insulating film or insulator of the semiconductor device using the CMP method and the improvement of reliability.

The TEOS interlayer insulating film 13 by the CVD method is formed on the base pattern on which the wiring 12 is formed on the semiconductor substrate 11, and the BPSG film 14 is formed thereon. As ions are implanted over the photoresist film 15 to have a concentration profile in the block portion 141 to be planarized by polishing the BPSG film 14, and then the photoresist film 15 is peeled off. As ions of the convex portion 141 are inserted into the hollow holes of the mesh structure of the BPSG film 14, the glass hardness decreases by about 30%, and the convex portion 141 is softened in comparison with the other portions, and is easily polished. do. As a result, the polishing rate of the convex portion 141 is increased locally, and the polishing selectivity other than the convex portion 141 is increased, and the polishing other than the convex portion 141 is suppressed to a minimum. eliminates dishing)

Description

Manufacturing Method of Semiconductor Device

As this is a public information case, the full text was not included.

1 is a cross-sectional view showing the most characteristic part of the embodiment of the manufacturing method of the semiconductor device of the present invention.

Claims (11)

A method of fabricating a semiconductor device, the method comprising: polishing a surface of a semiconductor substrate, the semiconductor substrate having a predetermined surface to be polished on a surface thereof, in which the original atomic structure of the film is formed in the film after formation of the surface to be polished; And a step of forming the deformed region, followed by polishing and planarizing the polished film. A method of manufacturing a semiconductor device, which has a process of polishing a surface of a semiconductor substrate by facing a wafer polishing apparatus with a semiconductor substrate having a predetermined surface to be polished, wherein a sacrificial film having a self-flatness is formed after the formation of the surface to be polished. And ion implantation so that impurities are distributed in a predetermined region in the to-be-finished film over the sacrificial film, and after removing the sacrificial film, the to-be-polished film is polished and planarized. A method of manufacturing a semiconductor device, which has a process of polishing a surface of a semiconductor substrate by facing a wafer polishing apparatus with a semiconductor substrate having a predetermined surface to be polished, wherein the concave portion of the surface to be polished is filled after the formation of the surface to be polished. Forming a sacrificial film having a self-smoothness than that of the film on the film to be exposed to a thickness such that the film is exposed; ion implanting the sacrificial film as a mask and distributing impurities in the convex portion of the film; And removing the sacrificial film and then polishing and planarizing the to-be-polished film. The method of manufacturing a semiconductor device according to claim 2, wherein the ion implantation locally deforms the atomic structure in the polishing film by the region where impurities are distributed. 3. The mechanical hardness of claim 2 is lowered by the ion implantation by locally modifying the atomic structure in the to-be-polished film as much as the region in which the impurities are distributed. A method for manufacturing a semiconductor device, characterized by selectively increasing the polishing speed. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of peeling the sacrificial film in order to diffuse impurities in the film to be polished by the ion implantation, followed by heat treatment. The method of manufacturing a semiconductor device according to claim 2, wherein said ion implantation and polishing are repeated two or more times on said to-be-polished film. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the ion implantation locally deforms the atomic structure in the polished film as much as a region in which impurities are distributed. 4. The mechanical hardness of claim 3, wherein the ion structure is locally modified by the ion implantation as much as the region in which the impurities are distributed, thereby lowering the mechanical hardness by the region in which the impurities are distributed. A method for manufacturing a semiconductor device, characterized by selectively increasing the polishing speed. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of peeling the sacrificial film in order to diffuse impurities in the film to be polished by the ion implantation and then performing heat treatment. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the ion implantation and polishing of the polishing film are repeated two or more times. ※ Note: The disclosure is based on the initial application.