US20010008292A1 - Densely patterned silicon-on-insulator (SOI) region on a wafer - Google Patents

Densely patterned silicon-on-insulator (SOI) region on a wafer Download PDF

Info

Publication number
US20010008292A1
US20010008292A1 US09/791,273 US79127301A US2001008292A1 US 20010008292 A1 US20010008292 A1 US 20010008292A1 US 79127301 A US79127301 A US 79127301A US 2001008292 A1 US2001008292 A1 US 2001008292A1
Authority
US
United States
Prior art keywords
silicon
layer
region
insulator
soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/791,273
Other versions
US6429488B2 (en
Inventor
Effendi Leobandung
Devendra Sadana
Dominic Schepis
Ghavam Shahidi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/791,273 priority Critical patent/US6429488B2/en
Publication of US20010008292A1 publication Critical patent/US20010008292A1/en
Application granted granted Critical
Publication of US6429488B2 publication Critical patent/US6429488B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates, in general, to the process of making a semiconductor device and, more specifically, to a process of making a semiconductor device having a silicon-on-insulator (SOI) region and a non-SOI (bulk) region.
  • SOI silicon-on-insulator
  • bulk non-SOI
  • a silicon-on-insulator (SOI) structure is formed when a buried insulating layer electrically isolates a silicon layer from a silicon substrate.
  • the SOI structure does not usually occupy the entire surface of the silicon substrate.
  • Such a selective SOI structure is disclosed by Tanigawa in U.S. Pat. No. 5,740,099, issued Apr. 14, 1998. There shown is an integrated circuit fabricated partially on the SOI structure and partially on the silicon substrate.
  • the circuit area assigned to the SOI structure is referred to as the SOI region, and the circuit area assigned outside the SOI structure is referred to as the bulk region.
  • Tanigawa teaches building regions of SOI and bulk silicon on a substrate and fabricating different types of circuits in each region. Tanigawa uses a patterned ion implant technique to build the different regions. For example, a very high dose of oxygen ions is implanted deep within the silicon at sufficient energy to form the buried layer of silicon dioxide.
  • Tanigawa's method has several drawbacks.
  • a high dose of oxygen is required to form a sharp Si/SiO 2 interface and high energy of implantation is required to achieve the buried layer.
  • This method is also known to cause defects at all of the patterned edge regions and usually results in a non-planar structure because oxidation causes expansion of the SOI portion of the wafer.
  • FIG. 1 a of the publication also FIG. 1 a of this specification, two mask levels are used to create structure 40 which includes silicon substrate 42 and insulating oxide layer 44 .
  • Oxide opening 48 is formed from a first masking process, and the height of the center portion of the oxide layer, island 50 , is controlled by a second masking process.
  • epitaxial silicon 46 is grown selectively as shown in FIG. 1 b.
  • a chemical-mechanical polish is used to remove the excess epitaxial material.
  • Insulating oxide layer 44 acts as a reference point for the chemical-mechanical polish, so that the remaining epitaxial silicon ends up flush with the oxide layer, as shown in FIG. 1 c.
  • the SOI region is formed to make the silicon island 50 completely isolated from the insulating oxide layer 44 .
  • ELO epitaxial lateral overgrowth
  • a SOI structure is one of the possible candidates for fabricating a high-performance microprocessor. It is difficult to make high-performance DRAM cells on SOI, however, because of lack of substrate connection for the DRAM pass transistors. The lack of substrate connection results from the inability to grow SOI that is sufficiently wide to allow fabrication of many DRAM cells on a single island of SOI. Because many islands of SOI need to be grown, a common substrate is lacking. Lack of a common substrate may also cause floating body effects and severe cell leakages, thereby degrading DRAM performance.
  • Sun grows the epitaxial layer over the bulk region.
  • Sun forms a shallow trench isolation (STI) region within the SOI region, and another STI region within the bulk region.
  • STI shallow trench isolation
  • Sun teaches how to form a mixed SOI region and a bulk region on a single substrate.
  • the drawback in Sun's process is that many steps are required to separate the two regions. Specifically, Sun requires the formation of the sidewall spacers, in addition to the conventional step of forming the STI regions.
  • STI region 54 is formed over the bulk region and STI region 52 is formed over the SOI region. Both STIs are formed adjacent to wall spacer 46 . Forming the trenches for the STIs is difficult because the spacer abuts the STIs.
  • the present invention provides a process for making densely patterned SOI on a wafer.
  • the process includes making a SOI region and a bulk region in a semiconductor device.
  • the process includes providing a SOI structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer.
  • a nitride layer is deposited on top of the SOI structure.
  • the SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region.
  • the silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure.
  • An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region.
  • the nitride portion above the SOI structure is finally removed.
  • a logic circuit may be formed above the SOI region and a DRAM circuit may be formed above the bulk region.
  • FIGS. 1 a - 1 c are cross-sectional views showing a process sequence for fabricating a prior art semiconductor device to grow regions of SOI on a wafer;
  • FIGS. 2 a - 2 h are cross-sectional views showing a process for fabricating a semiconductor device to make densely patterned SOI on a wafer according to this invention.
  • Wafer 10 has both SOI regions and non-SOI (or bulk) regions on substrate 12 .
  • the process sequence starts with preparation of semiconductor substrate 12 , which is a single crystal silicon.
  • An insulating oxide layer 14 for example silicon dioxide, is grown on the entire surface of semiconductor substrate 12 .
  • the insulating oxide layer has a thickness of 100-500 nm.
  • silicon layer 16 is shown formed on top of the entire surface of insulating oxide layer 14 .
  • the silicon layer 16 has a thickness ranging from 50 nm to 300 nm. The preferred thickness is approximately 200 nm. It will be appreciated that silicon layer 16 and insulating oxide layer 14 together constitute SOI structure 11 .
  • the SOI structure 11 may be provided by any conventional technique for fabricating SOI structures.
  • the SOI structure 11 may be formed by implanting a high concentration of oxygen in substrate 12 by a conventional separation-by-implanted-oxygen (SIMOX) technique.
  • the SOI structure 11 may be formed by a conventional bond and etch back process.
  • the present invention unlike conventional processes, makes SOI over the entire surface of substrate 12 . Consequently, there is no need to form SOI islands as is done in conventional processes. In addition, there is no limitation to the width of the SOI island.
  • a thin pad oxide layer 18 for example silicon dioxide, is grown on the entire surface of silicon layer 16 .
  • the pad oxide layer 18 has a thickness ranging from 5 nm to 20 nm, and preferably of 10 nm.
  • nitride is deposited on top of pad oxide layer 18 to form nitride layer 20 , as shown in FIG. 2 b.
  • the thickness of nitride layer 20 ranges from 100 nm to 500 nm.
  • Pad oxide layer 18 reduces the stress between nitride layer 20 and silicon layer 16 .
  • a photoresist (not shown) is formed on top of the nitride layer.
  • the photoresist is then patterned into a mask using, for example, conventional photolithographic techniques.
  • the top nitride layer 20 is then selectively removed using reactive ion etching (RIE). After removal, as shown in FIG. 2 c, the regions covered by the nitride layer 20 on the SOI wafer remain as SOI regions, for example, 22 a and 22 c, and the uncovered regions will be used to form either shallow trench isolation regions or will be used as bulk silicon regions.
  • RIE reactive ion etching
  • STI shallow trench isolation
  • a photoresist mask 17 is patterned into a mask using a conventional photolithographic technique.
  • the exposed STI region 28 c is etched using reactive ion etching (RIE).
  • RIE reactive ion etching
  • the etch is continued through the buried oxide layer 14 , all the way to expose substrate 12 of wafer 10 in region 22 b ′.
  • photoresist mask 17 is removed by a conventional technique and the wafer 10 is cleaned.
  • the resultant structure is shown in FIG. 2 f.
  • the next steps in the process are the cleaning of the exposed substrate 12 by using standard cleaning techniques, and the annealing of wafer 10 at high temperatures (between 1000°C.-1100°C.) to repair the silicon damaged by the RIE process.
  • a thin layer of oxide (not shown), for example silicon dioxide, is grown on top of the exposed substrate 12 .
  • the thin oxide layer has a thickness of approximately 10 nm.
  • the thin oxide layer is removed by using hydrofluoric (HF) solution, again resulting in exposing substrate 12 .
  • HF hydrofluoric
  • high-quality silicon may be grown on the part of wafer 10 that has exposed silicon substrate 12 , namely region 22 b ′, but not on the regions covered by nitride layer 20 or STI areas 28 a, 28 b, and 28 c.
  • the grown silicon is shown as epitaxial layer 26 in FIG. 2 g.
  • the thickness of epitaxial layer 26 may be adjusted such that its top surface is planar with nitride layer 20 .
  • the surface of epitaxial layer 26 may be planarized using chemical-mechanical polishing, for example by using nitride layer 20 as a stopping layer during polishing.
  • nitride layer 20 is stripped using hot phosphoric acid and pad oxide layer 18 is removed using HF solution.
  • the result of this step is shown in FIG. 2 g.
  • wafer 10 may be annealed at a high temperature (between 1000°C.-1100°C.) to fix any damage resulting after the epitaxial deposition.
  • the resulting wafer shown in FIG. 2 g has regions 22 a and 22 c with silicon on buried oxide (SOI) and region 22 b ′ without a buried oxide.
  • Region 22 b ′ forms the bulk region which is surrounded by STI regions 22 b.
  • Wafer 10 is now ready for fabricating circuitry in a conventional manner.
  • DRAM components such as cell 32 (FIG. 2 h ) may be fabricated on the epitaxial layer 26 in region 22 b ′, which has a common substrate and, therefore, does not having floating body effects.
  • Logic components, such as 30 a and 30 b, may be fabricated on the SOI regions 22 a and 22 c.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

Description

    TECHNICAL FIELD
  • The present invention relates, in general, to the process of making a semiconductor device and, more specifically, to a process of making a semiconductor device having a silicon-on-insulator (SOI) region and a non-SOI (bulk) region. [0001]
    • BACKGROUND OF THE INVENTION
  • A silicon-on-insulator (SOI) structure is formed when a buried insulating layer electrically isolates a silicon layer from a silicon substrate. The SOI structure does not usually occupy the entire surface of the silicon substrate. Such a selective SOI structure is disclosed by Tanigawa in U.S. Pat. No. 5,740,099, issued Apr. 14, 1998. There shown is an integrated circuit fabricated partially on the SOI structure and partially on the silicon substrate. The circuit area assigned to the SOI structure is referred to as the SOI region, and the circuit area assigned outside the SOI structure is referred to as the bulk region. Tanigawa teaches building regions of SOI and bulk silicon on a substrate and fabricating different types of circuits in each region. Tanigawa uses a patterned ion implant technique to build the different regions. For example, a very high dose of oxygen ions is implanted deep within the silicon at sufficient energy to form the buried layer of silicon dioxide. [0002]
  • Tanigawa's method has several drawbacks. A high dose of oxygen is required to form a sharp Si/SiO[0003] 2 interface and high energy of implantation is required to achieve the buried layer. This method is also known to cause defects at all of the patterned edge regions and usually results in a non-planar structure because oxidation causes expansion of the SOI portion of the wafer.
  • Another publication, titled “Process for Fabrication of Very Thin Epitaxial Silicon Films Over Insulating Layers,” IBM Technical Disclosure Bulletin, Volume 35, No. 2, pages 247-49 (July 1992) (author unknown), teaches the use of selective epitaxial growth of silicon to grow regions of SOI on a wafer. As shown in FIG. 1[0004] a of the publication (also FIG. 1a of this specification), two mask levels are used to create structure 40 which includes silicon substrate 42 and insulating oxide layer 44. Oxide opening 48 is formed from a first masking process, and the height of the center portion of the oxide layer, island 50, is controlled by a second masking process.
  • Next, [0005] epitaxial silicon 46 is grown selectively as shown in FIG. 1b. A chemical-mechanical polish is used to remove the excess epitaxial material. Insulating oxide layer 44 acts as a reference point for the chemical-mechanical polish, so that the remaining epitaxial silicon ends up flush with the oxide layer, as shown in FIG. 1c. In this manner, the SOI region is formed to make the silicon island 50 completely isolated from the insulating oxide layer 44.
  • This process, known as epitaxial lateral overgrowth (ELO), has its drawbacks. The area of SOI formed may only be up to approximately 10 microns thick. The size and quality of silicon is limited when the SOI formed is wider then 10 microns in [0006] regions 52 of FIG. 1c. Consequently, the amount of SOI devices on a wafer is also limited.
  • It is necessary to combine both logic and dynamic random access memory (DRAM) circuitry, for example, in the same chip in order to make a high-performance microprocessor. A SOI structure is one of the possible candidates for fabricating a high-performance microprocessor. It is difficult to make high-performance DRAM cells on SOI, however, because of lack of substrate connection for the DRAM pass transistors. The lack of substrate connection results from the inability to grow SOI that is sufficiently wide to allow fabrication of many DRAM cells on a single island of SOI. Because many islands of SOI need to be grown, a common substrate is lacking. Lack of a common substrate may also cause floating body effects and severe cell leakages, thereby degrading DRAM performance. [0007]
  • In U.S. Pat. No. 5,399,507 issued to Sun on Mar. 21, 1995, a process is disclosed for fabricating a mixed thin film and bulk semiconductor substrate. A thin film over the SOI structure is masked and etched to expose the underlying bulk substrate. An epitaxial layer is then grown to build the exposed bulk portion to form the mixed substrate. Before growing the epitaxial layer, however, Sun teaches (1) that a dielectric layer be deposited over the entire substrate, and (2) that the dielectric layer be selectively etched to form sidewall spacers in order to separate the SOI region from the bulk region in the substrate. [0008]
  • After completing the aforementioned two steps, Sun grows the epitaxial layer over the bulk region. Finally, Sun forms a shallow trench isolation (STI) region within the SOI region, and another STI region within the bulk region. Thus, Sun teaches how to form a mixed SOI region and a bulk region on a single substrate. The drawback in Sun's process is that many steps are required to separate the two regions. Specifically, Sun requires the formation of the sidewall spacers, in addition to the conventional step of forming the STI regions. Moreover, as shown in FIG. 11 of Sun's disclosure, STI region [0009] 54 is formed over the bulk region and STI region 52 is formed over the SOI region. Both STIs are formed adjacent to wall spacer 46. Forming the trenches for the STIs is difficult because the spacer abuts the STIs.
  • The deficiencies of conventional processes in making SOI and bulk regions on the same wafer, and the difficulties in making high-quality, densely patterned SOI regions suitable for microprocessors, show that a need still exists for a process which can make densely patterned SOI for merged logic and DRAM circuitry, or for other types of circuitry. [0010]
    • SUMMARY OF THE INVENTION
  • To meet this and other needs, and in view of its purposes, the present invention provides a process for making densely patterned SOI on a wafer. In one embodiment, the process includes making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed. A logic circuit may be formed above the SOI region and a DRAM circuit may be formed above the bulk region. [0011]
  • It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention. [0012]
    • BRIEF DESCRIPTION OF THE DRAWING
  • The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following figures: [0013]
  • FIGS. 1[0014] a-1 c are cross-sectional views showing a process sequence for fabricating a prior art semiconductor device to grow regions of SOI on a wafer; and
  • FIGS. 2[0015] a-2 h are cross-sectional views showing a process for fabricating a semiconductor device to make densely patterned SOI on a wafer according to this invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Referring to FIGS. 2[0016] a and 2 b of the drawing, a process for making densely patterned SOI regions in wafer 10 is shown. Wafer 10 has both SOI regions and non-SOI (or bulk) regions on substrate 12. The process sequence starts with preparation of semiconductor substrate 12, which is a single crystal silicon. An insulating oxide layer 14, for example silicon dioxide, is grown on the entire surface of semiconductor substrate 12. The insulating oxide layer has a thickness of 100-500 nm. Next, silicon layer 16 is shown formed on top of the entire surface of insulating oxide layer 14. The silicon layer 16 has a thickness ranging from 50 nm to 300 nm. The preferred thickness is approximately 200 nm. It will be appreciated that silicon layer 16 and insulating oxide layer 14 together constitute SOI structure 11.
  • The [0017] SOI structure 11 may be provided by any conventional technique for fabricating SOI structures. For example, the SOI structure 11 may be formed by implanting a high concentration of oxygen in substrate 12 by a conventional separation-by-implanted-oxygen (SIMOX) technique. Alternatively, the SOI structure 11 may be formed by a conventional bond and etch back process.
  • It will be appreciated that the present invention, unlike conventional processes, makes SOI over the entire surface of [0018] substrate 12. Consequently, there is no need to form SOI islands as is done in conventional processes. In addition, there is no limitation to the width of the SOI island.
  • A thin [0019] pad oxide layer 18, for example silicon dioxide, is grown on the entire surface of silicon layer 16. The pad oxide layer 18 has a thickness ranging from 5 nm to 20 nm, and preferably of 10 nm. Next, nitride is deposited on top of pad oxide layer 18 to form nitride layer 20, as shown in FIG. 2b. The thickness of nitride layer 20 ranges from 100 nm to 500 nm. Pad oxide layer 18 reduces the stress between nitride layer 20 and silicon layer 16.
  • By methods well known in the art, a photoresist (not shown) is formed on top of the nitride layer. The photoresist is then patterned into a mask using, for example, conventional photolithographic techniques. The [0020] top nitride layer 20 is then selectively removed using reactive ion etching (RIE). After removal, as shown in FIG. 2c, the regions covered by the nitride layer 20 on the SOI wafer remain as SOI regions, for example, 22 a and 22 c, and the uncovered regions will be used to form either shallow trench isolation regions or will be used as bulk silicon regions.
  • Using the same patterned photoresist mask and selective RIE, the [0021] silicon layer 16 is removed in regions 22 b, 22 d, and 22 e, all the way down to the buried oxide layer 14. Next, shallow trench isolation (STI) is defined to bound the SOI regions 22 a and 22 c. STI areas 28 a and 28 b isolate regions 22 c from 22 a, while STI areas 28 a and 28 c isolate region 22 a, as shown in FIG. 2d.
  • Now referring to FIG. 2[0022] e, a photoresist mask 17 is patterned into a mask using a conventional photolithographic technique. The exposed STI region 28 c is etched using reactive ion etching (RIE). The etch is continued through the buried oxide layer 14, all the way to expose substrate 12 of wafer 10 in region 22 b′. Next, photoresist mask 17 is removed by a conventional technique and the wafer 10 is cleaned. The resultant structure is shown in FIG. 2f.
  • The next steps in the process are the cleaning of the exposed [0023] substrate 12 by using standard cleaning techniques, and the annealing of wafer 10 at high temperatures (between 1000°C.-1100°C.) to repair the silicon damaged by the RIE process. During annealing, a thin layer of oxide (not shown), for example silicon dioxide, is grown on top of the exposed substrate 12. The thin oxide layer has a thickness of approximately 10 nm. Next, the thin oxide layer is removed by using hydrofluoric (HF) solution, again resulting in exposing substrate 12.
  • It will be appreciated that high-quality silicon may be grown on the part of [0024] wafer 10 that has exposed silicon substrate 12, namely region 22 b′, but not on the regions covered by nitride layer 20 or STI areas 28 a, 28 b, and 28 c. The grown silicon is shown as epitaxial layer 26 in FIG. 2g. The thickness of epitaxial layer 26 may be adjusted such that its top surface is planar with nitride layer 20. Although not shown, the surface of epitaxial layer 26 may be planarized using chemical-mechanical polishing, for example by using nitride layer 20 as a stopping layer during polishing.
  • Next, [0025] nitride layer 20 is stripped using hot phosphoric acid and pad oxide layer 18 is removed using HF solution. The result of this step is shown in FIG. 2g. Finally, wafer 10 may be annealed at a high temperature (between 1000°C.-1100°C.) to fix any damage resulting after the epitaxial deposition. The resulting wafer shown in FIG. 2g has regions 22 a and 22 c with silicon on buried oxide (SOI) and region 22 b′ without a buried oxide. Region 22 b′ forms the bulk region which is surrounded by STI regions 22 b.
  • [0026] Wafer 10 is now ready for fabricating circuitry in a conventional manner. For example, DRAM components such as cell 32 (FIG. 2h) may be fabricated on the epitaxial layer 26 in region 22 b′, which has a common substrate and, therefore, does not having floating body effects. Logic components, such as 30 a and 30 b, may be fabricated on the SOI regions 22 a and 22 c.
  • It will now be appreciated that the inventors have developed a new process for making SOI and non-SOI (bulk) regions on a wafer. Because the inventors first start with SOI on the entire substrate and then make bulk regions selectively on the substrate, the SOI has no transitions in which defects may be formed at the patterned edges. Consequently, the SOI regions may be densely patterned. [0027]
  • Although illustrated and described herein with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention. It will be understood, for example, that the present invention is not limited to only making merged logic and DRAM circuitry on a wafer. Rather, the invention may be extended to any other type of circuit which may be densely patterned on SOI regions and any other type of circuit which may be patterned on bulk regions. [0028]

Claims (16)

What is claimed:
1. A process for making a silicon-on-insulator region and a bulk region in a semiconductor device, the process comprising the steps of:
(a) providing a silicon-on-insulator structure, the silicon-on-insulator structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer;
(b) forming a nitride layer on top of the silicon-on-insulator structure;
(c) selectively etching portions of the nitride layer to expose the silicon-on-insulator structure, a portion of the nitride layer not etched forming the silicon-on-insulator region;
(d) selectively etching a portion of the exposed silicon-on-insulator structure to expose the silicon substrate;
(e) growing an epitaxial layer on top of the expose silicon substrate to form the bulk region; and
f) removing the nitride portion above the silicon-on-insulator structure.
2. The process of
claim 1
 wherein step (a) includes implanting a high concentration of oxygen into the substrate to form the insulating oxide layer.
3. The process of
claim 1
 wherein step (b) includes forming a pad oxide layer on top of the silicon-on-insulator structure prior to forming the nitride layer.
4. The process of
claim 1
 wherein step (c) includes forming a shallow trench isolation to bound the silicon-on-insulator region.
5. The process of
claim 1
 wherein step (f) further includes forming a first type of circuit above the silicon-on-insulator region and a second type of circuit above the bulk region.
6. The process of
claim 5
 wherein the first type of circuit is a logic circuit and the second type of circuit is a DRAM circuit.
7. The process of
claim 5
 wherein step (d) further includes annealing the semiconductor device at a temperature between 1000°C.-1100°C. after the silicon substrate is exposed.
8. The process of
claim 5
 wherein etching includes reactive ion etching.
9. A semiconductor device made by the process of
claim 1
.
10. A process for making dense patterned silicon-on-insulator for merged logic and DRAM circuitry on a wafer, the process comprising the steps of:
a) providing a silicon-on-insulator structure, the silicon-on-insulator structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer;
(b) forming a nitride layer on top of the silicon-on-insulator structure;
(c) selectively etching portions of the nitride layer to expose the silicon-on-insulator structure, a portion of the nitride layer not etched forming a silicon-on-insulator region;
(d) selectively etching a portion of the exposed silicon-on-insulator structure to expose the silicon substrate;
(e) growing an epitaxial layer on top of the exposed silicon substrate to form a bulk region;
(f) removing the nitride portion above the silicon-on-insulator structure; and
(g) forming the logic circuitry above the silicon-on-insulator region and the DRAM circuitry above the bulk region.
11. The process of
claim 10
 wherein step (a) includes implanting a high concentration of oxygen into the substrate to form the insulating oxide layer.
12. The process of
claim 10
 wherein step (b) includes forming a pad oxide layer on top of the silicon-on-insulator structure prior to forming the nitride layer.
13. The process of
claim 10
 wherein step (c) includes forming a shallow trench isolation to bound the silicon-on-insulator region.
14. The process of
claim 10
 wherein step (d) further includes annealing the wafer at a temperature between 1000°C.-1100°C. after the silicon substrate is exposed.
15. The process of
claim 10
 wherein etching includes reactive ion etching.
16. A semiconductor device made by the process of
claim 10
.
US09/791,273 1998-11-17 2001-02-22 Densely patterned silicon-on-insulator (SOI) region on a wafer Expired - Fee Related US6429488B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/791,273 US6429488B2 (en) 1998-11-17 2001-02-22 Densely patterned silicon-on-insulator (SOI) region on a wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/193,606 US6214694B1 (en) 1998-11-17 1998-11-17 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
US09/791,273 US6429488B2 (en) 1998-11-17 2001-02-22 Densely patterned silicon-on-insulator (SOI) region on a wafer

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/193,606 Division US6214694B1 (en) 1998-11-17 1998-11-17 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Publications (2)

Publication Number Publication Date
US20010008292A1 true US20010008292A1 (en) 2001-07-19
US6429488B2 US6429488B2 (en) 2002-08-06

Family

ID=22714309

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/193,606 Expired - Fee Related US6214694B1 (en) 1998-11-17 1998-11-17 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
US09/791,273 Expired - Fee Related US6429488B2 (en) 1998-11-17 2001-02-22 Densely patterned silicon-on-insulator (SOI) region on a wafer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/193,606 Expired - Fee Related US6214694B1 (en) 1998-11-17 1998-11-17 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Country Status (2)

Country Link
US (2) US6214694B1 (en)
KR (1) KR100413911B1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030094641A1 (en) * 2001-11-21 2003-05-22 Fernando Gonzalez Methods of forming semiconductor circuitry, and semiconductor constructions
US20030201512A1 (en) * 2002-02-13 2003-10-30 Takashi Yamada Semiconductor device having one of patterned SOI and SON structure
US20040137672A1 (en) * 2003-01-14 2004-07-15 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled cmos transistors
US20050191797A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same
US20060284278A1 (en) * 2005-06-21 2006-12-21 Freescale Semiconductor, Inc. Area diode formation in SOI application
US20080217689A1 (en) * 2007-03-05 2008-09-11 Yong-Hoon Son Semiconductor devices having silicon-on-insulator (soi) substrates and methods of manufacturing the same
CN102201372A (en) * 2011-03-29 2011-09-28 上海宏力半导体制造有限公司 Semiconductor device and manufacturing method thereof
US20120214289A1 (en) * 2011-02-21 2012-08-23 Institute of Microelectronics, Chinese Academy of Sciences Method for Forming Semiconductor Substrate Isolation
CN103545363A (en) * 2012-07-09 2014-01-29 上海华虹Nec电子有限公司 P-type high-voltage Metal Oxide Semiconductor (LDMOS) device and production method thereof
CN103824857A (en) * 2012-11-15 2014-05-28 格罗方德半导体公司 Semiconductor structure including semiconductor-on-insulator region and bulk region, and method for the formation thereof

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1308063B1 (en) * 1999-05-28 2001-11-29 St Microelectronics Srl PROCEDURE FOR THE CREATION OF A SLICE OF SEMI-CONDUCTING MATERIALS INCLUDING DIELECTRICALLY POWER REGIONS
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
US6808944B1 (en) * 2000-07-24 2004-10-26 Cypress Semiconductor Corporation Structure and method for monitoring a semiconductor process, and method of making such a structure
TWI230392B (en) 2001-06-18 2005-04-01 Innovative Silicon Sa Semiconductor device
JP4322453B2 (en) * 2001-09-27 2009-09-02 株式会社東芝 Semiconductor device and manufacturing method thereof
KR100434955B1 (en) * 2001-11-28 2004-06-09 주식회사 하이닉스반도체 CMOS of semiconductor device and method for manufacturing the same
JP3825688B2 (en) * 2001-12-25 2006-09-27 株式会社東芝 Manufacturing method of semiconductor device
US6630714B2 (en) * 2001-12-27 2003-10-07 Kabushiki Kaisha Toshiba Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer
JP2003203967A (en) * 2001-12-28 2003-07-18 Toshiba Corp Method for forming partial soi wafer, semiconductor device and its manufacturing method
JP3831277B2 (en) * 2001-12-28 2006-10-11 株式会社東芝 Semiconductor device
US6569729B1 (en) 2002-07-19 2003-05-27 Taiwan Semiconductor Manufacturing Company Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application
EP1357603A3 (en) 2002-04-18 2004-01-14 Innovative Silicon SA Semiconductor device
EP1355316B1 (en) * 2002-04-18 2007-02-21 Innovative Silicon SA Data storage device and refreshing method for use with such device
US6828202B1 (en) 2002-10-01 2004-12-07 T-Ram, Inc. Semiconductor region self-aligned with ion implant shadowing
US6912150B2 (en) * 2003-05-13 2005-06-28 Lionel Portman Reference current generator, and method of programming, adjusting and/or operating same
US20040228168A1 (en) * 2003-05-13 2004-11-18 Richard Ferrant Semiconductor memory device and method of operating same
US7085153B2 (en) * 2003-05-13 2006-08-01 Innovative Silicon S.A. Semiconductor memory cell, array, architecture and device, and method of operating same
US6875656B2 (en) * 2003-05-22 2005-04-05 Texas Instruments Incorporated Method for improving silicon-on-insulator (SOI) film uniformity on a semiconductor wafer
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7335934B2 (en) * 2003-07-22 2008-02-26 Innovative Silicon S.A. Integrated circuit device, and method of fabricating same
JP2005072084A (en) * 2003-08-28 2005-03-17 Toshiba Corp Semiconductor device and its fabricating process
US7184298B2 (en) * 2003-09-24 2007-02-27 Innovative Silicon S.A. Low power programming technique for a floating body memory transistor, memory cell, and memory array
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
US7476939B2 (en) * 2004-11-04 2009-01-13 Innovative Silicon Isi Sa Memory cell having an electrically floating body transistor and programming technique therefor
US7251164B2 (en) * 2004-11-10 2007-07-31 Innovative Silicon S.A. Circuitry for and method of improving statistical distribution of integrated circuits
US7301838B2 (en) * 2004-12-13 2007-11-27 Innovative Silicon S.A. Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US7301803B2 (en) * 2004-12-22 2007-11-27 Innovative Silicon S.A. Bipolar reading technique for a memory cell having an electrically floating body transistor
US7410840B2 (en) * 2005-03-28 2008-08-12 Texas Instruments Incorporated Building fully-depleted and bulk transistors on same chip
US20070023833A1 (en) * 2005-07-28 2007-02-01 Serguei Okhonin Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
US7606066B2 (en) 2005-09-07 2009-10-20 Innovative Silicon Isi Sa Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US7355916B2 (en) * 2005-09-19 2008-04-08 Innovative Silicon S.A. Method and circuitry to generate a reference current for reading a memory cell, and device implementing same
US7459748B2 (en) * 2005-10-17 2008-12-02 Kabushiki Kaisha Toshiba Semiconductor memory device
US20070085140A1 (en) * 2005-10-19 2007-04-19 Cedric Bassin One transistor memory cell having strained electrically floating body region, and method of operating same
US7683430B2 (en) * 2005-12-19 2010-03-23 Innovative Silicon Isi Sa Electrically floating body memory cell and array, and method of operating or controlling same
US8530355B2 (en) * 2005-12-23 2013-09-10 Infineon Technologies Ag Mixed orientation semiconductor device and method
US7542345B2 (en) * 2006-02-16 2009-06-02 Innovative Silicon Isi Sa Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
DE102006015076B4 (en) * 2006-03-31 2014-03-20 Advanced Micro Devices, Inc. Semiconductor device with SOI transistors and solid-state transistors and a method for manufacturing
US7492632B2 (en) * 2006-04-07 2009-02-17 Innovative Silicon Isi Sa Memory array having a programmable word length, and method of operating same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7606098B2 (en) 2006-04-18 2009-10-20 Innovative Silicon Isi Sa Semiconductor memory array architecture with grouped memory cells, and method of controlling same
WO2007128738A1 (en) * 2006-05-02 2007-11-15 Innovative Silicon Sa Semiconductor memory cell and array using punch-through to program and read same
US8069377B2 (en) * 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7542340B2 (en) * 2006-07-11 2009-06-02 Innovative Silicon Isi Sa Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
KR101277402B1 (en) 2007-01-26 2013-06-20 마이크론 테크놀로지, 인코포레이티드 Floating-body dram transistor comprising source/drain regions separated from the gated body region
WO2009031052A2 (en) 2007-03-29 2009-03-12 Innovative Silicon S.A. Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8085594B2 (en) * 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US8194487B2 (en) 2007-09-17 2012-06-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
US8349662B2 (en) * 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells
US8014195B2 (en) * 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8189376B2 (en) * 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US7957206B2 (en) * 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7933140B2 (en) 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7924630B2 (en) * 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US8223574B2 (en) * 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
US8213226B2 (en) * 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8319294B2 (en) * 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
WO2010102106A2 (en) 2009-03-04 2010-09-10 Innovative Silicon Isi Sa Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
WO2010114890A1 (en) * 2009-03-31 2010-10-07 Innovative Silicon Isi Sa Techniques for providing a semiconductor memory device
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8508994B2 (en) * 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8498157B2 (en) * 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9076543B2 (en) * 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8199595B2 (en) * 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8174881B2 (en) 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
US8310893B2 (en) * 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
US8416636B2 (en) * 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8411513B2 (en) * 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8369177B2 (en) * 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
CN102812552B (en) 2010-03-15 2015-11-25 美光科技公司 Semiconductor memory system and the method for being biased semiconductor memory system
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
US8772902B2 (en) * 2012-04-19 2014-07-08 International Business Machines Corporation Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration
CN103545346B (en) * 2012-07-09 2016-11-16 上海华虹宏力半导体制造有限公司 Isolated form N-type LDMOS device and manufacture method thereof
US10056293B2 (en) * 2014-07-18 2018-08-21 International Business Machines Corporation Techniques for creating a local interconnect using a SOI wafer

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661832A (en) * 1982-06-30 1987-04-28 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4758531A (en) * 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG
US4960726A (en) * 1989-10-19 1990-10-02 International Business Machines Corporation BiCMOS process
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate
JPH03173175A (en) 1989-12-01 1991-07-26 Hitachi Ltd Semiconductor device
US5151387A (en) * 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
US5086016A (en) * 1990-10-31 1992-02-04 International Business Machines Corporation Method of making semiconductor device contact including transition metal-compound dopant source
US5279987A (en) 1991-10-31 1994-01-18 International Business Machines Corporation Fabricating planar complementary patterned subcollectors with silicon epitaxial layer
US5298784A (en) * 1992-03-27 1994-03-29 International Business Machines Corporation Electrically programmable antifuse using metal penetration of a junction
JP3116609B2 (en) * 1992-11-25 2000-12-11 日本電気株式会社 Method for manufacturing semiconductor device
US5394294A (en) * 1992-12-17 1995-02-28 International Business Machines Corporation Self protective decoupling capacitor structure
US5314840A (en) * 1992-12-18 1994-05-24 International Business Machines Corporation Method for forming an antifuse element with electrical or optical programming
US5504434A (en) * 1992-12-18 1996-04-02 International Business Machines Corporation Instrument for the measurement of electrical characteristics during manufacturing processes
EP0606758B1 (en) * 1992-12-30 2000-09-06 Samsung Electronics Co., Ltd. Method of producing an SOI transistor DRAM
JP2526786B2 (en) * 1993-05-22 1996-08-21 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5597738A (en) 1993-12-03 1997-01-28 Kulite Semiconductor Products, Inc. Method for forming isolated CMOS structures on SOI structures
US5622892A (en) * 1994-06-10 1997-04-22 International Business Machines Corporation Method of making a self cooling electrically programmable fuse
US5399507A (en) * 1994-06-27 1995-03-21 Motorola, Inc. Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
US5444287A (en) * 1994-08-10 1995-08-22 International Business Machines Corporation Thermally activated noise immune fuse
JP2806286B2 (en) 1995-02-07 1998-09-30 日本電気株式会社 Semiconductor device
US5770875A (en) 1996-09-16 1998-06-23 International Business Machines Corporation Large value capacitor for SOI
US5811357A (en) * 1997-03-26 1998-09-22 International Business Machines Corporation Process of etching an oxide layer
US5909626A (en) * 1997-03-28 1999-06-01 Nec Corporation SOI substrate and fabrication process therefor

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967132B2 (en) 2001-11-21 2005-11-22 Micron Technology, Inc. Methods of forming semiconductor circuitry
US6979631B2 (en) 2001-11-21 2005-12-27 Micron Technology, Inc. Methods of forming semiconductor circuitry
US20030094641A1 (en) * 2001-11-21 2003-05-22 Fernando Gonzalez Methods of forming semiconductor circuitry, and semiconductor constructions
US20040183134A1 (en) * 2001-11-21 2004-09-23 Micron Technology, Inc. Methods of forming semiconductor circuitry
US20040185606A1 (en) * 2001-11-21 2004-09-23 Micron Technology, Inc. Methods of forming semiconductor circuitry
US20030151048A1 (en) * 2001-11-21 2003-08-14 Fernando Gonzalez Methods of forming semiconductor circuitry, and semiconductor constructions
US6861326B2 (en) 2001-11-21 2005-03-01 Micron Technology, Inc. Methods of forming semiconductor circuitry
US7199017B2 (en) 2001-11-21 2007-04-03 Micron Technology, Inc. Methods of forming semiconductor circuitry
US6894310B2 (en) * 2001-11-21 2005-05-17 Micron Technology, Inc. Semiconductor constructions comprising monocrystalline silicon together with semiconductive materials comprising elements other than silicon
US20030201512A1 (en) * 2002-02-13 2003-10-30 Takashi Yamada Semiconductor device having one of patterned SOI and SON structure
US6800530B2 (en) 2003-01-14 2004-10-05 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
US20040137672A1 (en) * 2003-01-14 2004-07-15 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled cmos transistors
US20050191797A1 (en) * 2004-02-27 2005-09-01 Koji Usuda Semiconductor device and method of manufacturing the same
US7229892B2 (en) * 2004-02-27 2007-06-12 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20060284278A1 (en) * 2005-06-21 2006-12-21 Freescale Semiconductor, Inc. Area diode formation in SOI application
US7517742B2 (en) * 2005-06-21 2009-04-14 Freescale Semiconductor, Inc. Area diode formation in SOI application
US20080217689A1 (en) * 2007-03-05 2008-09-11 Yong-Hoon Son Semiconductor devices having silicon-on-insulator (soi) substrates and methods of manufacturing the same
US20120214289A1 (en) * 2011-02-21 2012-08-23 Institute of Microelectronics, Chinese Academy of Sciences Method for Forming Semiconductor Substrate Isolation
US8426282B2 (en) * 2011-02-21 2013-04-23 Institute of Microelectronics, Chinese Academy of Sciences Method for forming semiconductor substrate isolation
CN102201372A (en) * 2011-03-29 2011-09-28 上海宏力半导体制造有限公司 Semiconductor device and manufacturing method thereof
CN103545363A (en) * 2012-07-09 2014-01-29 上海华虹Nec电子有限公司 P-type high-voltage Metal Oxide Semiconductor (LDMOS) device and production method thereof
CN103824857A (en) * 2012-11-15 2014-05-28 格罗方德半导体公司 Semiconductor structure including semiconductor-on-insulator region and bulk region, and method for the formation thereof

Also Published As

Publication number Publication date
US6214694B1 (en) 2001-04-10
KR100413911B1 (en) 2004-01-07
US6429488B2 (en) 2002-08-06
KR20000035489A (en) 2000-06-26

Similar Documents

Publication Publication Date Title
US6214694B1 (en) Process of making densely patterned silicon-on-insulator (SOI) region on a wafer
US6228727B1 (en) Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
US5691230A (en) Technique for producing small islands of silicon on insulator
US6211039B1 (en) Silicon-on-insulator islands and method for their formation
US5747377A (en) Process for forming shallow trench isolation
KR960016502B1 (en) Integrated circuit isolation method
US6404014B1 (en) Planar and densely patterned silicon-on-insulator structure
US4954459A (en) Method of planarization of topologies in integrated circuit structures
EP0570043A2 (en) Bicmos SOI wafer having thin and thick SOI regions of silicon
US5436173A (en) Method for forming a semiconductor on insulator device
US7115463B2 (en) Patterning SOI with silicon mask to create box at different depths
US5891763A (en) Damascene pattering of SOI MOS transistors
US6046477A (en) Dense SOI programmable logic array structure
US6255145B1 (en) Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product
US6548345B2 (en) Method of fabricating trench for SOI merged logic DRAM
US4731343A (en) Method for manufacturing insulation separating the active regions of a VLSI CMOS circuit
KR100244847B1 (en) Methods to prevent divot formation in shallow trench isolation areas and integrated circuit chip formed thereby
US5970367A (en) Double damascene pattering of silcon-on-insulator transistors
EP1109216B1 (en) Process of making a semiconductor device having regions of insulating material formed in a semiconductor substrate
US6479328B1 (en) Method of fabricating SOI wafer
JPH0529310A (en) Manufacture of semiconductor device
JPS63228668A (en) Manufacture of semiconductor device
JPS63228619A (en) Manufacture of semiconductor device
KR20010056788A (en) Method for fabricating soi substrate
KR20050068117A (en) Method for fabricating sti of semiconductor device

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100806

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910