DE102006015076B4 - Semiconductor device with SOI transistors and solid-state transistors and a method for manufacturing - Google Patents

Abstract

A method comprising: providing a substrate having a buried insulating layer formed on a first crystalline layer and a second crystalline layer formed on the buried insulating layer; Removing a portion of the second crystalline layer and the buried insulating layer using a mask to expose a portion of the first crystalline layer; and forming a crystalline bulk substrate region by depositing a semiconductor material and recrystallizing the deposited semiconductor material using the exposed area of the substrate as a crystal template and removing excess material of the deposited semiconductor material by chemical mechanical polishing, the mask layer serving as a polishing stop, the recrystallizing the deposited semiconductor material after chemical mechanical polishing takes place.

Description

Field of the present invention

In general, the present invention relates to the fabrication of integrated circuits, and more particularly to the fabrication of field effect transistors in complex circuits having high speed logic circuitry and functional blocks having less speed critical behavior, such as a memory area, for example in the form of a cache memory of a CPU.

Description of the Related Art

The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit arrangement. In general, process technologies are currently being practiced, and for complex circuits such as microprocessors, memory chips, ASICs, and the like, CMOS technology is currently one of the most promising solutions due to its good performance in terms of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i. H. n-channel transistors and p-channel transistors, formed on a substrate having a crystalline semiconductor layer. Regardless of whether an n-channel transistor or a p-channel transistor is considered, a MOS transistor comprises so-called PN junctions formed by an interface of highly doped drain and source regions with an inversely doped or lightly doped channel region. which is arranged between the drain region and the source region. The conductivity of the channel region, i. H. the forward current capability of the conductive channel is controlled by a gate electrode formed over the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region in the construction of a conductive channel due to the application of a suitable control voltage to the gate electrode depends on the dopant concentration, the mobility of the majority carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source region and the drain region , which is also referred to as channel length. Thus, in conjunction with the ability to rapidly establish a conductive channel under the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, due to the latter aspect, the reduction in channel length, and hence the reduction in channel resistance, is an essential design criterion for achieving an increase in integrated circuit processing speed.

In view of the first aspect, in addition to other advantages, the SOI (semiconductor or silicon-on-insulator) architecture has constantly gained a greater degree of importance in the fabrication of MOS transistors due to the characteristics of lower PN parasitic capacitance. Transitions, allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region in which the drain and source regions as well as the channel region are arranged, which is also referred to as a body, is dielectrically encapsulated, which brings distinct advantages, but is also the cause of a number of problems. Unlike the body of bulk substrate devices, which is electrically connected to the substrate, and thus by holding a particular potential to the substrate, holds the bodies of bulk substrate transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential. and thus the potential of the body is typically floating due to the accumulation of minority carriers, which results in a variation of the threshold voltage Vt of the transistors, also referred to as hysteresis. Especially for static memory cells, the threshold variation can lead to significant instabilities of the cell that are not acceptable in terms of the data integrity of the memory cell. Thus, in conventional SOI devices with memory blocks, the variation in the forward current associated with the threshold voltage variations is taken into account by appropriate design measures to provide a sufficiently large forward current range of the SOI transistors in the memory block. Thus, respective SOI transistors in the memory block are typically made with a sufficiently large width to provide the required forward current range, thereby requiring a moderately large amount of chip area. Similarly, in other design measures to eliminate the threshold fluctuations caused by the floating body potential, so-called body contacts are provided, which are a very space consuming solution and therefore not advantageous in view of extremely scaled-up and complex semiconductor devices with extended RAM areas.

The US 2003/0146488 A1 discloses a substrate having SOI regions and bulk substrate regions in each of which MOS transistors are formed. The MOS transistors in the SOI area can be formed so that they form a logic circuit. The MOS transistors in the bulk substrate area are formed to form memory cells and amplifier stages.

The US 6 214 653 B1 discloses a substrate having SOI regions separated by STI regions and a bulk substrate region, as shown in FIGS 6a and 6b is shown. In the bulk substrate area, DRAM memory cells are formed while logic circuits are arranged in the SOI areas. The hybrid substrate may be formed by forming an isolation region and depositing amorphous silicon and then recrystallizing.

The US 2004/0150044 A1 discloses a substrate comprising an SOI region and a non-SOI region. The non-SOI region is formed by blanket deposition of amorphous silicon followed by recrystallization, where monocrystalline silicon is formed only in regions where the amorphous silicon layer is in contact with the underlying semiconductor layer. Regions that do not have contact with the semiconductor layer become polycrystalline upon recrystallization. Subsequently, the polysilicon is selectively removed by polishing or by etching to the crystalline region.

In view of the situation described above, there is a need for an alternative technique that enables the formation of advanced SOI devices in critical functional blocks while avoiding or at least reducing one or more of the problems identified above.

Overview of the invention

In general, the present invention is directed to a technique aimed at reducing the required chip area in modern integrated circuits with time-critical functional circuit blocks constructed on the basis of SOI architecture and further comprising device regions with increased sensitivity for hysteresis effects, e.g. static RAM areas, and the like. To this end, transistors within sensitive device areas, such as cache memory areas or other memory areas and device areas, are provided with less speed critical requirements based on a full substrate-like transistor architecture, while in other areas the SOI architecture continues to be used, thereby providing the ability to substantially To eliminate fluctuations in the threshold voltage of the fully substrate-like components, which would otherwise cause a floating body potential. Consequently, the full-substrate type transistors can be provided with smaller dimensions compared to equivalent SOI transistors, since the on-state current capability of these devices can be set unlike the SOI transistors without the need for hysteresis effects.

The object of the present invention is achieved in particular by the method according to claim 1 or the device according to claim 3.

Brief description of the drawings

Further embodiments of the present invention are defined in the appended claims and will become more apparent from the following detailed description when studied with reference to the accompanying drawings, in which:

1a to 1f schematically show cross-sectional views of a semiconductor device during various manufacturing stages to form SOI-type transistors and solid substrate transistors in adjacent device regions, starting from an SOI substrate and regrowing relevant areas of a semiconductor material based on a crystalline region of the substrate according to examples for explaining partial aspects of Invention;

1g schematically shows a top view of a plurality of transistor elements formed as SOI devices and bulk substrate devices, wherein the transistor width of the bulk substrate devices is reduced compared to equivalent SOI devices according to the present invention;

2a to 2d schematically show cross-sectional views during fabrication of first and second crystalline semiconductor regions for SOI devices and bulk substrate devices in which additional material removal processes, such as CMP, are employed in accordance with illustrative embodiments of the present invention;

Detailed description

In general, the present invention relates to a technique for fabricating SOI transistors and bulk substrate transistors in a common manner on a single substrate, wherein the bulk substrate devices have functional circuit blocks with increased sensitivity to hysteresis effects, ie variations in the threshold voltage of corresponding field effect transistors not connected by carrier accumulation in the transistor body SOI transistors are caused to represent, thereby increasing Component stability is achieved without requiring additional body contacts or a significantly increased transistor width to provide larger forward current ranges. Consequently, in critical circuit blocks, such as CPU cores, combinational logic blocks, and the like, the transistors may be provided in an SOI architecture, thereby achieving the advantages of SOI configuration, ie, high switching speeds due to reduced parasitic capacitances, while on the other hand sensitive component areas, such as static RAM areas, cache memory areas, and the like, a significant reduction in chip area occupied by the circuit as compared to conventional modern overall SOI devices is achieved. For this purpose, respective device regions are fabricated based on highly efficient fabrication processes in which buried insulating layers such as buried oxides and the like having desired properties are formed while additionally forming respective bulk substrate regions.

Related to the 1a to 1g and 2a to 2d Now, examples of aspects of the invention and illustrative embodiments of the present invention will be described in more detail.

1a schematically shows a semiconductor device in cross section in an early stage of manufacture. The component 100 includes a substrate 101 which may represent any suitable substrate, such as a bulk semiconductor substrate, such as a silicon substrate, or other semiconductor substrate. The substrate 101 In some illustrative embodiments, includes a base region 101 which has any configuration and which may be constructed of, for example, an insulating material, a semiconductor material, and the like, while an upper portion 101b may be constructed of a substantially crystalline semiconductor material, such as silicon, silicon / germanium, silicon / carbon, or other suitable semiconductor material. As explained in more detail below, the substrate becomes 101 ie at least the area 101b , as a crystalline template for forming a corresponding crystalline semiconductor region in specified regions of the device 100 used, which in some embodiments receive field effect transistors to form memory areas. Consequently, depending on the desired properties of the corresponding, based on the upper range 101b to be produced semiconductor regions corresponding crystal properties for the area 101b be provided, for example, in terms of crystal orientation, the grid spacing, and the like. If, for example, a special crystal orientation for that based on the upper range 101b is to be prepared to be produced full substrate semiconductor region, a corresponding crystal orientation for the area 101b intended. The component 100 further comprises a buried insulating layer 102 , which may be constructed of any suitable insulating material, such as silicon dioxide, silicon nitride, or other materials having the required characteristics for forming state-of-the-art SOI transistor elements in specific areas of the device 100 provide as described later. Further, a crystalline semiconductor layer 103 on the buried insulating layer 102 formed, wherein the semiconductor layer 103 Has properties that are desirable for SOI transistors on specific areas of the device 100 are to be formed. For example, the material composition, the crystalline orientation, the thickness and the like of the semiconductor layer 103 determined according to the device requirements for modern SOI transistors. In some illustrative embodiments, the semiconductor layer is 103 silicon, which may contain some amount of non-silicon atoms, such as carbon, germanium, and the like, depending on the further process and device requirements.

Typically, the semiconductor device becomes 100 as it is in 1a is made on the basis of well-established methods including disc bonding techniques, modern SIMOX implantation methods, and the like.

1b schematically shows the device 100 in a more advanced manufacturing stage. The component comprises a mask 104 For example, a hardmask layer that is a device area 150s which is intended to serve as an SOI region for the production of corresponding SOI transistors, while a region 150b is exposed, which is to receive a corresponding crystalline semiconductor material, with the substrate 101 is connected, ie at least with the upper area 101b from that. The mask 104 may be constructed of any suitable material, such as silicon nitride, silicon dioxide, or other suitable material compositions that provide sufficient selectivity during subsequent processing. In one illustrative embodiment, an optional etch stop layer is provided 105 , for example in the form of a material having a high etch selectivity with respect to the material of the mask 104 provided to structuring the mask 104 and to improve its removal in a later stage of production. For example, the mask 104 be constructed of silicon nitride, while the optional etch stop layer 105 is formed of silicon dioxide. The mask 104 can be prepared using the following processes. First, the optional etch stop layer 105 if provided, formed by, for example, oxidation and / or deposition based on well established deposition techniques, such as plasma enhanced CVD (chemical vapor deposition) and the like. Thereafter, a material layer, for example, based on plasma enhanced CVD having a required thickness and property as for the mask 104 are desired, deposited. Thereafter, the material layer is patterned on the basis of a lithography process, for example, forming a corresponding resist mask, and the material layer is etched using the resist mask as an etching mask. Thereafter, the resist mask is removed and the device 100 becomes another etching environment 106 for removing an exposed portion of the layer 105 if provided, and for etching through the layers 103 and 102 subjected. For example, in a first step of the etching process 106 , possibly after removal of the optional etch stop layer 105 , through the semiconductor layer 103 etching, wherein selective etching chemistries are used to reliably etch the process in or on the buried insulating layer 102 to stop. In this way, a well controllable etching process over the entire substrate 101 get away. Thereafter, the etch chemistry may be changed to a high etch rate for the buried insulating layer material 102 to reach up to the top 101b to etch. In some illustrative embodiments, also in this etching step, a highly selective etch chemistry relative to the material of the upper region may be used 101b then also good controllability and a very uniform etching result over the entire substrate 101 gives away. In other illustrative embodiments, the etching process 106 performed on the basis of a non-selective etching chemistry, thereby passing through the layer 103 and the layer 102 is etched in a single etching step. In this case, the end of the etching process 106 be determined on the basis of an end point detection or by a predetermined etching time.

1c schematically shows the device 100 after the end of the process sequence described above and after cleaning processes to remove contaminants from the exposed surface 101c of the area 101b to the surface 101c to prepare for a subsequent epitaxial growth process. In this manufacturing phase, the component includes 100 a first crystalline semiconductor region 103s containing the remainder of the crystalline semiconductor layer 103 that is above the rest of the buried insulating layer 102 is formed, which now as 102s is designated, whereby an SOI region in the device 100 is provided, in and above which corresponding SOI transistor elements can be formed.

1d schematically shows the semiconductor device 100 at a more advanced stage of manufacture during a non-inventive selective epitaxial growth process 107 for selectively forming a second crystalline semiconductor region 108 that with the substrate 101 is connected, ie with its upper portion 101b , In the selective epitaxial growth process 107 For example, appropriate process parameters, such as pressure, temperature, precursor gas composition, amount and type of carrier gases, and the like, are set such that material deposition of the semiconductor material is substantially to the exposed region of the region 101b is limited, while essentially no material on the mask 104 is formed. Consequently, divorces during the process 107 Semiconductor material initially on the exposed surface 101c and also takes the crystal structure of the surface 101c at. After a special height of the epitaxially grown material is reached, the process becomes 107 finished, reducing the crystalline area 108 whose properties are essentially determined by the nature of the deposited material and the crystal structure of the underlying upper area 101b are determined. If, for example, a different crystallographic orientation is advantageous for the formation of transistor elements in the second crystalline semiconductor region 108 compared to the first crystalline semiconductor region 103 is, the area can be 101b be provided with the desired crystal orientation. Thus, in some illustrative embodiments, providing the first crystalline semiconductor region 103s and the second crystalline semiconductor region 108 as an SOI region or as a bulk substrate area with provision of different crystal properties of the regions 103s and 108 combined.

In an illustrative embodiment, as well as in FIG 1d is shown before the epitaxial growth process 107 an optional spacer 109 at corresponding exposed side walls of the layer stack 102s . 103s and 104s formed when the influence of the crystalline material of the semiconductor region 103s during the epitaxial growth process 107 is considered inappropriate. In this case, the spacer will 109 based on well-established processes involving the conformal deposition of a suitable spacing material, such as silicon nitride, silicon dioxide, and the like, which is subsequently removed from horizontal surface areas. Thus, the semiconductor region 103s effective during the growth process 107 be isolated.

1e schematically shows the semiconductor device 100 in a more advanced stage of manufacture, in which the mask 104 is removed, causing the first semiconductor region 103s which exposes the SOI area 150s adjacent to the bulk substrate area 150b provided. Removing the mask 104 can be accomplished on the basis of highly selective etching processes, such as those well established for many dielectric materials, such as silicon dioxide, silicon nitride, and the like, with respect to a silicon-based material, when the first and second semiconductor regions 103s . 108 are constructed essentially of crystalline silicon. For example, silicon nitride can be efficiently removed in a very selective manner on the basis of hot phosphoric acid without substantial material removal in the second semiconductor region 108 occurs. In other illustrative embodiments, after removal of the mask 104 Another leveling process is performed when the resulting surface topography of the device 100 considered insufficient for further processing. For example, a CMP (chemical-mechanical polishing) process may occur after removal of the mask 104 which provides a planar surface configuration, as described in more detail below.

1f schematically shows the semiconductor device in a more advanced manufacturing stage. Here are several transistor elements 151s in and on the first semiconductor region 103s are formed, which accordingly represent transistor elements based on an SOI architecture. Furthermore, several transistor elements 151b in and on the second semiconductor region 108 forming a full substrate transistor architecture is provided. The transistors 151s . 151b can be made according to specific design requirements, where, as previously explained, the SOI transistors 151s can be formed on the basis of speed specifications, while the transistors 151b can be manufactured to a high functional stability with less space requirement within the component 100 provide. For this purpose, well-established manufacturing processes are used which incorporate state-of-the-art manufacturing processes to obtain the desired transistor properties. For example, in very demanding applications, stress and strain-inducing process technologies can be incorporated to improve the performance of transistors, particularly SOI transistors 151s , to improve, with different deformation properties for the transistors 151b can be provided. As explained above, for example, the properties of the material of the semiconductor region may be 108 from the properties of the material of the area 103s to further enhance the corresponding transistor characteristics with respect to the functions in the different device areas 150s and 150b to improve. For example, in some applications, it may be advantageous to use the material of the semiconductor region 103s as a deformed silicon material, whereas a corresponding deformation in the semiconductor region 108 not desired. Consequently, in this case, the material of the area 108 being grown as a substantially relaxed semiconductor material, such as silicon, by providing a substantially undeformed semiconductor material in the region 101b of the substrate 101 provided. It should also be noted that the in 1f shown transistor configuration is merely illustrative in nature and that any suitable transistor configuration can be used. For example, as shown, the transistors 1515 and 151b corresponding gate electrodes 152 which, in some embodiments, have dimensions of about 100 nm and significantly less than those on corresponding gate insulating layers 153 are formed, for example, the corresponding layers may differ between the individual transistor elements and also between the transistors 151s and 151b can distinguish. Furthermore, corresponding Dain and source areas 154 be formed, which enclose a channel region within a body region 155 is trained. As previously explained, the body areas 155 the SOI transistors 151s Dielectric due to the provision of appropriate isolation structures 156 and the underlying insulating layer 102s encapsulated. Consequently, carriers that are in the body regions 155 the SOI transistors 151s accumulated, only via leakage currents through the drain and source regions 154 be removed, provided that no body contacts are provided, but require a significant amount of area, and thus may be a degree of fluctuation of the floating potential of the body 155 generated during operation of the transistors. Consequently, a corresponding fluctuation of the respective threshold voltages can be observed, which is also referred to as hysteresis. For time-critical circuit blocks, such as CPU cores, or other time-critical circuits, the corresponding hysteresis effects may be accepted in view of increased circuit speed, or certain countermeasures, such as PN transitions with increased leakage current, may have a larger transistor width to compensate for the loss of on-state current capability Reason of the hysteresis effects, and the like. Unlike the isolated bodies 155 the SOI transistors 151s , are the body areas 155 of the bulk substrate transistors 151b electrically at least with the upper area 101b of substrate 101 due to the direct connection of the semiconductor area 108 to the upper area 101b connected. Thus, similar to a conventional bulk substrate configuration, a desired reference potential 156 , about ground potential, to the body areas 155 of the bulk substrate transistors 151b be created. Therefore, in some illustrative embodiments, when the plurality of bulk substrate transistors 151b Memory cells, such as static RAM cells, may have the respective memory cells of high stability, and the transistor configuration, ie, size in the width direction, may be selected based on the forward current requirements of bulk transistors, rather than the requirements for accommodating large variability the threshold voltage are to be maintained, as would be the case for equivalent SOI transistors, whereby much larger transistor widths would be required to ensure the required stable operation of memory cells in SOI devices. For example, in some demanding applications, up to 30% or more of valuable chip area may be stored in a memory area using a hybrid configuration such as that described in U.S. Pat 1f can be saved as compared to an equivalent SOI device that provides the same performance in time-critical functional blocks, CPU cores, when the memory block is also implemented in SOI technology.

1g schematically shows two inverter pairs, for example, in the field 150s and 150b are formed, for example, the corresponding circuits a static RAM cell 160 can represent. It should be noted that in illustrative embodiments, corresponding RAM cells are substantially in the field 150b be prepared to achieve a significant space savings. Thus, those in the field 150s shown circuit represent a conventional RAM cell when it is formed in a modern SOI device with time-critical function blocks, as for example by the plurality of transistors 151s in 1f are represented.

The RAM cell 160 which are in the bulk substrate area 150b is formed, may be an n-channel transistor 161c and a p-channel transistor 171c comprising a respective inverter formed by a common gate electrode 162 is controlled. Furthermore, the output of the inverter, through the transistors 161c . 171c is formed, with another n-channel transistor 181c which may represent a passgate for a signal received from the inverter 161c . 171c provided. Similarly, transistors can 171d and 161d form a further inverter which is connected to another gate 181d connected is. As previously explained, a corresponding transistor ready, such as 161W or 171W for a given technology, ie a length of the gate 162W , are selected on the basis of the forward current capability necessary for proper operation of the memory cell 160 is required, without taking into account threshold variations due to the bulk configuration of the transistors used for the memory cell 160 be used. In contrast, a corresponding configuration would be found in the SOI area 150s is formed, require a significantly higher chip area, since here the corresponding transistor width 161W . 171W is significantly increased to account for hysteresis effects, requiring a broad range of forward currents. Consequently, according to the invention corresponding memory areas in the device 100 within the component area 150b based on a full substrate transistor architecture, thereby significantly reducing the required area while implementing time critical circuit blocks in the high efficiency SOI architecture.

Related to the 2a to 2d Illustrative embodiments of the present invention will now be described in detail, in which further process methods are described to clearly reduce the requirements for the selectivity of an epitaxial growth process, or to substantially completely avoid an epitaxial growth process.

2a schematically shows a semiconductor device 200 during an early manufacturing stage, which is a substrate 201 comprising, at least in an upper region thereof, a substantially crystalline semiconductor material serving as a crystal template for subsequent processing of the device 200 can serve. With regard to the properties of the substrate 201 Apply the same criteria as before with respect to the substrate 101 are explained. Furthermore, corresponding SOI areas 250s and corresponding full substrate areas 250b in the device 200 provided according to the component and design requirements. That is, depending on the complexity of circuit blocks that are susceptible to hysteresis effects, the size and number of corresponding full substrate regions 250b be adjusted accordingly, while the size and number of corresponding SOI areas 250s can be set according to the respective time-critical circuit blocks. Thus, the lateral sizes of the areas are 250b and possibly 250s in a range of a few 10 μm to 100 or a few 100 μm. How similar for the device 100 is described in the corresponding SOI areas 250s a stack of layers is provided, which is a buried insulating layer 202s , a first crystalline one Semiconductor region 203s and a mask 204 includes. Furthermore, corresponding second crystalline semiconductor regions 208 in the corresponding full-substrate areas 250b be formed, the crystal properties of the area 208 may be the same or different compared to the characteristics of the area 203s as previously related to the areas 103s and 108 is explained.

This in 2a shown component 200 can be made on the basis of substantially the same process method as previously described with respect to the device 100 are described. Thus, after patterning corresponding layers to provide the layer stack in the regions 250s based on techniques as described above, an epitaxial growth process 207 be carried out, wherein, depending on the dimensions of the areas 250s , which can be reduced selectivity for material deposition, so that also continuous material areas 208a on the mask 204 be deposited. Consequently, the requirements for the selectivity of the epitaxial growth process 207 To simplify, a certain amount of material deposition in the form of the radicals 208a be taken into account by performing an additional material removal process, for example based on a selective etch process and / or a CMP process. In some illustrative embodiments, the material may be for the areas 208 during the growth process 207 are formed with an excess height, which is subsequently removed by a selective etching process, whereby the radicals 208a from the corresponding masks 204 be removed to allow a very uniform removal process for the masks 204 to provide in a subsequent process step, as for example, with respect to the device 100 is described. In other illustrative embodiments, the removal of the residues 208a based on a CMP process, where in some illustrative embodiments the mask 204 a stop layer 204a which allows reliable control of the corresponding CMP process when the material of the area 208 and the mask 204 have different removal rates. For example, in some embodiments, the mask 204 an upper area 204b on, for example, is made of silicon dioxide, while the stop layer 204a can be constructed of silicon nitride. Thus, during a polishing process, the residues 208a efficiently removed and also the area 204b is polished efficiently, with the removal rate in the areas 250b due to a greater hardness compared to the material of the layer 204b is reduced. Consequently, after substantially completely removing the area 204b the stop layer 204a for a much lower polishing rate in the areas 250s take care while the material in the area 250b is efficiently polished to a substantially planar surface configuration.

2 B schematically shows the semiconductor device 200 after the end of the process sequence described above. Thus, a substantially planar surface topography is achieved with the remainder of the stop layer 204a which may have a relatively small thickness, for example about 5 nm or less, may then be removed on the basis of a selective etching process, as previously described. Thus, by introducing a further material removal process, such as an additional etch process, a CMP process, or a combination thereof, the conditions regarding the selectivity of the etch process as well as the deposition uniformity across the entire substrate 201 be cleared away, since the height level finally reached the area 208 and thus the finally obtained surface flatness substantially by well controllable deposition processes, such as appropriate Abscheiderezepte for the formation of the stop layer 204 including the areas 204a and 204b , is determined. In this way, an increased level of nonuniformity can be tolerated during the recess etch process. Furthermore, increased flexibility with regard to the process parameters of the deposition process 207 and also for the selection of suitable growth mask materials, since any suitable material can be selected that has a high selectivity during the epitaxial growth process 207 which does not necessarily indicate a desired high etch selectivity for subsequent removal based on the etch process.

2c schematically shows the device 200 a method wherein the deposition process 207 as an epitaxial process with a significantly lower selectivity or no selectivity with respect to the mask 204 is designed. Consequently, the layer becomes 208a through the process 207 formed, with at least one central area 208c within the areas 250b a substantially crystalline structure according to the template of the substrate 201 exhibit. In illustrative embodiments, the layer becomes 208a deposited as a substantially amorphous layer. Regardless of whether the shift 208a in the deposited form has crystalline regions or not, its thickness is selected so that the depressions in the areas 250b be filled to a desired height. Thereafter, a CMP process will be performed to determine the surface topography of the layer 208a in some illustrative embodiments, the layer 208a essentially completely from the corresponding mask layers 204 is removed, which can now serve as a CMP stop layer, as previously explained.

2d schematically shows the semiconductor device 200 after the end of the process sequence described above. Thus, the device comprises the semiconductor region 208 having a substantially planar surface configuration with respect to the areas 250s , wherein the semiconductor regions 208 may be substantially completely amorphous, polycrystalline, or the crystalline region 208c can contain. Then the mask layer becomes 204 removed on the basis of a selective etching process, before or after removal of the mask layer 204 a suitably trained annealing process is performed to cover the areas 208 using the substrate 201 or a part thereof as a crystal template. For example, a heat treatment at temperatures of about 600 to 1100 degrees C may be performed to cover the areas 208 to recrystallize. In other illustrative embodiments, laser-assisted or flash-based bake processes are employed to efficiently provide a corresponding crystal structure in the regions 208 to obtain. Thereafter, the further processing can be continued, as with reference to the 1f and 1g that is, corresponding transistors having an SOI configuration can be used in and on the semiconductor regions 203s while corresponding transistors having a bulk configuration in and on the crystal regions 208 can be formed. Consequently, a corresponding hybrid configuration is achieved with increased process flexibility with regard to forming the bulk substrate regions 250b can be achieved when starting from an SOI substrate.

Thus, the present invention provides a technique that enables the integration of full-substrate transistor architectures, for example, for complex SRAM regions, into otherwise SOI-like circuits with the advantage of high switching speed, while the SRAM full-area type provides significant area savings the absence of hysteresis effects in the memory areas. This is accomplished by forming locally corresponding bulk substrate regions in the substrate by growth method, starting with an SOI substrate. It uses less complex deposition techniques, such as a non-selective epitaxial growth process, deposition of amorphous or polycrystalline material in conjunction with additional material removal processes to provide improved process flexibility.

Claims (5)

Method with: Providing a substrate having a buried insulating layer formed on a first crystalline layer and a second crystalline layer formed on the buried insulating layer; Removing a portion of the second crystalline layer and the buried insulating layer using a mask to expose a portion of the first crystalline layer; and Forming a crystalline bulk substrate region by depositing a semiconductor material and recrystallizing the deposited semiconductor material using the exposed portion of the substrate as a crystal template and removing excess material of the deposited semiconductor material by chemical mechanical polishing, the mask layer serving as a polishing stop, wherein recrystallizing the deposited semiconductor material after the chemical mechanical polishing takes place. The method of claim 1, wherein the crystalline bulk substrate region is a region that receives a plurality of integrated circuit memory cells to be fabricated over the substrate. Semiconductor device comprising: a substrate having a plurality of SOI regions ( 250S ) and a plurality of full substrate areas ( 250B ) between the SOI areas ( 250S ), wherein a lateral size of the solid substrate areas ( 250B ) is in a range of several 10 μm to several 100 μm; several first transistors in the SOI regions ( 250S ); and a plurality of second transistors in the bulk substrate regions ( 250B ). The semiconductor device of claim 3, wherein the plurality of first transistors represent a logic circuit and the plurality of second transistors represent a memory block. The semiconductor device of claim 4, wherein the plurality of second transistors are connected to a common reference potential.

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