JP2003258212A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce an influence of a temperature difference generated from the difference of thermal absorbing efficiencies of an SOI region or an SON region and a silicon region on a substrate even when abrupt heating or cooling is conducted on the substrate, and which can prevent a crystal defect from occurring on the substrate. <P>SOLUTION: The semiconductor device comprises a first semiconductor layer 12 formed via either an insulating film or a cavity on a first region, and a plurality of second semiconductor layers 13 formed on a second region on the semiconductor substrate 11. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SO in which a semiconductor layer is formed in a partial region of a semiconductor substrate via an insulating film.
I (Silicon On Insulator) structure or SON (Silicon On Nothi) in which a semiconductor layer is formed via a cavity region.
ng) structure has a semiconductor device.

[0002]

2. Description of the Related Art Recently, substrates having an SOI structure (hereinafter referred to as S
The OI substrate) is regarded as a promising substrate for forming elements capable of improving the operating speed and reducing the power consumption. In particular, attention has been paid to logic devices for which high speed is required. On the other hand, when a memory device such as a DRAM for storing data or an analog circuit such as a power amplifier is formed on an SOI, there is a problem that the device malfunctions due to a floating effect. Therefore, DRAM and analog circuits are S
It is necessary to form on normal silicon, not on OI, in order to stabilize the operation of the device.

Therefore, in order to mount the logic device and the memory device together on the substrate, the SOI device is previously mounted on the substrate.
Unstructured silicon region and SO with SOI structure
There is a method of using a partial SOI substrate in which the I region is partially formed. Then, it is necessary to form the logic circuit on the SOI region where the buried oxide film exists under the silicon, and to form the DRAM and the analog circuit on the normal silicon region where the buried oxide film does not exist under the silicon.

[0004]

However, since the analog element forming the analog circuit is easily affected by noise, it is better to electrically disconnect it from the logic circuit and the memory circuit. In the partial SOI substrate, the logic circuit is formed on the SOI region and the elements are separated.
Therefore, the logic circuit and the analog circuit are electrically disconnected. However, since the DRAM and the analog circuit formed on the same silicon region are formed adjacent to each other, noise propagation from the DRAM to the analog element becomes a problem.

Further, when an input / output circuit for exchanging signals with another semiconductor device is formed on the SOI region,
Since the SOI region is insulated, a high voltage is applied to the elements themselves that form the input / output circuit, and electrostatic breakdown easily occurs. Further, the semiconductor layer in the SOI region has a side surface covered with SiO 2 for element isolation and a bottom surface formed of SiO 2 having a buried oxide film.
It is covered with 2. Therefore, the element formed on the SOI region has a drawback that the heat generated from the element when driven is poor.

Further, it is necessary to make the junction shallower with the miniaturization of the element. Boron (B), phosphorus (P), arsenic (A
When heat treatment is performed by ion-implanting impurities such as s) into the semiconductor layer, if the heat treatment time is long, the impurities diffuse more than necessary and the junction becomes deep. In order to prevent the junction from becoming deep, it is necessary to rapidly heat and cool the semiconductor layer. A halogen lamp or the like is usually used for the heating, but a temperature difference occurs between the SOI region and the silicon region due to the difference in heat absorption efficiency between them. Due to this temperature difference, crystal defects such as slips may occur on the substrate.

Therefore, the present invention has been made in view of the above-mentioned problems. Even if the substrate is rapidly heated and cooled, the heat absorption efficiency of the SOI region or SON region on the substrate and the silicon region can be improved. An object of the present invention is to provide a semiconductor device capable of reducing the influence of a temperature difference caused by the difference and preventing the occurrence of crystal defects in the substrate.

[0008]

In order to achieve the above object, a semiconductor device according to the present invention comprises a first semiconductor device on a semiconductor substrate.
The region includes a first semiconductor layer formed with one of an insulating film and a cavity interposed, and a plurality of second semiconductor layers formed in a second region on the semiconductor substrate.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment] First, a semiconductor device according to a first embodiment of the present invention will be described. In the first embodiment, SO is provided on one main surface of the semiconductor chip.
An example in which the I region is formed and a plurality of island-shaped silicon regions are formed in this SOI region will be described.

FIG. 1 is a top view showing the structure of the semiconductor device according to the first embodiment.

On the semiconductor chip 11, as shown in FIG. 1, an SOI region 12 and four silicon regions 13 are formed. The SOI region 12 is formed on one main surface of the semiconductor chip 11. The cross-sectional structure of the SOI region 12 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

The silicon region 13 is the SOI region 12
It is surrounded by and is formed in multiple islands. Here, four silicon regions 13 having a predetermined size or less are arranged in the SOI region 12, but the number is not limited to this, and a plurality of other silicon regions may be formed.
The predetermined size and number of the silicon regions 13 are set so that crystal defects such as slips do not occur in the semiconductor chip 11 during the heat treatment.

An analog circuit such as a digital / analog converter (A / D converter) and an amplifier circuit is formed in one of the four silicon regions 13. In the remaining three silicon regions 13,
A semiconductor memory circuit, for example, an 8-megabit DRAM is formed. On the other hand, a logic circuit is formed in the SOI region 12.

In the semiconductor chip having such a structure, by forming a plurality of silicon regions 13 in the SOI region 12 on the semiconductor chip 11, as compared with the case where one silicon region is formed, individual silicon regions are formed. Area 13
Can be made smaller, so that the thermal stress generated in the silicon region 13 during the heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 11 during the heat treatment process can be reduced.

The plurality of silicon regions 13 are arranged in line symmetry with respect to a certain straight line on the semiconductor chip 11. It is preferable that the semiconductor chip 11 is arranged symmetrically with respect to a certain point. This allows
The thermal stress generated in the plurality of silicon regions 13 during the heat treatment can be appropriately dispersed on the semiconductor chip 11. As a result, crystal defects such as slips that occur in the semiconductor chip 11 during the heat treatment process can be reduced.

Further, since the logic circuit is formed in the SOI region 12, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit. Also, S
Since the analog circuit is formed in the silicon region 13 separated by the OI region 12, noise can be prevented from propagating from the logic circuit or DRAM to the analog circuit.

FIG. 2 is a top view of the wafer before the semiconductor chip 11 shown in FIG. 1 is diced.

As shown in FIG. 2, a wafer (semiconductor substrate)
The SOI region 12 is formed on the top. In the SOI region 12, a plurality of silicon regions 13 having a predetermined size are arranged. The predetermined size and number of silicon regions 13 are set so that crystal defects such as slips do not occur on the wafer during the heat treatment. The semiconductor chip 11 shown in FIG. 1 is cut along the broken line shown in FIG.

Next, a method of manufacturing the semiconductor device of the first embodiment will be described.

First, two silicon wafers having a mirror surface of 200 mmφ are prepared. An oxide film having a film thickness of 100 nm is formed on the first wafer in a dry oxygen atmosphere. After that, the surface of the first wafer on which the oxide film is formed and the mirror surface of the second wafer are bonded together, and the two wafers are integrated by heat treatment at 1100 ° C.

Subsequently, one side of the integrated substrate is polished to reduce the thickness of the silicon film existing on the oxide film to 100.
nm. A photoresist film is formed on the silicon film, and a desired pattern is transferred to the photoresist film using an exposure mask. Then, the resist film existing on the internal oxide film to be removed in a later step is peeled off to form a resist pattern. After that, potassium hydroxide (KO
H) is used to etch the silicon film not covered with the resist pattern, and then hydrogen fluoride (H
The buried oxide film is removed by the aqueous solution of F).

Next, by the selective epitaxial growth method,
An epitaxial layer of silicon is formed on the silicon film exposed by removing the oxide film. If necessary, the surface of the silicon epitaxial layer is polished by the CMP method.

By the above-described manufacturing method, as a specific example of the first embodiment, a 6 mm × 6 mm silicon region 13 is formed in the SOI region 12 on the wafer 1 in the vertical and horizontal directions.
Wafers arranged at 0 mm pitch were prepared. further,
This wafer was cut to form a semiconductor chip having a size of 20 mm × 20 mm. This semiconductor chip has 6mm
4 x 6 mm silicon regions 13 are arranged, an A / D converter and an amplifier circuit are formed in one silicon region 13, and an 8-megabit D is formed in the remaining 3 silicon regions 13.
RAM was formed.

As a comparative example of the first embodiment, 12 mm × 12 m in the SOI region 12 on the wafer.
A wafer was prepared in which m silicon regions were arranged in the vertical and horizontal directions at a pitch of 20 mm. Furthermore, this wafer is cut,
A semiconductor chip having a size of 20 mm × 20 mm was formed. In this semiconductor chip, one 12 mm × 12 mm silicon area is arranged, and the A / D is set in one silicon area.
A converter, an amplifier circuit, and a megabit DRAM were formed.

The silicon area (6 mm × 6 mm) is divided into 4
A semiconductor chip 11 having a plurality of silicon chips and a silicon region (12 mm
As a result of comparison of the characteristics with the semiconductor chip 11A having one x12 mm), the results are as follows. Semiconductor chip 1
No. 1 had an S / N ratio of 30 dB, and semiconductor chip 11A had an S / N ratio of 15 dB. That is, the semiconductor chip 11A has an A / D converter in one silicon region,
The deterioration of the characteristics due to the noise that is considered to be generated due to the formation of the amplifier circuit and the DRAM was observed. Also,
In the semiconductor chip 11, the leakage current characteristic was not deteriorated, but in the semiconductor chip 11A, the leakage current characteristic was deteriorated due to a slip that is considered to occur in the heat treatment step (RTA step) in the element forming step.

In the first embodiment, a SON region having a SON structure may be formed instead of the SOI region described above. Even when the SON region is formed, the same effect as when the SOI region is formed can be obtained.
The SON area will be described in detail in a seventh embodiment described later.

As described above, in the first embodiment, even if the substrate is rapidly heated and cooled, the difference in heat absorption efficiency between the SOI region or SON region on the substrate and the silicon region The influence of the temperature difference that occurs can be reduced
It is possible to prevent crystal defects from occurring on the substrate.

[Second Embodiment] Next, a semiconductor device according to a second embodiment of the present invention will be described. In the second embodiment, SO is provided on one main surface of the semiconductor chip.
An example will be described in which an I region is formed, a plurality of silicon regions are formed so as to be surrounded by the SOI region, and a silicon region is also formed around the end portion of the semiconductor chip.

FIG. 3 is a top view showing the structure of the semiconductor device according to the second embodiment.

As shown in FIG. 3, the semiconductor chip 21 has an SOI region 22 and two silicon regions 23A and 23A.
B is formed. The silicon region 23A is arranged around the edge of the semiconductor chip 21 with a predetermined width so as to surround the SOI region 22. The silicon region 23B is S
It is surrounded by the OI region 22 and formed in an isolated island shape, and has a size equal to or smaller than a predetermined size. The predetermined width of the silicon region 23A and the predetermined size of the silicon region 23B are set so that crystal defects such as slips do not occur in the semiconductor chip 21 during the heat treatment. The sectional structure of the SOI region 22 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, in the semiconductor layer,
For example, a silicon film is used.

An input / output circuit (I / O circuit) for inputting / outputting signals to / from the outside is formed in the silicon region 23A.
A semiconductor memory circuit, for example, an 8-megabit DRAM is formed in the silicon region 23B. on the other hand,
A logic circuit is formed in the SOI region 22.

In the semiconductor chip having such a structure, the silicon region 23A is formed around the edge of the semiconductor chip 21.
By forming a silicon region 23B in the SOI region 22 surrounded by the silicon region 23A,
Since the size of each of the silicon regions 23A and 23B can be reduced as compared with the case of forming one silicon region, the thermal stress generated in the silicon regions 23A and 23B during the heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 21 during the heat treatment process can be reduced.

Since the logic circuit is formed in the SOI region 22, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit. Further, by forming the input / output circuit in the silicon region 23A,
It is possible to prevent high voltage from being applied to the elements themselves that configure the input / output circuit, and prevent electrostatic breakdown.

FIG. 4 is a top view of the wafer before the semiconductor chip 21 shown in FIG. 3 is diced.

As shown in FIG. 4, a wafer (semiconductor substrate)
An SOI region 22 is formed on the top. In the SOI region 22, a plurality of silicon regions 23B having a predetermined size are arranged. Further, between the SOI regions 22, silicon regions 23A having a predetermined width are linearly arranged vertically and horizontally. The predetermined width of the silicon region 23A and the predetermined size of the silicon region 23B are set so that crystal defects such as slips do not occur on the wafer during the heat treatment.
The semiconductor chip 21 shown in FIG. 3 is obtained by cutting along the broken line shown in FIG.

As described above, the SOI region 2 on the wafer
By forming a plurality of silicon regions 23B in FIG. 2 and forming linear silicon regions 23A between the SOI regions 22, the size of each of the silicon regions 23A and 23B can be reduced, so that the thermal stress generated during the heat treatment is reduced. Can be relaxed. As a result, crystal defects such as slips that occur on the wafer during the heat treatment process can be reduced.

The method of manufacturing the semiconductor device according to the second embodiment is the same as that of the first embodiment, and the description thereof is omitted.

Next, a semiconductor device of a modification of the second embodiment will be described.

FIG. 5 is a top view showing the structure of the semiconductor device of the first modification of the second embodiment.

On the semiconductor chip 21, as shown in FIG. 5, an SOI region 22, a silicon region 23A and two silicon regions 23B are formed. Silicon region 23
A indicates the semiconductor chip 21 so as to surround the SOI region 22.
Is arranged with a predetermined width around the end of the. Each of the two silicon regions 23B is surrounded by the SOI region 22 and formed in an isolated island shape, and has a size equal to or smaller than a predetermined size. The predetermined width of the silicon region 23A and the predetermined size of the silicon region 23B are set so that crystal defects such as slips do not occur in the semiconductor chip 21 during the heat treatment. The sectional structure of the SOI region 22 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate.
Here, for example, a silicon film is used for the semiconductor layer.

An input / output circuit (I / O circuit) for inputting / outputting signals to / from the outside is formed in the silicon region 23A.
An analog circuit, for example, a digital / analog converter (A / D converter) or an amplifier circuit is formed in one of the two silicon regions 23B. A semiconductor memory circuit, for example, an 8-megabit DRAM is formed in the remaining silicon region 23B. On the other hand, a logic circuit is formed in the SOI region 22.

In the semiconductor chip having such a structure, the silicon region 23A is formed around the edge of the semiconductor chip 21.
Is formed and two silicon regions 23B are formed in the SOI region 22 surrounded by the silicon region 23A, compared to the case where one silicon region is formed. Since the size can be reduced, thermal stress generated in the silicon regions 23A and 23B during heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 21 during the heat treatment process can be reduced.

Since the logic circuit is formed in the SOI region 22, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit. Also, S
An analog circuit is formed in one silicon region 23B separated by the OI region 22, and D is formed in the other silicon region 23B.
Since RAM is formed, logic circuits and DRAM
Therefore, it is possible to prevent the propagation of noise to the analog circuit.

Although two SOI regions 23B are shown here, the present invention is not limited to this, and a plurality of other S regions may be used.
The OI region may be formed.

FIG. 6 is a top view showing the structure of the semiconductor device of the second modification of the second embodiment.

On the semiconductor chip 21, as shown in FIG. 6, an SOI region 22, a silicon region 23A and four silicon regions 23B are formed. Silicon region 23
A indicates the semiconductor chip 21 so as to surround the SOI region 22.
Is arranged with a predetermined width around the end of the. Each of the four silicon regions 23B is surrounded by the SOI region 22 and is formed in an isolated island shape, and has a size equal to or smaller than a predetermined size. The predetermined width of the silicon region 23A and the predetermined size of the silicon region 23B are set so that crystal defects such as slips do not occur in the semiconductor chip 21 during the heat treatment. The sectional structure of the SOI region 22 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate.
Here, for example, a silicon film is used for the semiconductor layer.

An input / output circuit (I / O circuit) for inputting / outputting a signal to / from the outside is formed in the silicon region 23A.
An analog circuit, for example, a digital / analog converter (A / D converter) and an amplifier circuit are formed in one silicon region 23B among the four silicon regions 23B. A semiconductor memory circuit, for example, an 8-megabit DRAM is formed in the remaining three silicon regions 23B. On the other hand, a logic circuit is formed in the SOI region 22.

In the semiconductor chip having such a structure, the silicon region 23A is formed around the edge of the semiconductor chip 21.
Is formed and four silicon regions 23B are formed in the SOI region 22 surrounded by the silicon region 23A, as compared with the case where one silicon region is formed. Since the size can be reduced, thermal stress generated in the silicon regions 23A and 23B during heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 21 during the heat treatment process can be reduced.

Further, since the logic circuit is formed in the SOI region 22, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit. Also, S
An analog circuit is formed in one silicon region 23B separated by the OI region 22, and the remaining three silicon regions 23B are formed.
Since the DRAM is formed in B, the logic circuit and D
It is possible to prevent the propagation of noise from the RAM to the analog circuit.

Although the four SOI regions 23B are shown here, the present invention is not limited to this.
The OI region may be formed.

In addition, in the second embodiment and the modified example, a SON region having a SON structure may be formed instead of the SOI region described above. Even when the SON region is formed, the same effect as when the SOI region is formed can be obtained.

As described above, in the second embodiment and the modified example, even if the substrate is rapidly heated and cooled, the heat absorption efficiency between the SOI region or SON region on the substrate and the silicon region is high. It is possible to reduce the influence of the temperature difference caused by the difference between the two, and it is possible to prevent crystal defects from occurring on the substrate.

[Third Embodiment] Next, a semiconductor device according to a third embodiment of the present invention will be described. In the third embodiment, an example will be described in which a silicon region is formed on one main surface of a semiconductor chip, and an island-shaped SOI region is formed so as to be surrounded by the silicon region.

FIG. 7 is a top view showing the structure of the semiconductor device according to the third embodiment.

As shown in FIG. 7, the semiconductor chip 31 has four SOI regions 32 and silicon regions 33 formed therein. The silicon region 33 is formed on one main surface of the semiconductor chip 31. The SOI region 32 is surrounded by the silicon region 33 and is formed in a plurality of isolated islands. Here, four SOI regions 32 having a predetermined size or smaller are arranged in the silicon region 33, but the number of the SOI regions 32 is not limited to this, and a plurality of other silicon regions may be formed. The predetermined size of the SOI region 32 is set so that crystal defects such as slips do not occur in the semiconductor chip 31 during heat treatment. The sectional structure of the SOI region 32 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

In the silicon region 33, a semiconductor memory circuit, for example, an 8-megabit DRAM, an analog circuit, and a signal input / output circuit are formed. On the other hand, 4 SO
A logic circuit is formed in the I region 32.

In the semiconductor chip having such a configuration, by forming a plurality of SOI regions 32 in the silicon region 33 on the semiconductor chip 31, as compared with the case where one SOI region is formed, individual SOI regions are formed. Since the size of the region 32 can be reduced, thermal stress generated in the SOI region 32 during heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 31 during the heat treatment process can be reduced.

The plurality of SOI regions 32 are arranged in line symmetry with respect to a certain straight line on the semiconductor chip 31. It is preferable that the semiconductor chip 31 is arranged symmetrically with respect to a certain point on the semiconductor chip 31. This allows
The thermal stress generated in the plurality of SOI regions 32 during the heat treatment is
It can be dispersed appropriately on the semiconductor chip 31. As a result, crystal defects such as slips that occur in the semiconductor chip 31 during the heat treatment process can be reduced.

Since the logic circuit is formed in the SOI region 32, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit.

Next, a semiconductor device of a modification of the third embodiment will be described.

FIG. 8 is a top view showing the structure of the semiconductor device of the first modification of the third embodiment.

On the semiconductor chip 31, as shown in FIG. 8, two SOI regions 32 and a silicon region 33 are formed. The SOI region 32 is surrounded by the silicon region 33 and is formed in a plurality of isolated islands. here,
In the silicon region 33, the SOI region 3 of a predetermined size or smaller
Two 2 are arranged. The predetermined size of the SOI region 32 is set so that crystal defects such as slips do not occur in the semiconductor chip 31 during heat treatment. The sectional structure of the SOI region 32 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

In the silicon region 33, a semiconductor memory circuit, for example, an 8-megabit DRAM is formed.
On the other hand, logic circuits are formed in the four SOI regions 32.

In the semiconductor chip having such a structure, as described above, by forming a plurality of SOI regions 32 in the silicon region 33 on the semiconductor chip 31,
Compared to the case of forming one SOI region, each SO
Since the size of the I region 32 can be reduced, it is possible to reduce the size of the S region during heat treatment.
The thermal stress generated in the OI region 32 can be relaxed.
As a result, crystal defects such as slips that occur in the semiconductor chip 31 during the heat treatment process can be reduced.

Since the logic circuit is formed in the SOI region 32, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit.

FIG. 9 is a top view showing the structure of the semiconductor device of the second modification of the third embodiment.

As shown in FIG. 9, an SOI region 32 and silicon regions 33 and 33A are formed in the semiconductor chip 31. The SOI region 32 is a silicon region 33, 3
It is formed in an island shape surrounded by 3A and has a size equal to or smaller than a predetermined size. The predetermined size of the SOI region 32 is set so that crystal defects such as slips do not occur in the semiconductor chip 31 during heat treatment. This SO
The sectional structure of the I region 32 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

The silicon region 33 is the semiconductor chip 3
The silicon region 33A is arranged around the edge of the first region 1 and has a predetermined width.
It is located between and.

An input / output circuit for inputting / outputting a signal to / from the outside is formed in the silicon region 33, and a semiconductor memory circuit, for example, an 8-megabit DRAM is formed in the silicon region 33A in the broken line. On the other hand, a logic circuit is formed in the SOI region 32.

In the semiconductor chip having such a structure, the silicon region 33 is formed around the edge of the semiconductor chip 31.
By forming 33A and forming the SOI region 32 of a predetermined size in the region surrounded by the silicon regions 33, 33A, the thermal stress generated during the heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 31 during the heat treatment process can be reduced.

Since the logic circuit is formed in the SOI region 32, the parasitic capacitance of the wiring can be reduced. This facilitates speeding up of the logic circuit.

In the third embodiment and the modified example, the SON region having the SON structure may be formed instead of the SOI region described above. Even when the SON region is formed, the same effect as when the SOI region is formed can be obtained.

As described above, in the third embodiment and the modified example, even if the substrate is rapidly heated and cooled, the heat absorption efficiency between the SOI region or SON region and the silicon region on the substrate is high. It is possible to reduce the influence of the temperature difference caused by the difference between the two, and it is possible to prevent crystal defects from occurring on the substrate.

[Fourth Embodiment] Next, a semiconductor device according to a fourth embodiment of the present invention will be described. Also in the fourth embodiment, an example will be described in which a silicon region is formed on one main surface of a semiconductor chip and a plurality of SOI regions are formed so as to be surrounded by the silicon region. Further, an example will be described in which, in the selective epitaxial growth step for forming the silicon region, the problem of selective collapse in which silicon is deposited on the SOI region other than the silicon region is dealt with.

FIG. 10 is a top view showing the structure of the semiconductor device according to the fourth embodiment.

As shown in FIG. 10, the semiconductor chip 41 has four isolated SOI regions 42 and silicon regions 43.
Are formed. The silicon region 43 is formed on one main surface of the semiconductor chip 41. SOI area 42
Are surrounded by the silicon region 43 and are formed in a plurality of isolated islands. Here, four SOI regions 42 each having a predetermined size or less are arranged in the silicon region 43, but the number is not limited to this, and a plurality of other silicon regions may be formed. The predetermined size of the SOI region 42 is set so that crystal defects such as slips do not occur in the semiconductor chip 41 during heat treatment. The sectional structure of the SOI region 42 is such that a semiconductor layer is formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

The semiconductor chip 41 having such a structure
Then, in the silicon region 43 on the semiconductor chip 41, S
Since the size of each SOI region 42 can be made smaller by forming the OI region 42 in a plurality of island shapes than in the case of forming one SOI region, the SOI region can be reduced during the heat treatment.
The thermal stress generated in the region 42 can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 41 during the heat treatment process can be reduced.

Next, when the SOI region and the silicon region are formed on the semiconductor chip, the selective epitaxial growth process is used for forming the silicon region. When this selective epitaxial growth method is used, a problem of selective collapse occurs in that silicon is deposited on an insulating film such as an oxide film or a nitride film on the SOI region. Hereinafter, a semiconductor device that has dealt with the problem of the selective collapse will be described. First, the manufacturing method by the selective epitaxial growth method will be described, and then the method for preventing the selective collapse will be described.

First, the natural oxide film existing on the surface of the silicon substrate is removed by, for example, pretreatment using an aqueous solution of hydrogen fluoride. After that, the wafer is introduced into the epitaxial growth apparatus. Then, heat treatment is performed in a non-oxidizing atmosphere such as a hydrogen atmosphere. This heat treatment is a heat treatment for cleaning the surface of the silicon substrate before the epitaxial growth, and the silicon oxide film on the surface of the substrate is completely removed at this stage. Therefore, this heat treatment is preferably performed in a non-oxidizing atmosphere such as a hydrogen atmosphere. As the heat treatment condition, for example, 1000 ° C., 10 Torr, and 3 minutes are used.

Subsequently, epitaxial growth of silicon is continuously performed. Si as a growth gas / carrier gas
H2Cl2 (DCS) and HCl / H2 gas are used. When the silicon oxide film or the silicon nitride film is patterned on the silicon substrate, DCS and HCl can be used to selectively form the epitaxial silicon film only on the silicon substrate. At this time,
Epitaxial growth is performed at a temperature of 900 ° C. or higher.

Next, the results of investigating selective collapse when the above-mentioned selective epitaxial growth method is performed will be described below.

FIGS. 11, 12, and 13 are diagrams in which the number of silicon grains generated on the SOI region after the epitaxial growth is monitored. The vertical axis represents the number of silicon particles, and the larger the number of silicon particles, the greater the selective collapse. The surface of the SOI region is a silicon oxide film or a silicon nitride film.

In general, selective epitaxial growth is possible on both a silicon oxide film and a silicon nitride film, but with respect to selectivity, the use of a silicon nitride film is more likely to cause selective collapse. Therefore, in this experiment, the experiment was conducted under more severe conditions using the silicon nitride film.

First, the selectivity of a wafer whose one main surface was covered with a silicon nitride film was evaluated.
FIG. 11 shows the dependency of the number of silicon particles on the flow rate of hydrochloric acid. From this, it is understood that the lower the flow rate of hydrochloric acid, the lower the selectivity.

Next, FIG. 12 shows the dependence of the number of silicon grains on the size of the SOI region under the condition of poor selectivity. From this, it is understood that the selectivity can be secured (the selectivity is not deteriorated) by reducing the area of the isolated SOI region. A square is used for the shape of the SOI region.

Next, FIG. 13 shows the dependence of the number of silicon grains on the shape of the SOI region. The shape of the SOI region is rectangular and the area is constant. And, the change of the number of silicon grains is shown when the length of the short side of the rectangle is changed. From this, it is understood that the selectivity can be secured by shortening the length of the short side of the rectangle even if the area of the SOI region is constant. That is, by shortening the length of the side of the SOI region, selectivity can be secured for a larger SOI area. The length of the short side of the rectangle of the SOI area is 10 m
When it is m or less, the number of silicon particles is less than or equal to the allowable number.
From this, consider a square in which the side length of the SOI region is 10 mm. Since the distance from the center of the SOI region (the point where the diagonal lines intersect) to the end of the SOI region is 5 mm, if at least a part of the silicon region for epitaxial growth is provided within a radius of 5 mm from a certain point on the SOI region. It can be seen that selective collapse in selective epitaxial growth can be suppressed.

It is considered that the phenomenon that the selective collapse in the selective epitaxial growth can be suppressed is as follows. FIG. 14 is a diagram schematically showing a cross section of the SOI region 42 and the silicon region 43 in the semiconductor chip 41.

As shown in FIG. 14, a silicon film 46 is formed on a silicon substrate 44 via an insulating film 45. A silicon nitride film 47 having an opening 47A is formed on the silicon film 46. In the opening 47A of the silicon nitride film 47, silicon 48 which is being epitaxially grown is deposited on the silicon substrate 44.

In the state shown in FIG. 14, the silicon grains 49A deposited on the silicon nitride film 47 (SOI region) by selective epitaxial growth have a distance from the opening (silicon region) 47A which is equal to or less than a predetermined distance X. ,
It moves toward the opening 47A and is absorbed by the silicon 48. On the other hand, the silicon particles 49B having Y that is longer than X from the opening 47A have a long distance from the opening 47A, and thus are unlikely to be absorbed by the silicon 48 even if they move toward the opening 47A. , Stays on the silicon nitride film 47 as it is and grows. The selective collapse is caused by the silicon grains 49B.

As described above, in the fourth embodiment, even if the substrate is rapidly heated and cooled, the temperature difference caused by the difference in the heat absorption efficiency between the SOI region and the silicon region on the substrate is reduced. The influence can be reduced and the occurrence of crystal defects on the substrate can be prevented.

Further, by providing at least a part of the epitaxial silicon region within a predetermined distance X (5 mm) from a certain point on the SOI region, selective collapse in the selective epitaxial growth can be suppressed.

In this embodiment, an example in which a plurality of SOI regions are formed has been shown. However, even when one SOI region is formed, a predetermined distance X ( By providing at least a part of the epitaxial silicon region within 5 mm, selective collapse in selective epitaxial growth can be suppressed.

In the fourth embodiment, a SON region having a SON structure may be formed instead of the SOI region described above. Even when the SON region is formed, the same effect as when the SOI region is formed can be obtained.

[Fifth Embodiment] Next, a semiconductor device according to a fifth embodiment of the present invention will be described. In the fifth embodiment, SO is provided on one main surface of the semiconductor chip.
An example in which the I region is formed and a plurality of silicon regions are formed so as to be surrounded by the SOI region will be described. Further, an example will be described in which, in the selective epitaxial growth step for forming the silicon region, the problem of selective collapse in which silicon is deposited on the SOI region other than the silicon region is dealt with.

FIG. 15 is a top view showing the structure of the semiconductor device according to the fifth embodiment.

In the semiconductor chip 51, as shown in FIG. 15, an SOI region 52 and four isolated silicon regions 53 are formed.
Are formed. The SOI region 52 is the semiconductor chip 5
1 is formed on one main surface. This SOI area 52
The sectional structure of is a semiconductor layer formed on an insulating film on a semiconductor substrate. Here, for example, a silicon film is used for the semiconductor layer.

The silicon region 53 is the SOI region 52.
It is surrounded by and is formed in multiple islands. Here, four silicon regions 53 having a predetermined size or less are arranged in the SOI region 52, but the present invention is not limited to this, and a plurality of other silicon regions may be formed.
The predetermined size of the silicon region 53 is set so that crystal defects such as slips do not occur in the semiconductor chip 51 during heat treatment.

The semiconductor chip 51 having such a configuration
Then, by forming the silicon region 53 in the SOI region 52 on the semiconductor chip 51 in the form of a plurality of islands, the size of each silicon region 53 can be made smaller than in the case of forming one silicon region. Therefore, the thermal stress generated in the silicon region 53 during the heat treatment can be relaxed. As a result, crystal defects such as slips that occur in the semiconductor chip 51 during the heat treatment process can be reduced.

Based on the countermeasure against the selective collapse described in the fourth embodiment, at least a part of the silicon region 53 is provided within a predetermined distance X (5 mm) from a certain point on the SOI region 52. . As a result, it is possible to suppress selective collapse in the selective epitaxial growth.

In this embodiment, an example in which a plurality of silicon regions are formed is shown, but the silicon region is 1
Even in the case of individual formation, selective collapse in selective epitaxial growth can be suppressed by providing at least a part of the epitaxial silicon region within a predetermined distance X (5 mm) from any point on the SOI region.

The constitution for suppressing the selective collapse in the selective epitaxial growth is the same as the above-mentioned first to third
It is also applicable to the embodiment.

In the fifth embodiment, a SON region having a SON structure may be formed instead of the SOI region described above. Even when the SON region is formed, the same effect as when the SOI region is formed can be obtained.

[Sixth Embodiment] Next, a semiconductor device according to a sixth embodiment of the present invention will be described. In the sixth embodiment, an example in which elements are respectively formed in the silicon region and the SOI region provided in the semiconductor device of the first to fifth embodiments will be described with reference to sectional views.

FIG. 16 is a sectional view showing the structure of the semiconductor device according to the sixth embodiment.

As shown in FIG. 16, the silicon substrate 60 is partially provided with an SOI structure. That is, the insulating layer 61 is formed on a partial region of the silicon substrate 60, and the semiconductor layer 62 is formed on the insulating layer 61. The insulating layer 61 is, for example, a silicon oxide film, and hereinafter, the insulating layer 61 is referred to as a BOX (Buried Oxide) layer. The semiconductor layer 62 is, for example, a silicon layer, and the semiconductor layer 62 is hereinafter referred to as an SOI layer. A semiconductor layer, for example, a silicon layer 63 is provided on the other region of the silicon substrate 60.

As described above, B is formed on the silicon substrate 60.
The region where the SOI structure including the OX layer 61 and the SOI layer 62 is provided is the SOI region, and the region where the silicon layer 63 is provided on the silicon substrate 60 is the silicon region.
The SOI layer 62 is formed by the BOX layer 61.
It is electrically separated from 0. On the other hand, the silicon layer 63
Are electrically connected to the silicon substrate 60.

Element regions surrounded by the element isolation region STI and the element isolation region 64 are provided in the silicon region and the SOI region, respectively. The element isolation region 64 in the SOI region and the element isolation region STI at the boundary between the silicon region and the SOI region are at least B.
It is provided so as to reach the OX layer 61. Also, SO
The element isolation region 64 in the I region is, for example, the well-known LOCO.
It is formed by an S (Local Oxidation of Silicon) method or the like. A device isolation region STI at the boundary between the silicon region and the SOI region, and a device isolation region ST in the silicon region
I is formed by forming a trench and then burying an insulating film in the trench.

A MOS transistor TR1 is formed in the element region provided in the silicon region, and a MOS transistor TR2 is formed in the element region provided in the SOI region.
Are formed. MOS transistors TR1 and TR
Reference numeral 2 has a source region, a drain region, and a gate electrode, respectively. The source region 65A and the drain region 66A of the MOS transistor TR1 are formed on the surface of the silicon layer 63 so as to be separated from each other. MOS
The gate electrode 67A of the transistor TR1 is formed on the silicon layer 63 between the source region 65A and the drain region 66A with the gate insulating film 68A interposed therebetween.

The source region 65B and the drain region 66B of the MOS transistor TR2 are formed on the surface of the SOI layer 62 so as to be separated from each other. The gate electrode 67B of the MOS transistor TR2 has a source region 65.
A gate insulating film 68B is formed on the SOI layer 62 between B and the drain region 66B. In addition, M
The source region 65B and the drain region 66B of the OS transistor TR2 are provided so that the bottoms thereof reach the BOX layer 61.

According to the semiconductor device of the sixth embodiment, the thermal stress generated in the silicon region and the SOI region can be relaxed, as described in the first to fifth embodiments. As a result, crystal defects such as slips that occur in the semiconductor device can be reduced.

[Seventh Embodiment] Next, a semiconductor device according to a seventh embodiment of the present invention will be described. In the seventh embodiment, a semiconductor device having a SON (Silicon On Nothing) structure will be described. The SON structure is a structure in which a silicon layer is provided on the cavity region.
The SON structure will be described in detail later. In the sixth embodiment, the example in which the element is provided in the SOI region having the SOI structure is shown, but in the seventh embodiment, the element is provided in the SON region having the SON structure instead of the SOI region. An example in which is provided is shown.

FIG. 17 is a sectional view showing the structure of the semiconductor device according to the seventh embodiment.

As shown, the semiconductor device has a silicon region and a SON region. Silicon region and SO
In the N region, element regions electrically isolated from each other by the element isolation region STI are provided. MOS transistors TR1 and TR3 are provided in these element regions, respectively.

Since the structure of the silicon region is the same as that of the sixth embodiment, the description thereof is omitted. Here, SO is used.
Only the N region will be described.

As shown in FIG. 17, the silicon substrate 60 is partially provided with a SON structure. That is, the cavity region 71 is provided on a partial region of the silicon substrate 60. A semiconductor layer 72 is provided on the silicon substrate 60 with the cavity region 71 interposed. Semiconductor layer 72
Is a silicon layer, for example, and the semiconductor layer 72 is hereinafter referred to as a SON layer. Thus, on the silicon substrate 60,
The region where the SON structure including the cavity region 71 and the SON layer 72 is provided is the SON region. The SON layer 72 is electrically separated from the silicon substrate 60 by the cavity region 71. Therefore, the same effect as the SOI structure having the BOX layer 61 between the silicon substrate 60 and the SOI layer 62 as described in the sixth embodiment can be obtained.

An element isolation region STI is formed in the SON region.
An element region surrounded by the element isolation region 73 is provided. The element isolation region 73 in the SON region is formed so as to reach the silicon substrate 60. The element isolation region 73 is the element isolation region ST in the silicon region.
I and the element isolation region STI at the boundary between the silicon region and the SON region are formed by a manufacturing process different from the manufacturing process.

A MOS transistor TR3 is provided in the element region provided in the SON region. MO
The S transistor TR3 includes a source region, a drain region,
And a gate electrode. MOS transistor TR
The source region 74B and the drain region 75B of No. 3 are provided so as to reach the cavity region 71. The gate electrode 76B of the MOS transistor TR3 is provided on the SON layer 72 between the source region 74B and the drain region 75B with the gate insulating film 77B interposed. Since the structure of the MOS transistor TR1 provided in the element region in the silicon region is the same as that of the sixth embodiment, description thereof will be omitted.

As described above, even in the semiconductor device having the SON structure in a partial region of the silicon substrate, the first
~ The same effect as that described in the fifth embodiment can be obtained.

According to the semiconductor device of the seventh embodiment, the thermal stress generated in the silicon region and the SON region can be relaxed as in the sixth embodiment. As a result, crystal defects such as slips that occur in the semiconductor device can be reduced.

Further, each of the above-described embodiments is
Not only can it be carried out alone, but it is also possible to carry out it in an appropriate combination.

Furthermore, each of the embodiments described above includes inventions at various stages, and inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment. Is also possible.

As described above, according to the embodiment of the present invention, even if the substrate is rapidly heated and cooled, the difference in heat absorption efficiency between the SOI region or the SON region on the substrate and the silicon region. It is possible to provide a semiconductor device which can reduce the influence of the temperature difference caused by the above and can prevent the occurrence of crystal defects in the substrate.

[0124]

As described above, according to the embodiment of the present invention, even if the substrate is rapidly heated and cooled,
It is possible to provide a semiconductor device that can reduce the influence of the temperature difference caused by the difference in heat absorption efficiency between the SOI region or SON region on the substrate and the silicon region, and can prevent crystal defects from occurring on the substrate.

[Brief description of drawings]

FIG. 1 is a top view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a top view of a wafer before the semiconductor device shown in FIG. 1 is diced.

FIG. 3 is a top view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a top view of a wafer before the semiconductor device shown in FIG. 3 is diced.

FIG. 5 is a top view showing a configuration of a semiconductor device of a first modification example of the second embodiment.

FIG. 6 is a top view showing a configuration of a semiconductor device of a second modification example of the second embodiment.

FIG. 7 is a top view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a top view showing a configuration of a semiconductor device of a first modified example of the third exemplary embodiment.

FIG. 9 is a top view showing a configuration of a semiconductor device of a second modified example of the third exemplary embodiment.

FIG. 10 is a top view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing the dependency of the number of particles on the flow rate of hydrochloric acid and the epitaxial growth temperature in the semiconductor device of the fourth embodiment.

FIG. 12 is a diagram showing the dependence of the number of particles on the size of the SOI region under conditions of poor selectivity in the semiconductor device of the fourth embodiment.

FIG. 13 is a diagram showing the dependency of the number of particles on the shape of the SOI region in the semiconductor device of the fourth embodiment.

FIG. 14 is a sectional view schematically showing a section of an SOI region and a silicon region in the semiconductor device of the fourth embodiment.

FIG. 15 is a top view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 16 is a sectional view showing a structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.

[Explanation of symbols]

11 ... Semiconductor chip 11A ... Semiconductor chip 12 ... SOI area or SON area 13 ... Silicon area 21 ... Semiconductor chip 22 ... SOI area or SON area 23A ... Silicon area 23B ... Silicon area 31 ... Semiconductor chip 32 ... SOI area or SON area 33 ... Silicon area 41 ... Semiconductor chip 42 ... SOI area or SON area 43 ... Silicon area 44 ... Silicon substrate 45 ... Insulating film 46 ... Silicon film 47 ... Silicon nitride film 47A ... Opening 48 ... Silicon 49A ... Silicon grains 49B ... Silicon grains 51 ... Semiconductor chip 52 ... SOI area or SON area 53 ... Silicon area 60 ... Silicon substrate 61 ... Insulating layer (BOX layer) 62 ... Semiconductor layer (SOI layer) 63 ... Silicon layer 64 ... Element isolation region 65A ... Source area 65B ... Source area 66A ... Drain region 66B ... Drain region 67A ... Gate electrode 67B ... Gate electrode 68A ... Gate insulating film 68B ... Gate insulating film 71 ... Cavity area 72 ... Semiconductor layer (SON layer) 73 ... Element isolation region 74B ... Source area 75B ... Drain region 76B ... Gate electrode 77B ... Gate insulating film TR1 ... MOS transistor TR2 ... MOS transistor TR3 ... MOS transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8242 H01L 27/10 671C 27/04 27/04 A 27/08 331 21/76 A 27/10 461 29/78 626C 27/108 29/786 (72) Inventor Ichiro Mizushima 8 Shinsitata-cho, Isogo-ku, Yokohama-shi, Kanagawa Incorporated company Toshiba Yokohama Works (72) Inventor Kei Yamada Shin-Sugita-cho, Isogo-ku, Yokohama-shi, Kanagawa No. 8 Incorporation company Toshiba Yokohama Works (72) Inventor Yumune Yushin, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa 8 Incorporation Company Toshiba Yokohama Works (72) Inventor Shinichi Nitta Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa No. 8 F Company in Toshiba Corporation, Yokohama Works (reference) 5F032 AA06 AA13 AA34 AA82 AC02 BA08 CA17 CA23 DA16 DA24 DA33 DA71 DA74 5F038 AV06 BH13 BH19 CA05 CA06 CA08 CA14 CD13 DF01 DF03 DF05 DF12 EZ04 EZ06 EZ11 EZ14 EZ15 EZ16 EZ17 EZ20 5F048 AA04 AA07 AB01 AB03 AB06 AB07 AC01 BA09 BA16 BG06 BG14 5F083 AD00 GA27 HA02 LA25 ND0325

Claims (18)

[Claims] 1. A first semiconductor layer formed in a first region on a semiconductor substrate with an insulating film or a cavity interposed therebetween, and a plurality of plurality of semiconductor layers formed in a second region on the semiconductor substrate. A semiconductor device comprising: a second semiconductor layer. 2. A plurality of first semiconductor layers formed in the first region on the semiconductor substrate with one of an insulating film and a cavity interposed, and a second region formed on the semiconductor substrate. A semiconductor device comprising: a second semiconductor layer. 3. The semiconductor according to claim 1, wherein at least a part of the second semiconductor layer is arranged within a radius of 5 mm from a point on the first semiconductor layer. apparatus. 4. The semiconductor device according to claim 1, wherein each of the plurality of second semiconductor layers is surrounded by the first semiconductor layer. 5. The semiconductor device according to claim 2, wherein each of the plurality of first semiconductor layers is surrounded by the second semiconductor layer. 6. A logic circuit is formed on the first semiconductor layer, and at least one of a memory element, an analog element, and a signal input / output circuit is formed on the second semiconductor layer. The semiconductor device according to claim 1. 7. The one of the plurality of second semiconductor layers, one of the second semiconductor layers is arranged so as to surround the first semiconductor layer. Semiconductor device. 8. The semiconductor device according to claim 1, wherein the plurality of second semiconductor layers are arranged point-symmetrically with respect to a point on the semiconductor substrate. 9. The semiconductor device according to claim 1, wherein the plurality of second semiconductor layers are arranged in line symmetry with respect to a certain straight line passing through the semiconductor substrate. 10. A semiconductor device having a plurality of the semiconductor devices according to claim 1 laid out. 11. The semiconductor according to claim 1, wherein one of the plurality of second semiconductor layers is formed at an end of the semiconductor substrate. apparatus. 12. A semiconductor device having a plurality of the semiconductor devices according to claim 11 laid out. 13. The semiconductor device according to claim 2, wherein the plurality of first semiconductor layers are arranged point-symmetrically with respect to a certain point on the semiconductor substrate. 14. The semiconductor device according to claim 2, wherein the plurality of first semiconductor layers are arranged in line symmetry with respect to a straight line passing through the semiconductor substrate. 15. A rectangular first semiconductor layer formed on a semiconductor substrate with one of an insulating film and a cavity interposed, and the first semiconductor layer at an end portion on the semiconductor substrate. A second semiconductor layer formed so as to surround the first semiconductor layer, wherein the second semiconductor layer overhangs a corner portion of the rectangular first semiconductor layer. 16. The semiconductor device according to claim 1, wherein the area of the second semiconductor layer is larger than the area of the first semiconductor layer. 17. The semiconductor device according to claim 1, wherein the second semiconductor layer is a semiconductor layer deposited by an epitaxial growth method. 18. A first semiconductor layer formed in a first region on a semiconductor substrate with an insulating film or a cavity interposed therebetween, and a second region formed in a second region on the semiconductor substrate. The semiconductor device according to claim 1, wherein at least a part of the second semiconductor layer is arranged within a radius of 5 mm from any point on the first semiconductor layer.