US20010006830A1 - Method of producing a semiconductor device - Google Patents

Method of producing a semiconductor device Download PDF

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Publication number
US20010006830A1
US20010006830A1 US09/737,056 US73705600A US2001006830A1 US 20010006830 A1 US20010006830 A1 US 20010006830A1 US 73705600 A US73705600 A US 73705600A US 2001006830 A1 US2001006830 A1 US 2001006830A1
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Prior art keywords
conductor tracks
cleaning process
wiring terminals
housing configuration
semiconductor chip
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US6436731B2 (en
Inventor
Achim Neu
Volker Strutz
Rudiger Uhlmann
Stephan Wege
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Polaris Innovations Ltd
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a method of producing a semiconductor device in which a semiconductor chip with wiring terminals is applied to a component of a housing configuration which contains organic, silicon-containing material, and in which the conductor tracks are subsequently connected to the wiring terminals.
  • a semiconductor chip with wiring terminals is in this case generally packaged in a housing and mounted on a printed-circuit board.
  • a semiconductor device is disposed in a housing configuration in accordance with a so-called fine-pitch ball grid array (FBGA) housing configuration, which is based in particular on the so-called beam-lead-bonding technique.
  • FBGA fine-pitch ball grid array
  • This type of housing configuration can be advantageously used in particular in the case of semiconductor memory devices based on Rambus technology with comparatively high clock-pulse rates, since in particular line inductances are relatively low because of the specific configuration of the arrangement.
  • the FBGA housing configuration also referred to as an FBGA package, usually contains a semiconductor chip with terminals for the electrical connection to the terminals of the printed-circuit board and a flexible printed-circuit board (also referred to as interposer) with a substrate and conductor tracks applied to it.
  • a flexible printed-circuit board also referred to as interposer
  • the semiconductor chip During the mounting of the semiconductor chip, it is initially attached to the spacers with or without an additional layer of adhesive (so-called die bonding), whereby a narrow intermediate space is produced between the semiconductor chip and the interposer.
  • the spacers and adhesive are formed of organic silicon-containing materials.
  • parts of the conductor tracks are bent from the interposer onto the wiring terminals of the semiconductor chip and are welded on there with the aid of heat, pressure and ultrasound.
  • the requirements for the quality of the welded contacts are relatively high, in order that the functionality of the semiconductor device is ensured even under high electrical demands, for example at high clock-pulse rates.
  • the semiconductor device For attaching the semiconductor chip on the spacers, the semiconductor device is usually subjected to a process at a correspondingly elevated process temperature, in which the silicon-containing material of the layer of adhesive and the spacers is released. This then generally adheres to the surfaces of the conductor tracks and/or wiring terminals of the semiconductor chip as a contaminant layer. This impairs the contact quality during the later connection of the conductor tracks to the wiring terminals of the semiconductor chip.
  • a method of producing a semiconductor device includes providing a housing configuration formed of conductor tracks and a component formed of an organic, silicon-containing material connected to the conductor tracks.
  • a semiconductor chip having wiring terminals is permanently connected to the component of the housing configuration.
  • the conductor tracks and/or the wiring terminals are then subjected to a cleaning process, for removing any of silicon-containing material adhering to a surface of either the conductor tracks or the wiring terminal.
  • the conductor tracks are then connected, in an electrically conducting manner, to the wiring terminals.
  • the semiconductor chip is applied to the component of the housing configuration that contains the organic silicon-containing material and is permanently connected to the component of the housing configuration.
  • the conductor tracks for the electrical connection of the semiconductor chip and/or the wiring terminals of the semiconductor chip are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. Following this, the conductor tracks are connected in an electrically conducting manner to the wiring terminals of the semiconductor chip.
  • the cleaning process ensures that any contaminant layer of silicon-containing material is removed. Such a contaminant layer may be located on the conductor tracks and/or the wiring terminals of the semiconductor chip.
  • the substrate and the conductor tracks located on it can be additionally cleaned before the semiconductor chips are applied.
  • An advantageous development of the invention provides that the conductor tracks are additionally subjected to the cleaning process described before the semiconductor chip is applied to the component of the housing configuration.
  • This cleaning step is provided for any contaminants of silicon-containing material that are already present before the semiconductor chip is applied to be removed before it is applied. This can additionally improve the contact quality during the later connection of the conductor tracks.
  • the cleaning process has a plasma etching process.
  • the etching removal required to eliminate a contaminant layer takes place by dry etching by use of atoms or molecules of a gas and/or by bombardment of the surface to be etched with ions, photons or electrons.
  • the etching process may, for example, be of a physical or chemical type.
  • a chemical plasma etching process may be used for example.
  • a chemical etching reaction takes place between excited particles of a reaction gas and atoms of the surface to be etched. Consequently, silicon-containing material adhering to a surface is chemically converted and detached from the surface by the reaction gas.
  • a precondition for such a cleaning operation is in this case the formation of a gaseous volatile reaction product that can be carried away in the gaseous state.
  • the reaction gas has a fluorine component.
  • excited fluorine atoms from the plasma form with the atoms of the surface contaminated with silicon-containing material the volatile reaction product SiF 4 .
  • CF 4 , SF 6 or NF 3 may be used for example as the reaction gas.
  • undesired byproducts may occur and be deposited on the surfaces to be cleaned.
  • carbon compounds to be deposited for example polymer deposits
  • reaction products that are produced by the cleaning process being applied are also formed when SF 6 or NF 3 is used. These reaction products may be caused, for example, by the cleaning by the reaction gas also affecting surrounding material that is not to be cleaned of contaminants.
  • a further cleaning process is carried out, removing a reaction product that is adhering to a surface and is produced by the cleaning process being applied for eliminating silicon-containing material.
  • This further cleaning process contributes to making sure that undesired byproducts of the preceding plasma cleaning do not contribute to impairing the contact quality.
  • this further cleaning process may be carried out repeatedly, in order to improve the cleaning result further.
  • the further cleaning process advantageously has a plasma etching process.
  • the step of forming the housing configuration as a fine-pitch ball grid array (FBGA) housing configuration.
  • FBGA fine-pitch ball grid array
  • FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor device in an FBGA housing configuration according to the invention.
  • FIG. 2 is a schematic representation of a configuration of an apparatus for a plasma etching process.
  • FIG. 1 a cross section of a semiconductor device 1 in a so-called fine-pitch ball grid array (FBGA) housing configuration.
  • FBGA fine-pitch ball grid array
  • a flexible printed-circuit board 7 an interposer
  • a semiconductor chip 2 is attached by wiring terminals 3 on the spacers 5 with or without an additional layer of adhesive.
  • the spacers 5 and the layer of adhesive possibly used are formed of organic silicon-rubber-containing materials (for example polymers).
  • the interposer 7 is connected by soldering beads 6 for example to a printed-circuit board.
  • FIG. 2 Represented in FIG. 2 is a schematic configuration of a device for a plasma etching process.
  • a suitable reaction gas 10 is fed to the previously almost evacuated reaction chamber 14 .
  • Oxygen with a 5-20% addition of the reaction gas CF 4 serves for example as the reaction gas 10 .
  • a plasma 12 is produced from the reaction gas 10 in a chamber 13 . Excited atoms or molecules diffuse out of the plasma 12 to the semiconductor device 1 (particle jet 16 ), which is applied to a substrate 15 , and react chemically with the atoms of the contaminated surfaces.
  • a precondition for the etching is the formation of volatile reaction products, which can be sucked away by a pump 11 .
  • reaction products that are adhering to the surfaces and are produced for example by the reaction gas CF 4 being applied are removed.
  • the plasma cleaning process applied once again for this purpose uses, for example, a reaction gas 10 containing pure oxygen. This reacts with the carbon compounds adhering to the surfaces to form carbon dioxide or carbon monoxide (CO 2 , CO), which is pumped away by the pump 11 .

Abstract

A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.

Description

    BACKGROUND OF THE INVENTION Field of the Invention
  • The present invention relates to a method of producing a semiconductor device in which a semiconductor chip with wiring terminals is applied to a component of a housing configuration which contains organic, silicon-containing material, and in which the conductor tracks are subsequently connected to the wiring terminals. [0001]
  • Integrated semiconductor devices are used in various applications. A semiconductor chip with wiring terminals (so-called bond pads) is in this case generally packaged in a housing and mounted on a printed-circuit board. For example, a semiconductor device is disposed in a housing configuration in accordance with a so-called fine-pitch ball grid array (FBGA) housing configuration, which is based in particular on the so-called beam-lead-bonding technique. This type of housing configuration can be advantageously used in particular in the case of semiconductor memory devices based on Rambus technology with comparatively high clock-pulse rates, since in particular line inductances are relatively low because of the specific configuration of the arrangement. [0002]
  • The FBGA housing configuration, also referred to as an FBGA package, usually contains a semiconductor chip with terminals for the electrical connection to the terminals of the printed-circuit board and a flexible printed-circuit board (also referred to as interposer) with a substrate and conductor tracks applied to it. Applied in turn to the interposer there are usually a plurality of spacers (also referred to as nubbins). [0003]
  • During the mounting of the semiconductor chip, it is initially attached to the spacers with or without an additional layer of adhesive (so-called die bonding), whereby a narrow intermediate space is produced between the semiconductor chip and the interposer. To conform to the customary configuration requirements, the spacers and adhesive are formed of organic silicon-containing materials. In a subsequent production step (so-called lead bonding), parts of the conductor tracks (so-called leads) are bent from the interposer onto the wiring terminals of the semiconductor chip and are welded on there with the aid of heat, pressure and ultrasound. The requirements for the quality of the welded contacts are relatively high, in order that the functionality of the semiconductor device is ensured even under high electrical demands, for example at high clock-pulse rates. [0004]
  • For attaching the semiconductor chip on the spacers, the semiconductor device is usually subjected to a process at a correspondingly elevated process temperature, in which the silicon-containing material of the layer of adhesive and the spacers is released. This then generally adheres to the surfaces of the conductor tracks and/or wiring terminals of the semiconductor chip as a contaminant layer. This impairs the contact quality during the later connection of the conductor tracks to the wiring terminals of the semiconductor chip. [0005]
    • SUMMARY OF THE INVENTION
  • It is accordingly an object of the invention to provide a method of producing a semiconductor device that overcomes the above-mentioned disadvantages of the prior art methods, in which a semiconductor chip is applied to a silicon-containing component of a housing configuration, and which ensures relatively high contact quality during the later connection of the semiconductor tracks to the wiring terminals of the semiconductor chip. [0006]
  • With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a semiconductor device. The method includes providing a housing configuration formed of conductor tracks and a component formed of an organic, silicon-containing material connected to the conductor tracks. A semiconductor chip having wiring terminals is permanently connected to the component of the housing configuration. The conductor tracks and/or the wiring terminals are then subjected to a cleaning process, for removing any of silicon-containing material adhering to a surface of either the conductor tracks or the wiring terminal. The conductor tracks are then connected, in an electrically conducting manner, to the wiring terminals. [0007]
  • According to the invention, the semiconductor chip is applied to the component of the housing configuration that contains the organic silicon-containing material and is permanently connected to the component of the housing configuration. The conductor tracks for the electrical connection of the semiconductor chip and/or the wiring terminals of the semiconductor chip are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. Following this, the conductor tracks are connected in an electrically conducting manner to the wiring terminals of the semiconductor chip. The cleaning process ensures that any contaminant layer of silicon-containing material is removed. Such a contaminant layer may be located on the conductor tracks and/or the wiring terminals of the semiconductor chip. [0008]
  • This eliminates contaminants that are present before the semiconductor chip is applied and contaminants that are caused by the semiconductor chip being applied. The described sequence of the method steps ensures that, during the connection of the conductor tracks, good contact quality is made possible by clean surfaces. [0009]
  • If other provisions are made in the production of the semiconductor device, for example there is already a method step for cleaning devices of, for example, carbon compounds, it can be modified in a way according to the invention. With the cleaning process described, the substrate and the conductor tracks located on it (the interposer) and also the spacers located on that can be additionally cleaned before the semiconductor chips are applied. [0010]
  • An advantageous development of the invention provides that the conductor tracks are additionally subjected to the cleaning process described before the semiconductor chip is applied to the component of the housing configuration. This cleaning step is provided for any contaminants of silicon-containing material that are already present before the semiconductor chip is applied to be removed before it is applied. This can additionally improve the contact quality during the later connection of the conductor tracks. [0011]
  • In an advantageous embodiment of the invention, the cleaning process has a plasma etching process. The etching removal required to eliminate a contaminant layer takes place by dry etching by use of atoms or molecules of a gas and/or by bombardment of the surface to be etched with ions, photons or electrons. The etching process may, for example, be of a physical or chemical type. [0012]
  • For etching away entire surfaces of layers, a chemical plasma etching process may be used for example. In this, a chemical etching reaction takes place between excited particles of a reaction gas and atoms of the surface to be etched. Consequently, silicon-containing material adhering to a surface is chemically converted and detached from the surface by the reaction gas. A precondition for such a cleaning operation is in this case the formation of a gaseous volatile reaction product that can be carried away in the gaseous state. [0013]
  • It is favorable in this case that the reaction gas has a fluorine component. For example, excited fluorine atoms from the plasma form with the atoms of the surface contaminated with silicon-containing material the volatile reaction product SiF[0014] 4.
  • CF[0015] 4, SF6 or NF3 may be used for example as the reaction gas. In the case of the cleaning process with the plasma etching process described, undesired byproducts may occur and be deposited on the surfaces to be cleaned. For example, when CF4 is used, an increased tendency for carbon compounds to be deposited (for example polymer deposits) can be observed. However, reaction products that are produced by the cleaning process being applied are also formed when SF6 or NF3 is used. These reaction products may be caused, for example, by the cleaning by the reaction gas also affecting surrounding material that is not to be cleaned of contaminants.
  • It is therefore favorable that, after the cleaning process, a further cleaning process is carried out, removing a reaction product that is adhering to a surface and is produced by the cleaning process being applied for eliminating silicon-containing material. This further cleaning process contributes to making sure that undesired byproducts of the preceding plasma cleaning do not contribute to impairing the contact quality. In a way similar to the preceding cleaning process for the removal of silicon-containing material, this further cleaning process may be carried out repeatedly, in order to improve the cleaning result further. [0016]
  • Since the mode of operation of the further cleaning process is similar to the mode of operation of the preceding cleaning process for the removal of silicon-containing material, the further cleaning process advantageously has a plasma etching process. [0017]
  • In accordance with an added feature of the invention, there is the step of forming the housing configuration as a fine-pitch ball grid array (FBGA) housing configuration. [0018]
  • In accordance with a concomitant feature of the invention, there is the step of providing the component of the FBGA housing configuration with a spacer. [0019]
  • Other features which are considered as characteristic for the invention are set forth in the appended claims. [0020]
  • Although the invention is illustrated and described herein as embodied in a method of producing a semiconductor device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0021]
  • The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. [0022]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor device in an FBGA housing configuration according to the invention; and [0023]
  • FIG. 2 is a schematic representation of a configuration of an apparatus for a plasma etching process. [0024]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In all the figures of the drawing, sub-features and integral parts that correspond to one another bear the same reference symbol in each case. Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown a cross section of a [0025] semiconductor device 1 in a so-called fine-pitch ball grid array (FBGA) housing configuration. For producing the housing configuration, a flexible printed-circuit board 7 (an interposer), formed of a substrate 8 and conductor tracks 4 and to which a plurality of spacers 5 are applied, is used. In the so-called die bonding, a semiconductor chip 2 is attached by wiring terminals 3 on the spacers 5 with or without an additional layer of adhesive. This produces a narrow intermediate space between the semiconductor chip 2 and the interposer 7. To conform to the configuration requirements, the spacers 5 and the layer of adhesive possibly used are formed of organic silicon-rubber-containing materials (for example polymers). Additionally, the interposer 7 is connected by soldering beads 6 for example to a printed-circuit board.
  • In the production step of the so-called lead bonding, parts of the conductor tracks [0026] 4 (leads) are bent from the interposer 7 onto the wiring terminals, also called bond pads 3, of the semiconductor chip 2 and are welded on there with the aid of heat, pressure and ultrasound. In the interests of good contact quality, the mutually touching surfaces of the conductor tracks 4 and the bond pads 3 should in particular be free of silicon-containing contaminants. These may be produced in the method of producing the semiconductor device 1 when the semiconductor chip 2 is applied to the spacers 5 and is permanently bonded to them. Before the conductor tracks 4 are connected in an electrically conducting manner to the bond pads 3 of the semiconductor chip 2, the conductor tracks 4 and/or the bond pads 3 are subjected to a cleaning process, in which any silicon-containing contaminants are eliminated.
  • Represented in FIG. 2 is a schematic configuration of a device for a plasma etching process. For etching, a [0027] suitable reaction gas 10 is fed to the previously almost evacuated reaction chamber 14. Oxygen with a 5-20% addition of the reaction gas CF4 serves for example as the reaction gas 10. A plasma 12 is produced from the reaction gas 10 in a chamber 13. Excited atoms or molecules diffuse out of the plasma 12 to the semiconductor device 1 (particle jet 16), which is applied to a substrate 15, and react chemically with the atoms of the contaminated surfaces. A precondition for the etching is the formation of volatile reaction products, which can be sucked away by a pump 11.
  • In a further cleaning process, reaction products that are adhering to the surfaces and are produced for example by the reaction gas CF[0028] 4 being applied are removed. The plasma cleaning process applied once again for this purpose uses, for example, a reaction gas 10 containing pure oxygen. This reacts with the carbon compounds adhering to the surfaces to form carbon dioxide or carbon monoxide (CO2, CO), which is pumped away by the pump 11.

Claims (10)

We claim:
1. A method of producing a semiconductor device, which comprises the steps of:
providing a housing configuration formed of conductor tracks and a component formed of an organic, silicon-containing material connected to the conductor tracks;
permanently connecting a semiconductor chip having wiring terminals to the component of the housing configuration;
subjecting at least one of the conductor tracks and the wiring terminals to a cleaning process, for removing any of the silicon-containing material adhering to a surface of at least one of the conductor tracks and the wiring terminals; and
connecting the conductor tracks in an electrically conducting manner to the wiring terminals.
2. The method according to
claim 1
, which comprises performing a plasma etching process during the cleaning process.
3. The method according to
claim 2
, which comprises using a reaction gas which chemically converts the silicon-containing material adhering to the surface of at least one of the conductor tracks and the wiring terminals and detaches it from the surface during the plasma etching process.
4. The method according to
claim 3
, which comprises providing the reaction gas with a fluorine component.
5. The method according to
claim 4
, which comprises using a gas selected from the group consisting of CF4, SF6 and NF3 as the reaction gas.
6. The method according to
claim 1
, which comprises after the cleaning process, carrying out a further cleaning process for removing a reaction product which is adhering to the surface and is produced by the cleaning process being applied.
7. The method according to
claim 6
, which comprises performing a plasma etching process during the further cleaning process.
8. The method according to
claim 1
, which comprises subjecting the conductor tracks to an additional cleaning process before the semiconductor chip is connected to the component of the housing configuration.
9. The method according to
claim 1
, which comprises forming the housing configuration as a fine-pitch ball grid array (FBGA) housing configuration.
10. The method according to
claim 9
, which comprises providing the component of the FBGA housing configuration with a spacer.
US09/737,056 1999-12-14 2000-12-14 Method of producing a semiconductor device comprising a cleaning process for removing silicon-containing material Expired - Lifetime US6436731B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
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KR101225238B1 (en) 2010-02-22 2013-01-22 가부시끼가이샤 히다찌 하이테크 인스트루먼츠 Plasma cleaning method

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN102164457A (en) * 2010-02-22 2011-08-24 株式会社日立高新技术仪器 Plasma cleaning method
KR101225238B1 (en) 2010-02-22 2013-01-22 가부시끼가이샤 히다찌 하이테크 인스트루먼츠 Plasma cleaning method

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