JP2005340288A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2005340288A
JP2005340288A JP2004153629A JP2004153629A JP2005340288A JP 2005340288 A JP2005340288 A JP 2005340288A JP 2004153629 A JP2004153629 A JP 2004153629A JP 2004153629 A JP2004153629 A JP 2004153629A JP 2005340288 A JP2005340288 A JP 2005340288A
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insulating film
film
interlayer insulating
low
manufacturing
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Naoki Ogawa
直樹 小川
Isato Iwamoto
勇人 岩元
Masafumi Muramatsu
真文 村松
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Sony Corp
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Sony Corp
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<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for reforming the surface of the damage layer of an interlayer insulating film, which is formed by dry etching, especially removing moisture remaining in a low dielectric constant insulating film (Low-k film) being the interlayer insulating film and restoring damage by plasma. <P>SOLUTION: The manufacturing method of the semiconductor device has a process for patterning the interlayer insulating film 4 formed in the semiconductor substrate 2 by dry etching, a process for cleaning the semiconductor substrate 2 having the interlayer insulating film 4, a process for drying the semiconductor substrate 2 having the interlayer insulating film 4 under reduced pressure, and a process for reforming the surface of the damage layer 10 in the interlayer insulating film 4 by dry etching. Drying under reduced pressure and surface reforming are continuously performed without exposing to atmosphere. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造方法、特に層間絶縁膜のダメージ層の表面改質を行う半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that performs surface modification of a damaged layer of an interlayer insulating film.

LSI(大規模半導体集積回路)の微細化により、素子の高速化、低消費電力化が進んでいる。その際、配線形成においては、配線抵抗の低減と配線容量を確保するために、銅(Cu)を用いる配線や配線間絶縁膜(以下、層間絶縁膜という)に、一般的にLow−k膜と呼ばれている低誘電率絶縁膜を用いることが検討されている。また、近年ではLow−k膜の低誘電率化も進んでおり、多孔質素材の開発が加速されている。
この銅による配線形成では、ダマシン(Damascene)法を用いて、先ずLow−k膜に配線形状の溝を形成し、その溝をバリアメタル及び銅メッキで埋め込んだ後、表面の余分な銅をCMP(化学機械研磨)により除去して形成することが一般的な方法である。
その際、Low−k膜に残ったドライエッチング時の加工残渣物を除去するために、薬液及び純水等のリンス処理を組み合わせて洗浄する。その洗浄の後に枚葉式装置では、乾燥処理としてスピンによる振り切りでの乾燥を行った後にバリアメタル及び銅の埋め込みを行っている。
With the miniaturization of LSIs (Large Scale Semiconductor Integrated Circuits), the speed of elements and the reduction of power consumption are progressing. At that time, in the formation of wiring, in order to reduce wiring resistance and secure wiring capacity, a low-k film is generally used for wiring using copper (Cu) or an insulating film between wirings (hereinafter referred to as an interlayer insulating film). The use of an insulating film having a low dielectric constant, which is called, has been studied. In recent years, low-k films have been made to have a low dielectric constant, and the development of porous materials has been accelerated.
In this wiring formation using copper, a damascene method is used to first form a wiring-shaped groove in the low-k film, and the groove is filled with a barrier metal and copper plating, and then excess copper on the surface is CMPed. It is a general method to remove and form by (chemical mechanical polishing).
At this time, in order to remove processing residues remaining in the low-k film during dry etching, cleaning is performed in combination with a rinsing process such as a chemical solution and pure water. In the single wafer apparatus after the cleaning, the barrier metal and copper are embedded after drying by spin-off as a drying process.

配線形成工程における洗浄処理では、Low−k膜の多孔質構造に起因してLow−k膜表面に残留する水分は洗浄時の乾燥処理により除去されるが、膜内部に洗浄時の水分が吸収されてしまうと除去することが困難になる。このような水分がLow−k膜中に残留することにより絶縁膜の耐圧特性の劣化や誘電率の上昇が問題となっている。
また、ドライエッチングによる加工時でのLow−k膜のプラズマダメージによりLow−k膜終端での分子構造を破壊させることによる膜へのダメージで、誘電率の上昇を発生させており、素子の性能に悪影響を及ぼしている。
In the cleaning process in the wiring formation process, moisture remaining on the surface of the Low-k film due to the porous structure of the Low-k film is removed by the drying process at the time of cleaning, but the moisture at the time of cleaning is absorbed inside the film. Once removed, it becomes difficult to remove. Since such moisture remains in the low-k film, the breakdown voltage characteristics of the insulating film are deteriorated and the dielectric constant is increased.
In addition, due to plasma damage of the low-k film at the time of processing by dry etching, damage to the film due to destruction of the molecular structure at the end of the low-k film causes an increase in the dielectric constant, and the device performance Has an adverse effect.

近年、枚葉式洗浄装置の基板乾燥技術としては、減圧処理する乾燥方法が考案されている。例えば、特許文献1のように、基板表面を加熱し基板より外部へ水蒸気として気化させ、その後、気化した水分に対して減圧処理を行う事により基板から除去する方法である。この減圧乾燥方式を用いることにより、Low−k膜中に残留する水分の除去は可能となってきている。
また、ドライエッチングによるLow−k膜のダメージを抑制するために、例えば特許文献2には、ダメージが入った層に対してHMDS(ヘキサメチルジシラザン)等での処理を行うことでシリル化することによりダメージ層を改質する方法が提案されている。
In recent years, as a substrate drying technique for a single wafer cleaning apparatus, a drying method for reducing the pressure has been devised. For example, as in Patent Document 1, the substrate surface is heated and vaporized as water vapor from the substrate to the outside, and then removed from the substrate by subjecting the vaporized water to a reduced pressure treatment. By using this reduced pressure drying method, it is possible to remove moisture remaining in the low-k film.
In order to suppress damage to the Low-k film due to dry etching, for example, in Patent Document 2, silylation is performed by performing a treatment with HMDS (hexamethyldisilazane) or the like on a damaged layer. Thus, a method for modifying the damaged layer has been proposed.

特開2003−174007号公報JP 2003-174007 A 特開2000−188331号公報JP 2000-188331 A

しかしながら、上述したこれらの方法では、以下のような問題点を有している。
(1) 減圧乾燥方式を用いるだけでは、Low−k膜中に残留する水分の除去は可能であるが、しかし、Low−k膜のプラズマによるダメージ層の分子構造を回復するような変化を何も与えないことから、不可能である。よって、誘電率の上昇は避けられなくなっている。
(2) ダメージ層へのHMDS処理によるシリル化は、一般的にダメージ層には親水性の性質のため吸湿し易いため、この親水性のダメージ層から大気中の水分などを吸着させLow−k膜中へ取り込ませてしまう。そのため、この方法を用いる場合は導入する工程が限られてしまう。
(3) Low−k膜にダメージ層が存在し、そのダメージ層からLow−k膜中に取り込まれた水分を保持させたまま、HMDS処理によるダメージ層のシリル化を行った場合、このダメージ層の膜の性質が改質されると疎水性に変化する。そのため、Low−k膜中に残留する水分を外部に脱離させることが難しくなってしまう。
However, these methods described above have the following problems.
(1) The moisture remaining in the low-k film can be removed only by using the reduced-pressure drying method. However, what is the change that restores the molecular structure of the damaged layer by the plasma of the low-k film? Is also impossible because Therefore, an increase in dielectric constant is inevitable.
(2) Since silylation by HMDS treatment to a damaged layer is generally easy to absorb moisture due to the hydrophilic nature of the damaged layer, moisture in the atmosphere is adsorbed from this hydrophilic damaged layer to Low-k It will be taken into the membrane. Therefore, when this method is used, the steps to be introduced are limited.
(3) When a damaged layer is present in the Low-k film and the damaged layer is silylated by HMDS treatment while retaining moisture taken into the Low-k film from the damaged layer, this damaged layer When the film properties are modified, it changes to hydrophobic. Therefore, it becomes difficult to desorb moisture remaining in the Low-k film to the outside.

本発明は、上述の点に鑑み、ドライエッチングによってできた層間絶縁膜のダメージ層の表面改質、特に、層間絶縁膜である低誘電率絶縁膜(Low−k膜)内部に残留する水分の除去とプラズマによるダメージを回復させる半導体装置の製造方法を提供するものである。   In view of the above points, the present invention is directed to surface modification of a damaged layer of an interlayer insulating film made by dry etching, in particular, moisture remaining in a low dielectric constant insulating film (Low-k film) that is an interlayer insulating film. The present invention provides a method of manufacturing a semiconductor device that recovers damage caused by removal and plasma.

本発明に係る半導体装置の製造方法は、半導体基板に形成した層間絶縁膜をドライエッチングでパターニングする工程と、層間絶縁膜を有する半導体基板を洗浄する工程と、層間絶縁膜を有する半導体基板を減圧乾燥する工程と、ドライエッチングによる層間絶縁膜のダメージ層の表面改質を行う工程とを有し、これら減圧乾燥と表面改質を大気に晒さずに連続して行うことを特徴とする。   A method of manufacturing a semiconductor device according to the present invention includes a step of patterning an interlayer insulating film formed on a semiconductor substrate by dry etching, a step of cleaning a semiconductor substrate having an interlayer insulating film, and a pressure reduction of the semiconductor substrate having an interlayer insulating film. The method includes a drying step and a step of modifying the surface of the damaged layer of the interlayer insulating film by dry etching, and the reduced-pressure drying and the surface modification are continuously performed without being exposed to the atmosphere.

前記減圧乾燥処理と表面改質処理は、同一の装置内で行うことができる。
あるいは、上記減圧乾燥処理と表面改質処理は、それぞれ異なる装置で行うことができる。
The reduced-pressure drying treatment and the surface modification treatment can be performed in the same apparatus.
Alternatively, the reduced-pressure drying process and the surface modification process can be performed by different apparatuses.

前記表面改質に使用する材料としては、シラザン系の化合物を用いることが好ましい。
前記シラザン系化合物としては、Si−n結合及びCH3の結合からなる化合物であることが好ましい。
層間絶縁膜としては、低誘電率絶縁膜を用いることが好ましい。
As a material used for the surface modification, it is preferable to use a silazane compound.
The silazane compound is preferably a compound composed of a Si-n bond and a CH3 bond.
As the interlayer insulating film, a low dielectric constant insulating film is preferably used.

本発明の半導体装置の製造方法では、半導体基板に形成した層間絶縁膜をドライエッチングでパターニングし、洗浄処理した後、基板乾燥として減圧中で加熱処理する、いわゆる減圧乾燥することにより、層間絶縁膜内部に吸収された水分が除去される。この減圧乾燥後に、大気中に晒さずに連続してドライエッチングによる層間絶縁膜のダメージ層の表面改質を行うことにより、大気中の水分を吸着することなく、ダメージ層の表面改質が行われる。   In the method of manufacturing a semiconductor device of the present invention, an interlayer insulating film formed on a semiconductor substrate is patterned by dry etching, washed, and then heat-treated under reduced pressure as substrate drying. Moisture absorbed inside is removed. After drying under reduced pressure, the surface of the damaged layer of the interlayer insulating film is continuously modified by dry etching without being exposed to the air, so that the surface of the damaged layer is modified without adsorbing moisture in the air. Is called.

減圧乾燥と表面改質の処理を同一装置内で連続して行うことにより、層間絶縁膜を有する半導体基板を大気に触れさせずに処理することができ、基板乾燥と表面改質との間での水分の再吸収が起こらない。
減圧乾燥と表面改質とをそれぞれ異なる装置で連続して行う場合は、両装置間に層間絶縁膜を有する半導体基板を大気に触れさせないバッファ部が設けられる。この場合にも、基板乾燥と表面改質との間での水分の再吸収が起こらない。
By continuously performing the drying under reduced pressure and the surface modification in the same apparatus, the semiconductor substrate having the interlayer insulating film can be processed without being exposed to the atmosphere. Reabsorption of water does not occur.
When the drying under reduced pressure and the surface modification are successively performed by different apparatuses, a buffer unit that prevents the semiconductor substrate having an interlayer insulating film from being exposed to the atmosphere is provided between both apparatuses. Also in this case, reabsorption of moisture does not occur between substrate drying and surface modification.

表面改質に使用する材料としてシラザン系化合物、好ましくはSi−n結合及びCH3の結合からなる化合物を用いることにより、層間絶縁膜のダメージ層がシリル化する。   By using a silazane compound, preferably a compound composed of a Si-n bond and a CH3 bond, as the material used for the surface modification, the damaged layer of the interlayer insulating film is silylated.

本発明の半導体装置の製造方法によれば、ドライエッチングによる層間絶縁膜のパターニング及び洗浄処理の後に、大気に晒さずに連続して減圧乾燥による層間絶縁膜内の水分除去と、ダメージ層の表面改質が行われるので、水分に起因する層間絶縁膜の耐圧劣化や誘電率の上昇を抑制することができる。よって、半導体装置の歩留りが向上し、半導体装置の信頼性を向上した半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device of the present invention, after patterning and cleaning the interlayer insulating film by dry etching, the moisture in the interlayer insulating film is continuously removed by drying under reduced pressure without being exposed to the atmosphere, and the surface of the damaged layer Since the modification is performed, it is possible to suppress the breakdown voltage deterioration of the interlayer insulating film and the increase of the dielectric constant due to moisture. Therefore, the yield of the semiconductor device is improved, and the semiconductor device with improved reliability of the semiconductor device can be manufactured.

同一の装置内で連続して減圧乾燥とダメージ層の表面改質を行うときは、層間絶縁膜を有する半導体基板を大気に触れさせずに、これらの処理を行うことができる。よって、層間絶縁膜の耐圧劣化や誘電率の上昇を抑制し、歩留り良く、信頼性の高い半導体装置を製造することができる。
減圧乾燥とダメージ層の表面改質を、それぞれ異なる装置で大気に晒さずに連続して行うときも、層間絶縁膜の耐圧劣化や誘電率の上昇を抑制し、歩留り良く、信頼性の高い半導体装置を製造することができる。
When continuously drying under reduced pressure and modifying the surface of a damaged layer in the same apparatus, these treatments can be performed without exposing the semiconductor substrate having an interlayer insulating film to the atmosphere. Therefore, it is possible to manufacture a semiconductor device with high yield and high reliability by suppressing the breakdown voltage degradation and the increase in dielectric constant of the interlayer insulating film.
Even when vacuum drying and surface modification of damaged layers are carried out continuously without exposing them to the atmosphere with different devices, it is possible to suppress deterioration of the dielectric breakdown voltage and increase of dielectric constant of the interlayer insulation film, and to improve the yield and reliability. The device can be manufactured.

層間絶縁膜のダメージ層を、シラザン系の化合物、好ましくはSi−n結合及びCH3の結合からなる化合物でシリル化するときは、ダメージ層の表面改質を良好に行うことができる。
層間絶縁膜として低誘電率絶縁膜を用いることにより、配線容量の低減を図ることができる。
When the damage layer of the interlayer insulating film is silylated with a silazane compound, preferably a compound composed of a Si—n bond and a CH 3 bond, the surface modification of the damage layer can be performed satisfactorily.
By using a low dielectric constant insulating film as the interlayer insulating film, the wiring capacitance can be reduced.

以下、図面を参照して本発明の実施の形態を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1a〜図2hは、本発明に係る半導体装置の製造方法の実施の形態、すなわち、配線形成において、減圧乾燥方式による基板乾燥とHMDS処理によるシリル化を連続して処理する製造方法である。   1a to 2h show an embodiment of a method for manufacturing a semiconductor device according to the present invention, that is, a manufacturing method for successively processing substrate drying by a reduced pressure drying method and silylation by HMDS processing in wiring formation.

先ず、図1aに示すように、所要の半導体素子を形成した半導体基板のシリコン基板2上に、エッチングのストッパー膜3を成膜する。ストッパー膜3としては、シリコン窒化膜系(SiとNの結合)若しくは、SiC膜系(SiとCの結合)を成膜する。   First, as shown in FIG. 1a, an etching stopper film 3 is formed on a silicon substrate 2 of a semiconductor substrate on which required semiconductor elements are formed. As the stopper film 3, a silicon nitride film system (bonding of Si and N) or an SiC film system (bonding of Si and C) is formed.

次に、図1bに示すように、ストッパー膜3上に層間絶縁膜4を成膜する。本例では、層間絶縁膜4として低誘電率絶縁膜であるLow−k膜を成膜する(以下、層間絶縁膜をLow−k膜4とする)。本例では、Lowーk膜4を化学構造で示すSiOC系のCVD膜で形成する。
Low−k膜4としては、シリコンを主成分とする低誘電率材料でキセロゲル(ポーラスシリカ)、シリコン酸化炭化膜(SiOC(H))、メチルシリシスキオキサン(MSQ)、ハイドロシリシスキオキサン(HSQ)、同重合ポリマー(HMSQ)等を用いることができる。
Next, as shown in FIG. 1B, an interlayer insulating film 4 is formed on the stopper film 3. In this example, a low-k film that is a low dielectric constant insulating film is formed as the interlayer insulating film 4 (hereinafter, the interlayer insulating film is referred to as a low-k film 4). In this example, the low-k film 4 is formed of a SiOC-based CVD film having a chemical structure.
The low-k film 4 is a low dielectric constant material mainly composed of silicon, such as xerogel (porous silica), silicon oxycarbide film (SiOC (H)), methyl silisisquioxane (MSQ), hydrosilisisquioxane (HSQ). ), The same polymer (HMSQ), and the like can be used.

次に、図1cに示すように、Low−k膜4上にパターンマスクとなるシリコン酸化膜5を成膜して、さらにシリコン酸化膜5上にフォトレジスト膜6aを塗布する。   Next, as shown in FIG. 1 c, a silicon oxide film 5 serving as a pattern mask is formed on the low-k film 4, and a photoresist film 6 a is further applied on the silicon oxide film 5.

次に、図1dに示すように、フォトレジスト膜6aとシリコン酸化膜5に対してフォトリソグラフィー処理及びエッチング処理を行うことによって、配線溝(すなわち配線接続用のビアホール)のパターンに形成したパターンの開口7aを形成する。6bは、フォトリソグラフィー処理後のレジスト層である。   Next, as shown in FIG. 1d, a photolithography process and an etching process are performed on the photoresist film 6a and the silicon oxide film 5 to form a pattern of the wiring groove (that is, a via hole for wiring connection). Opening 7a is formed. 6b is a resist layer after photolithography.

次に、図1eに示すように、レジスト層6b及びシリコン酸化膜5をマスクにして、ドライエッチングにより、Low−k膜4に配線溝7bを形成する。ドライエッチング後には、配線溝7b内に残渣物9が付着する。また、配線溝7b内のLow−k膜4の表層近傍にはプラズマによるダメージを受けて分子構造が変化した、ダメージ層10が形成される。   Next, as shown in FIG. 1e, wiring grooves 7b are formed in the low-k film 4 by dry etching using the resist layer 6b and the silicon oxide film 5 as a mask. After the dry etching, the residue 9 adheres in the wiring groove 7b. In addition, a damaged layer 10 having a molecular structure changed due to plasma damage is formed near the surface layer of the low-k film 4 in the wiring trench 7b.

次に、図2fに示すように、ドライエッチングによるエッチング残渣物9を除去するための、洗浄処理を行う。この洗浄処理はドライエッチング後のシリコン基板3を例えば、枚葉式の洗浄装置内に搬送し、薬液及び純水等のリンス処理を組み合わせて行う。このときダメージ層10を介してLow−k膜4中に水分11が吸収される。図3aに示すようにLow−k膜4中の化学構造は、その多孔質内に水分11であるH2Oを含んだ状態である。なお、図3aは、図2fの配線溝7bの内壁部分の水分を吸収した領域Aに対応し、ダメージ層10及びLowーk膜4の化学構造を示している。   Next, as shown in FIG. 2f, a cleaning process for removing the etching residue 9 by dry etching is performed. This cleaning process is performed by transporting the dry-etched silicon substrate 3 into, for example, a single wafer cleaning apparatus, and combining a rinsing process such as a chemical solution and pure water. At this time, moisture 11 is absorbed into the low-k film 4 through the damage layer 10. As shown in FIG. 3a, the chemical structure in the low-k film 4 is a state in which H2O which is moisture 11 is contained in the porous body. Note that FIG. 3 a corresponds to the region A that has absorbed moisture in the inner wall portion of the wiring groove 7 b in FIG. 2 f and shows the chemical structure of the damage layer 10 and the low-k film 4.

この時パターンマスクは、レジスト層6bのみでも構わず、ドライエッチング後にアッシングによりレジスト層6bを除去する。   At this time, only the resist layer 6b may be used as a pattern mask, and the resist layer 6b is removed by ashing after dry etching.

次に、洗浄後のLowーk膜4を有した半導体基板2に対して、同一装置、例えば乾燥処理室(チャンバー)内で減圧乾燥による水分除去と、シラザン系化合物による処理でダメージ層10の表面改質、いわゆるシリル化とを行う。   Next, with respect to the semiconductor substrate 2 having the low-k film 4 after cleaning, the damage layer 10 is removed by removing moisture by drying under reduced pressure in the same apparatus, for example, a drying processing chamber (chamber) and processing with a silazane compound. Surface modification, so-called silylation, is performed.

すなわち、図2gに示すように、枚葉式の洗浄装置の処理室内で、減圧乾燥、すなわち減圧中で加熱処理して乾燥することによりLow−k膜4内部の水分11をダメージ層10を介して脱離させる。すなわち、図3b(図2gの領域Aに対応する)に示すように、ダメージ層10及びLow−k膜4よりH2Oが取り除かれた化学構造となる。   That is, as shown in FIG. 2g, the moisture 11 in the Low-k film 4 is passed through the damage layer 10 by drying under reduced pressure in the processing chamber of the single wafer cleaning apparatus, that is, by heat treatment in reduced pressure. To desorb. That is, as shown in FIG. 3B (corresponding to the region A in FIG. 2G), the chemical structure is obtained by removing H 2 O from the damaged layer 10 and the low-k film 4.

次いで、図2hに示すように、減圧乾燥処理と同一処理室内で連続してシラザン系化合物、本例では、Si−n結合及びCH3の結合からなる化合物であるHMDS(ヘキサメチルジシラザン)の処理を行うことにより、ダメージ層10をシリル化して回復する。図4に示すように、ダメージ層10の結合Si−OH(図4中左図参照)は、HMDS処理されることで、ダメージ層10はSi−O−Si−(CH3)3(図4中右図参照)に置き換えられる。反応式を化1に示す。   Next, as shown in FIG. 2h, the treatment of the silazane compound, HMDS (hexamethyldisilazane), which is a compound composed of a Si—n bond and a CH3 bond in this example, continuously in the same processing chamber as the vacuum drying treatment. To recover the damaged layer 10 by silylation. As shown in FIG. 4, the bonded Si—OH (see the left figure in FIG. 4) of the damaged layer 10 is subjected to HMDS treatment, so that the damaged layer 10 becomes Si—O—Si— (CH 3) 3 (in FIG. 4). (See the figure on the right). The reaction formula is shown in Chemical Formula 1.

Figure 2005340288
Figure 2005340288

このダメージ層10の表面改質処理では、減圧乾燥した減圧下で処理室内にHMDSガス(HMDS液体を気化したもの)を導入してHMDS処理する。減圧下でHMDS処理ができないときは、処理室内を不活性ガス(例えばN2ガス、Arガス等)でパージし、この不活性ガスをキャリアガスとしてHMDSガスを処理室内に導入する。そして、HMDSガスとダメージ層10とを反応させてダメージ層10をシリル化する。このときのキャリアガスとHMDSガスの比率、すなわちキャリアガス:HMDSガスは、20:1〜5:1の範囲とすることができる。   In the surface modification treatment of the damaged layer 10, HMDS treatment is performed by introducing HMDS gas (a vaporized HMDS liquid) into the treatment chamber under reduced pressure after drying under reduced pressure. When HMDS processing cannot be performed under reduced pressure, the processing chamber is purged with an inert gas (for example, N 2 gas, Ar gas, etc.), and HMDS gas is introduced into the processing chamber using the inert gas as a carrier gas. Then, the damaged layer 10 is silylated by reacting the HMDS gas with the damaged layer 10. At this time, the ratio of carrier gas to HMDS gas, that is, carrier gas: HMDS gas, can be in the range of 20: 1 to 5: 1.

次に、図示せざるも、配線溝7b内のストッパー層3を選択的にエッチング除去した後、配線溝7b内を埋めるように導電層を成膜し、パターニングして配線溝7b内の配線接続部と配線を形成する。例えばダマシン法を用い、配線溝を含む表面に銅(Cu)バリア膜を成膜し、パターニングして配線溝7b内の配線接続部を通じて下層の電極(あるいは配線)と接続した上層配線を形成する。多層配線を形成する場合は、図2bから図2hの工程が繰替えされる。このようにして、目的の配線を形成した半導体装置を得る。   Next, although not shown, after selectively removing the stopper layer 3 in the wiring groove 7b by etching, a conductive layer is formed so as to fill the wiring groove 7b and patterned to connect the wiring in the wiring groove 7b. And wiring are formed. For example, using a damascene method, a copper (Cu) barrier film is formed on the surface including the wiring groove, and patterned to form an upper layer wiring connected to the lower layer electrode (or wiring) through the wiring connecting portion in the wiring groove 7b. . In the case of forming a multilayer wiring, the steps of FIGS. 2b to 2h are repeated. In this way, a semiconductor device in which a target wiring is formed is obtained.

上述した実施の形態に係る半導体装置の製造方法では、減圧乾燥と表面改質を同一装置の同一処理室内で行うようにしたが、その他、同一装置内において、互いにシャッタ手段を介して隣接する減圧乾燥処理室と表面改質処理室でそれぞれ減圧乾燥と表面改質を大気に晒せずに連続して行うようにすることも可能である。この場合、表面改質処理室内に、ノズルを通じてHMDS液体を供給しHMDS液とダメージ層10とを反応させる、あるいは供給管を通じてHMDSガスを供給しHMDSガスとダメージ層10とを反応させるようになす。または、同一装置内において、乾燥処置室で減圧乾燥した後、表面改質を洗浄処置室で行うことも可能である。   In the semiconductor device manufacturing method according to the above-described embodiment, the reduced pressure drying and the surface modification are performed in the same processing chamber of the same apparatus. In addition, in the same apparatus, the reduced pressure adjacent to each other via the shutter unit. It is also possible to perform drying under reduced pressure and surface modification continuously in the drying treatment chamber and the surface modification treatment chamber without being exposed to the atmosphere. In this case, the HMDS liquid is supplied into the surface reforming chamber through the nozzle and the HMDS liquid and the damaged layer 10 are reacted, or the HMDS gas is supplied through the supply pipe to react the HMDS gas and the damaged layer 10. . Alternatively, in the same apparatus, it is possible to perform surface modification in the cleaning treatment chamber after drying under reduced pressure in the drying treatment chamber.

上述した本実施の形態の半導体装置の製造方法では、洗浄処理、減圧乾燥処理とHMDS処理を同一装置内で連続的に行ったが、各工程を別々の装置で行ってもよい。
減圧乾燥処理とHMDS処理を別々の処理装置で行う場合は、減圧乾燥処理装置とHMDS処理装置との間に処理すべき半導体基板を大気に晒さないで両装置間を搬送できるバッファ部を設けるようになす。この実施形態では、配線溝を形成したLow−k膜4を水洗浄処理後に、このLow−k膜4を有した半導体基板2を減圧乾燥処理を行う装置に格納して減圧乾燥する。その後、この半導体基板2をバッファ部を通じて表面改質処理を行う装置に搬送し、HMDS液、あるいはHMDSガスを導入してLow−k膜のダメージ層10をHMDS処理することによって回復させる。このように連続して処理することで、減圧乾燥後、ダメージ層を介してLow−k膜へ水分の再吸収が起こらなくなる。
In the semiconductor device manufacturing method of the present embodiment described above, the cleaning process, the reduced-pressure drying process, and the HMDS process are continuously performed in the same apparatus, but each process may be performed in separate apparatuses.
When the vacuum drying process and the HMDS process are performed by separate processing apparatuses, a buffer unit capable of transporting between the apparatuses without exposing the semiconductor substrate to be processed to the atmosphere is provided between the vacuum drying process apparatus and the HMDS processing apparatus. To make. In this embodiment, after the Low-k film 4 in which the wiring trench is formed is subjected to a water cleaning process, the semiconductor substrate 2 having the Low-k film 4 is stored in an apparatus for performing a vacuum drying process and dried under a reduced pressure. Thereafter, the semiconductor substrate 2 is transported to an apparatus for performing a surface modification treatment through a buffer unit, and the damaged layer 10 of the Low-k film is recovered by HMDS treatment by introducing HMDS liquid or HMDS gas. By continuously processing in this manner, moisture is not reabsorbed into the low-k film via the damaged layer after drying under reduced pressure.

本実施の形態に係る半導体装置の製造方法によれば、同一装置内、あるいは異なる装置で洗浄処理後の半導体基板2に対する減圧乾燥とHMDS処理を大気に触れずに連続的に行うことにより、Lowーk膜4内に吸収された水分を離脱させ、かつLowーk膜4内に再度水分を吸収させることなく、HMDS処理によるダメージ層10をシリル化して回復させることができる。よって、水に起因しタLowーk膜4の耐圧廉価や誘電率の上昇を抑制することができる。また、HMDS処理によりドライエッチング時のLowーk膜4のプラズマダメージを回復することができる。   According to the method for manufacturing a semiconductor device according to the present embodiment, low-pressure drying and HMDS processing are continuously performed on the semiconductor substrate 2 after being cleaned in the same device or in a different device without touching the atmosphere. The moisture layer absorbed by the HMDS treatment can be recovered by silylation without releasing the moisture absorbed in the −k film 4 and again absorbing the moisture in the low-k film 4. Therefore, it is possible to suppress an increase in the breakdown voltage and dielectric constant of the low-k film 4 due to water. Further, the plasma damage of the low-k film 4 during dry etching can be recovered by the HMDS process.

次に、図5〜図7の測定データを元に本実施の形態に係る半導体装置の製造方法の優位性を説明する。
図5は、Lowーk膜に対して、未処理、洗浄処理のみ、洗浄と減圧乾燥処理、洗浄とシリル化処理を行ったときの、それぞれの水分含有の状態を表したグラフである。図5では、縦軸に水分含有量をとり、横軸に加熱温度をとる。加熱温度を上げて行くに従って蒸発して膜中に含まれる水分が離脱し、その後蒸発が減って行く状態を示している。
この図5のグラフによれば、曲線(a)の未処理では、膜中の含まれる水分が極めて少ない。曲線(b)の洗浄処理のみの状態では、膜中に多く水分が含まれる。曲線(d)の洗浄後にシリル化処理した場合では、水分の離脱が少なく、膜中に多く水分が残る。曲線(c)の洗浄後に減圧乾燥した場合には、膜中の水分が離脱する。このグラフから分かるように、洗浄後のシリル化処理のみでは膜中の水分離脱を十分に行うことはできない。これに対して洗浄処理した後に減圧乾燥するときは、膜中の水分が十分離脱し、膜が確実に乾燥することが認められる。
Next, the superiority of the manufacturing method of the semiconductor device according to the present embodiment will be described based on the measurement data of FIGS.
FIG. 5 is a graph showing the respective moisture-containing states when the low-k film is untreated, washed only, washed and dried under reduced pressure, washed and silylated. In FIG. 5, the vertical axis represents moisture content, and the horizontal axis represents heating temperature. It shows a state in which as the heating temperature is raised, the water evaporates and moisture contained in the film is released, and then the evaporation decreases.
According to the graph of FIG. 5, the moisture contained in the film is extremely small when the curve (a) is untreated. In the state of only the cleaning process of the curve (b), the film contains a large amount of moisture. In the case where the silylation treatment is performed after the cleaning of the curve (d), there is little separation of moisture, and much moisture remains in the film. When drying under reduced pressure after washing the curve (c), moisture in the film is released. As can be seen from this graph, moisture removal from the film cannot be sufficiently performed only by the silylation treatment after washing. On the other hand, when drying under reduced pressure after washing treatment, it is recognized that water in the film is sufficiently removed and the film is surely dried.

図6は、基板の処理状態を変えて、基板の層間絶縁膜の誘電率を測定したグラフである。
先ず、未処理な状態の半導体装置の誘電率f1は、もっとも低い値となる。
次に、半導体装置を洗浄処理した後の誘電率f2は、未処理と比べ3倍程度上昇する値となる。
次に、半導体装置を洗浄処理後にHMDS処理した後の誘電率f3は、洗浄処理後にくらべ誘電率が若干減少する。
次に、洗浄処理後、減圧乾燥なしの基板では、洗浄処理後の誘電率f2と同等まで上昇して誘電率f4となる。
このとき、洗浄処理後、減圧乾燥ありの基板では、未処理基板の誘電率f1と同等の誘電率e5と低くなる。
FIG. 6 is a graph obtained by measuring the dielectric constant of the interlayer insulating film of the substrate while changing the processing state of the substrate.
First, the dielectric constant f1 of the unprocessed semiconductor device is the lowest value.
Next, the dielectric constant f2 after the semiconductor device is subjected to the cleaning process is a value that is increased about three times as compared with the unprocessed state.
Next, the dielectric constant f3 after the semiconductor device is subjected to the HMDS process after the cleaning process is slightly decreased as compared with the dielectric constant f3 after the cleaning process.
Next, after the cleaning process, the substrate without drying under reduced pressure rises to the same dielectric constant f2 after the cleaning process and becomes a dielectric constant f4.
At this time, after the cleaning treatment, the substrate with reduced pressure drying has a low dielectric constant e5 which is equivalent to the dielectric constant f1 of the untreated substrate.

図7は、基板の処理状態を変えて、その後7日間大気中に放置した場合の各基板の層間絶縁膜の誘電率を測定したグラフである。ただし、未処理基板については、7日間大気中に放置しないものを用いる。
未処理基板の誘電率g1が、もっとも低くなる。
次に、洗浄処理後の基板の誘電率g2は、高い誘電率g2となる。
次に、洗浄処理後にHMDS処理を行った基板の誘電率g3は、洗浄処理後の基板の誘電率g2にくらべ若干低くなる。
洗浄処理後、減圧乾燥のみを行った誘電率g4は、7日間大気中に放置している間に水分を吸収して、高くなる。
本実施の形態に係る洗浄処理後、減圧乾燥してHMDS処理した基板の誘電率g5は、未処理の基板の誘電率g1と同等の低い誘電率を保持することができる。
FIG. 7 is a graph obtained by measuring the dielectric constant of the interlayer insulating film of each substrate when the processing state of the substrate is changed and left in the air for 7 days thereafter. However, unprocessed substrates that are not left in the atmosphere for 7 days are used.
The unprocessed substrate has the lowest dielectric constant g1.
Next, the dielectric constant g2 of the substrate after the cleaning process becomes a high dielectric constant g2.
Next, the dielectric constant g3 of the substrate subjected to the HMDS process after the cleaning process is slightly lower than the dielectric constant g2 of the substrate after the cleaning process.
After the cleaning treatment, the dielectric constant g4, which is only dried under reduced pressure, increases by absorbing moisture while left in the atmosphere for 7 days.
After the cleaning process according to the present embodiment, the dielectric constant g5 of the substrate dried under reduced pressure and subjected to HMDS treatment can maintain a low dielectric constant equivalent to the dielectric constant g1 of the untreated substrate.

上述の実験結果からも半導体基板の層間絶縁膜の洗浄後に減圧乾燥とHMDS処理によるシリル化を連続して行うことは水分含有量の低減、しいては、誘電率の低減を図ることができる。   From the above experimental results, it is possible to reduce the moisture content and, further, to reduce the dielectric constant, by continuously performing the drying under reduced pressure and the silylation by the HMDS treatment after the cleaning of the interlayer insulating film of the semiconductor substrate.

a〜e 本発明に係る半導体装置の製造方法の一実施の形態を示す工程図である(その1)。a to e are process diagrams showing an embodiment of a method of manufacturing a semiconductor device according to the present invention (part 1). f〜h 本発明に係る半導体装置の製造方法の一実施の形態を示す工程図である(その2)。f to h are process diagrams showing an embodiment of a method of manufacturing a semiconductor device according to the present invention (part 2). a 図2fに対応したLow−k膜中の構造を示す化学構造式である。 b 図2gに対応したLow−k膜中の構造を示す化学構造式である。a is a chemical structural formula showing the structure in the Low-k film corresponding to FIG. b is a chemical structural formula showing the structure in the Low-k film corresponding to FIG. 図2hに対応したLow−k膜中の構造を示す化学構造式である。It is a chemical structural formula showing the structure in the Low-k film corresponding to FIG. 本発明に係る半導体装置の製造方法を用いた半導体装置と従来の半導体装置の配線間絶縁膜中の水分含有量に対する加熱温度の関係を比較したグラフである。6 is a graph comparing the relationship between the heating temperature and the moisture content in the inter-wiring insulating film of the semiconductor device using the method for manufacturing a semiconductor device according to the present invention and a conventional semiconductor device. 半導体装置の配線間絶縁膜中の誘電率を比較したグラフである。It is the graph which compared the dielectric constant in the insulating film between wiring of a semiconductor device. 本発明に係る半導体装置の製造方法を用いた半導体装置と従来の半導体装置の配線間絶縁膜中の誘電率を7日間大気中に放置して比較したグラフである。7 is a graph comparing the dielectric constant in the inter-wiring insulating film of the semiconductor device using the semiconductor device manufacturing method according to the present invention and the conventional semiconductor device, which is left in the atmosphere for 7 days.

符号の説明Explanation of symbols

2・・シリコン基板、3・・ストッパー膜、4・・層間絶縁膜(Low−k膜)、5・・シリコン酸化膜、6a・・フォトレジスト膜、6b・・レジスト層、7a・・開口、7b・・配線溝、9・・残渣物、10・・ダメージ層、11・水分、 2 .. Silicon substrate 3. Stopper film 4.. Interlayer insulating film (Low-k film) 5... Silicon oxide film 6 a .. Photoresist film 6 b .. Resist layer 7 a. 7b..Wiring groove, 9..Residue, 10..Damage layer, 11..Moisture,

Claims (6)

半導体基板に形成した層間絶縁膜をドライエッチングによってパターニングする工程と、
前記層間絶縁膜を有する半導体基板を洗浄する工程と、
前記層間絶縁膜を有する半導体基板を減圧乾燥する工程と、
前記ドライエッチングによる前記層間絶縁膜のダメージ層の表面改質を行う工程とを有し、
前記減圧乾燥と前記表面改質を大気に晒さずに連続して行う
ことを特徴とする半導体装置の製造方法。
Patterning the interlayer insulating film formed on the semiconductor substrate by dry etching;
Cleaning the semiconductor substrate having the interlayer insulating film;
Drying the semiconductor substrate having the interlayer insulating film under reduced pressure;
Modifying the surface of the damaged layer of the interlayer insulating film by the dry etching,
The method of manufacturing a semiconductor device, wherein the drying under reduced pressure and the surface modification are continuously performed without being exposed to the atmosphere.
前記減圧乾燥と前記表面改質を同一装置内で行う
ことを特徴とする請求項1記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 1, wherein the drying under reduced pressure and the surface modification are performed in the same apparatus.
前記減圧乾燥と前記表面改質を、それぞれ異なる装置で行う
ことを特徴とする請求項1記載の半導体基板の製造方法。
The method for manufacturing a semiconductor substrate according to claim 1, wherein the reduced-pressure drying and the surface modification are performed by different apparatuses.
前記表面改質に使用する材料は、シラザン系化合物である
ことを特徴とする請求項1記載の半導体基板の製造方法。
The method for manufacturing a semiconductor substrate according to claim 1, wherein the material used for the surface modification is a silazane compound.
前記シラザン系化合物は、Si−n結合及びCH3の結合からなる化合物である
ことを特徴とする請求項4記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 4, wherein the silazane compound is a compound composed of a Si—n bond and a CH 3 bond.
前記層間絶縁膜は低誘電率絶縁膜である
ことを特徴とする請求項1記載の半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a low dielectric constant insulating film.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7556970B2 (en) 2006-03-27 2009-07-07 Tokyo Electron Limited Method of repairing damaged film having low dielectric constant, semiconductor device fabricating system and storage medium
JP2010251596A (en) * 2009-04-17 2010-11-04 Toshiba Corp Method of manufacturing semiconductor device
US8338290B2 (en) 2009-01-15 2012-12-25 Panasonic Corporation Method for fabricating semiconductor device
JP2019087768A (en) * 2019-03-13 2019-06-06 ラピスセミコンダクタ株式会社 Semiconductor device
US11018017B2 (en) 2016-09-26 2021-05-25 SCREEN Holdings Co., Ltd. Substrate treatment method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7556970B2 (en) 2006-03-27 2009-07-07 Tokyo Electron Limited Method of repairing damaged film having low dielectric constant, semiconductor device fabricating system and storage medium
US8338290B2 (en) 2009-01-15 2012-12-25 Panasonic Corporation Method for fabricating semiconductor device
JP2010251596A (en) * 2009-04-17 2010-11-04 Toshiba Corp Method of manufacturing semiconductor device
US11018017B2 (en) 2016-09-26 2021-05-25 SCREEN Holdings Co., Ltd. Substrate treatment method
JP2019087768A (en) * 2019-03-13 2019-06-06 ラピスセミコンダクタ株式会社 Semiconductor device

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