US20010001230A1 - Apparatus for translating a voltage - Google Patents
Apparatus for translating a voltage Download PDFInfo
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- US20010001230A1 US20010001230A1 US09/732,793 US73279300A US2001001230A1 US 20010001230 A1 US20010001230 A1 US 20010001230A1 US 73279300 A US73279300 A US 73279300A US 2001001230 A1 US2001001230 A1 US 2001001230A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- This invention relates to electronic circuitry and, more particularly, to a charge pump for producing a negative substrate bias in a complementary metal oxide semiconductor (CMOS) integrated circuit.
- CMOS complementary metal oxide semiconductor
- MOS transistors are commonly used in electronic circuits such as dynamic random access memories (DRAMS).
- DRAMS dynamic random access memories
- an NMOS transistor an N-type source region is separated from an N-type drain region by a P-type channel region. All three regions are formed in a P-type semiconductor substrate.
- a positive voltage to a gate electrode disposed above the channel region electrons gather in the channel region between the source region and the drain region to allow current to flow from the drain region to the source region.
- PMOS transistors have the same structure except the conductivity types of the various regions are reversed and a negative gate voltage is required to allow current to flow from the source region to the drain region.
- NMOS transistors operate better when the P-type substrate of the NMOS (or of the NMOS transistors in a CMOS circuit) is driven negative with respect to circuit ground, in other words there is a negative substrate bias.
- a negative substrate bias provides a number of advantages in terms of the overall circuit performance. More specifically, a negative substrate bias decreases the NMOS transistor source and drain capacitance, decreases the likelihood of latchup, decreases PN diode injection when a node is driven below ground, and decreases the effective body effect, all of which are desirable in CMOS circuits.
- a charge pump circuit is used to create the negative substrate bias. Once a negative substrate bias is achieved, however, it does not last forever. For example, when an NMOS transistor is conductive with a relatively high drain to source voltage, some of the electrons traveling from the source region to the drain region collide with atoms in the channel region with enough energy to cause electron/hole pairs to form. The positive gate voltage attracts the generated electrons to the surface of the channel while the positive drain voltage attracts them to the drain where they simply add to the normal flow of electrons from source to drain. The positively charged holes, by contrast, are repelled by the positively charged gate away from the channel region into the substrate. The substrate current created by the excess holes makes the substrate more positively charged, thus counteracting the negative substrate bias.
- DRAMS DRAMS
- a substantial amount of substrate current is generated whenever the memory is read or written, since many transistors are switched on and off at that time.
- This component of substrate current may be orders of magnitude above the background (i.e., standby) leakage current of all the reverse biased P-N diodes throughout the circuit. Therefore, the charge pump must remove low substrate current during standby and high substrate current during high activity to maintain the negative substrate bias.
- FIG. 1 is a conceptual schematic diagram of a charge pump 2 which includes a first switch 4 coupled between a positive power supply voltage (V cc ) and a first terminal 6 of a capacitance C 1 .
- a second switch 8 is coupled between a ground potential (V ss ) and a second terminal 10 of capacitance C 1 .
- a third switch 12 is coupled between (V ss ) and terminal 6 of capacitance C 1
- a fourth switch 14 is coupled between the substrate (represented by the voltage (V bb )) and terminal 10 of capacitance C 1 .
- switches 4 and 8 are both closed (made conductive) for charging capacitance C 1 to a voltage equal to the difference between (V cc ) and (V ss ).
- switches 4 and 8 are opened and switches 12 and 14 are both closed. Since the positive terminal 6 of capacitance C 1 is now coupled to a ground potential, the negative terminal 10 of capacitance C 1 tries to drive V bb to negative 5 volts through switch 14 . Thereafter, switches 12 and 14 are opened, and the sequence repeats itself.
- An oscillator typically controls the repetitive switching sequence
- a detector (not shown) monitors the substrate voltage and controls the pumping operation to maintain the substrate at the proper negative voltage level.
- the present invention is directed to a charge pump which consumes only a very small amount of power (approximately 50 microwatts or less in the exemplary embodiment described herein when no additional pumping is required).
- the charge pump according to the present invention does not add substrate current as it operates, and operates more efficiently than known charge pumps.
- a low voltage regulator on the integrated circuit generates a low voltage supply on the integrated circuit for powering a variable frequency oscillator, whose nodes oscillate between ground and the regulated low voltage supply of, for example, about 1.5 volts.
- the low voltage regulator provides a slightly higher voltage until some negative substrate bias is achieved, assuring proper start-up operation of the oscillator.
- the low voltage supply dramatically reduces power consumption of the oscillator compared to known oscillators.
- the oscillator operates at a low frequency for low power consumption when no charge pumping is needed (i.e., when the substrate voltage is at or below the desired negative bias voltage level and the circuit is in standby), and operates at a much higher frequency when charge pumping is needed or likely will be needed.
- the charge pump will be needed when the substrate voltage is more positive than the desired negative bias voltage level, and may be needed when the integrated circuit is operating in a mode which typically generates high substrate currents.
- the variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump.
- Voltage translation circuitry translates the negative substrate voltage into a positive voltage signal (e.g., between 0 and +5 volts). This allows the (translated) substrate voltage to be compared to a positive reference voltage using a conventional comparator, without adding substrate current as it operates. When the substrate voltage is more positive than the desired level, the comparator generates a pump activating signal to a pump signal generator which turns on the charge pump.
- the charge pump itself uses an NMOS transistor to perform the switching function of switch 14 of FIG. 1 in a configuration that neither loses a threshold voltage when conducting nor allows P-N diode injection into the substrate when node 6 of capacitor C 1 is driven low by switch 12 . Likewise, all other switches 4 , 8 , and 14 do not exhibit a threshold voltage drop.
- the one-stage pump of the present invention is capable of pumping the substrate to a voltage of ⁇ 4.9 volts when operating from a supply of +5.0 volts (with the regulator disabled).
- FIG. 1 is a conceptual schematic diagram of a known charge pump
- FIG. 2 is a block diagram of a particular embodiment of a charge pumping system according to the present invention.
- FIG. 3 is a block diagram of a particular embodiment of the variable frequency oscillator shown in FIG. 2;
- FIG. 4 is a schematic diagram of a known oscillator stage
- FIG. 5 is a schematic diagram of a particular embodiment of the low voltage generator shown in FIG. 2;
- FIG. 6 is a schematic diagram of an alternative embodiment of the low voltage generator shown in FIG. 5;
- FIG. 7 is a waveform showing the operation of the dual frequency oscillator shown in FIG. 3;
- FIG. 8 is a schematic diagram of a particular embodiment of a variable frequency oscillator stage shown in FIG. 3;
- FIG. 9 is a schematic diagram of a timing signal generator shown in FIG. 2;
- FIG. 10 is a timing diagram illustrating the timing of signals generated by the timing signal generator shown in FIG. 9;
- FIG. 11 is a schematic diagram of a known substrate voltage comparator
- FIG. 12 is a conceptual schematic diagram of a particular embodiment of a substrate voltage detector according to the present invention.
- FIG. 13 is a schematic diagram of a particular embodiment of the logic voltage level translator shown in FIG. 2;
- FIG. 14 is a schematic diagram of particular embodiments of the substrate voltage translator and comparator shown in FIG. 2;
- FIG. 15 is a schematic diagram of a particular embodiment of the pump signal generator shown in FIG. 2;
- FIG. 16 is a timing diagram illustrating the timing of the input signal and of the signals generated by the pump signal generator shown in FIG. 15;
- FIG. 17 is a schematic diagram of a particular embodiment of the charge pump shown in FIG. 2;
- FIG. 18 is a schematic diagram of a known substrate charge switch comprising a diode-connected NMOS transistor
- FIG. 19 is a schematic diagram of a known substrate charge switch comprising a diode-connected PMOS transistor.
- FIG. 20 is a schematic diagram of a particular embodiment of a substrate charge switch comprising a serially connected PMOS transistor.
- FIG. 2 is a block diagram of a particular embodiment of a substrate charge pumping system 20 according to the present invention.
- a low voltage generator 24 provides a reduced potential source (for power saving) through bus 32 to power a variable (e.g., dual) frequency oscillator 28 and timing signal generator 34 .
- Variable frequency oscillator 28 provides oscillation signals of high or low frequency through a bus 36 to timing signal generator 34 . High frequency is for fast pumping and low frequency is for reduced power.
- timing signal generator 34 provides timing signals to control the operation of the remaining portions of the circuit.
- generator 34 provides timing signals to logic voltage level translator 40 , comparator 56 and substrate voltage translator 44 through bus 48 .
- Logic level voltage translator 40 translates the low voltage signals, for example 0 to +1.5 volts, produced by oscillator 28 and timing generator 34 into higher voltage signals, of for example 0 to +5 volts.
- the higher voltage signals are supplied to comparator 56 through a bus 50 .
- Substrate voltage translator 44 translates the substrate voltage from a level below ground to a level above ground and supplies the translated voltage to comparator 56 through a bus 58 .
- Comparator 56 compares the translated voltage received on bus 58 to a reference voltage received on a bus 60 and provides, when needed, pump activating signals to a pump signal generator 64 through a bus 68 .
- the SPUMP and NSPUMP signals are used to control the frequency of the oscillator.
- Pump signal generator 64 generates timing signals on a bus 76 for controlling the operation of a charge pump 80 .
- Charge pump 80 creates and maintains a negative substrate bias.
- Charge pump 80 uses special circuitry which does not experience an undesirable threshold drop in any diode-connected transistor.
- FIG. 3 is a block diagram of a particular embodiment of a dual frequency free-running oscillator 28 .
- Oscillator 28 comprises an odd number of oscillator stages 84 A-E in the form of inverters.
- the output terminal of each oscillator stage is coupled to the input terminal of the next oscillator stage, and the output terminal of oscillator stage 84 E is coupled to the input terminal of oscillator stage 84 A, thus forming a ring oscillator.
- the ring oscillator generates a free-running oscillating signal as each node in the ring alternates a logic “1” and a logic “0”.
- Each oscillator stage 84 A-E is coupled to bus 32 for receiving power from source 24 (not shown).
- FIG. 4 is a schematic diagram of a known oscillator stage suitable for use as oscillator stages 84 A-E.
- the oscillator stage comprises a PMOS transistor 88 coupled to an NMOS transistor 92 .
- the source terminal 94 of transistor 88 is coupled to V cc
- the drain terminal 96 is coupled to output node 98
- the gate terminal 102 is coupled to input node 104 .
- Node 104 receives signals from the output node of the previous stage, i.e., stage 84 B, if this is stage 84 C.
- NMOS transistor 92 has its drain terminal 106 coupled to output node 98 , its source terminal 108 coupled to V ss , and its gate terminal 110 coupled to input node 104 .
- low voltage generator 24 provides a low voltage signal on bus 32 for powering oscillator 28 .
- the low voltage is equal to the sum of the absolute magnitudes of the threshold voltages V tn and V tp .
- source terminal 94 of PMOS transistor 88 is coupled to a +1.5 volt potential rather than a +5 volt potential, according to the present invention. Therefore, when input node 104 is at 0 volts, PMOS transistor 88 conducts, NMOS transistor 92 is off, and output node 98 is at +1.5 volts.
- timing signal generator 34 When the voltage at input node 104 rises to +0.8 volts, NMOS transistor 92 turns on, and PMOS transistor 88 turns off. As the voltage at input node 104 continues to rise to +1.5 volts, only NMOS transistor 92 conducts. Because PMOS transistor 88 and NMOS transistor 92 do not conduct at the same time while the voltage at input node 104 swings between 0 and +1.5 V, the excessive power consumption of known inverter stages is eliminated. Additionally, operating these transistors at a low voltage means less charge is needed to charge and discharge the gates, thus further reducing power consumption. The logic of timing signal generator 34 also operates at low voltage to save power.
- FIG. 5 is a schematic diagram of a particular embodiment of low voltage generator 24 .
- a very narrow, very long channel, and thus weak, PMOS transistor 100 has a source terminal 102 coupled to (V cc ), a drain terminal 104 coupled to a node 108 , and a gate terminal 112 coupled to (V ss ).
- a moderately wide, short channel NMOS transistor 114 has a gate terminal 118 and drain terminal 122 together coupled to node 108 and a source terminal 126 coupled to a node 130 .
- Another similar NMOS transistor 134 has a gate terminal 138 and a drain terminal 142 together coupled to node 130 and a source terminal 144 coupled to a node 148 .
- a moderately wide, short channel PMOS transistor 152 has a source terminal 164 coupled to node 148 and to its N Well (schematically represented by a line 168 ).
- a gate terminal 154 and a drain terminal 158 of PMOS transistor 152 is coupled to a node 162 which, in turn, is coupled to (V ss ).
- transistors 100 , 114 , 134 and 152 form a voltage divider.
- Transistor 100 provides a very small current through diode-connected transistors 114 , 134 and 152 , each of which support this small current with a voltage slightly over that transistor's threshold voltage. Therefore, the voltage at node 162 is 0 volts, the voltage at node 148 is
- a wide, short channel NMOS transistor 170 has a gate terminal 174 coupled to node 108 , a drain terminal 178 coupled to (V cc ), and a source terminal 180 coupled to bus 32 .
- Transistor 170 is connected as a source follower, so the voltage on bus 32 is one NMOS threshold voltage below the voltage on node 108 .
- the voltage on bus 32 is
- oscillator 28 may malfunction if, for example, NMOS transistor 92 is in depletion mode with a negative threshold voltage. This could happen only in the absence of a negative substrate voltage; that is before the pump establishes the negative substrate bias. Consequently, an alternative embodiment of low voltage power supply 24 shown in FIG. 6 may be employed to ensure proper operation of oscillator 28 .
- the only difference between the circuit shown in FIG. 6 and the one shown in FIG. 5 is the addition of a moderately wide, short channel PMOS transistor 200 disposed between node 162 and (V ss ). As shown in FIG.
- PMOS transistor 200 has a gate terminal 204 coupled to the substrate (designated by the substrate voltage (V bb )), a source terminal 208 coupled to node 162 and to its N Well (represented by a line 212 ), and a drain terminal 216 coupled to (V ss ).
- the gate of PMOS transistor 200 is equal to 0 volts, and the current through transistor 200 causes node 162 to be one PMOS threshold voltage above V ss .
- the voltage at node 108 is
- +(V tn ) on bus 32 This higher voltage is sufficient to ensure proper operation of each oscillator stage, even if the NMOS transistors have a slightly negative threshold voltage.
- source follower PMOS transistor 200 pulls node 162 to (V ss ). This produces the
- charge pumping is often accomplished using two separate charge pumps.
- a smaller charge pump consuming lower power is activated during periods of low substrate current, and both it and a larger charge pump is activated during periods of high substrate current.
- the smaller charge pump is used when the memory is in standby mode, and both pumps are used whenever the memory is in an active cycle, i.e., read or write.
- the present invention employs a single charge pump, such that both the pump current into the substrate, as well as the current consumed by the pump may be controlled by varying the frequency of oscillator 28 .
- oscillator 28 During standby, oscillator 28 generates a relatively low frequency (e.g., ⁇ 200 KHz) oscillator signal (see FIG. 7) so that all components in the system consume low power.
- the substrate voltage is compared to the reference voltage once per cycle (e.g., at the leading edge of each cycle as shown). As long as the substrate voltage is at or below the desired negative substrate bias voltage, oscillator 28 continues operating at this low frequency.
- oscillator 28 switches to a higher frequency (e.g., ⁇ 20 MHz) via the signals on SPUMP line 70 and NSPUMP line 72 as discussed below.
- a single pump activating positive pulse is generated by comparator 56 on bus 68 so that charge pump 80 may execute a single pumping cycle as discussed above for FIG. 1.
- the comparison function still occurs on the leading edge of each oscillator signal, and a corresponding pump activating signal is generated each time comparator 56 determines pumping is required.
- comparator 56 determines pumping is no longer needed, it issues the appropriate signals on SPUMP line 70 and NSPUMP line 72 to cause oscillator 28 to return to the low frequency, low power mode.
- oscillator 28 also operates at the higher frequency whenever the associated circuit operates in a mode typically associated with high substrate current (e.g., when a DRAM; is in an active cycle) whether or not pumping is actually required. Pumping thus occurs on an as-needed basis, and the high frequency mode of oscillator 28 allows charge pump 80 to accommodate high substrate current conditions.
- Dual frequency operation of oscillator 28 is accomplished by adding transistors 210 , 214 , 218 , and 222 as shown in FIG. 8 to the basic oscillator structure shown in FIG. 4.
- Each of the transistors 210 , 214 , 218 and 222 is moderately narrow, short channel PMOS transistor transistors.
- 210 has a source terminal 228 coupled to source terminal 94 of PMOS transistor 88 (which, in this embodiment, is a very narrow, long channel transistor), a gate terminal 230 coupled to SPUMP (Slow Pump) line 70 , and a drain terminal 232 coupled to a node 234 .
- PMOS transistor 214 has a source terminal 236 coupled to node 234 , a gate terminal 240 coupled to gate terminal 102 of PMOS transistor 88 , and a drain terminal 244 coupled to node 106 .
- NMOS transistor 218 has a drain terminal 250 coupled to node 106 , a gate terminal 254 coupled to gate terminal 110 of NMOS transistor 92 (which, in this embodiment, is a very narrow, long channel transistor), and a source terminal 258 coupled to a node 260 .
- NMOS transistor 222 has a drain terminal 264 coupled to node 260 , a gate terminal 268 coupled to NSPUMP (Not Slow Pump) line 72 , and a source terminal 272 coupled to (V ss ).
- the signals on lines 70 and 72 are complementary signals and occur so that either transistors 210 and 222 are simultaneously on or simultaneously off.
- Oscillator 28 operates at a lower frequency determined by the very high resistances of transistors 88 and 92 whenever transistors 210 and 222 are off, and oscillator 28 operates at a much higher frequency determined by the much lower combined resistances of transistors 88 , 92 , 214 , 218 , 210 , and 222 whenever transistors 210 and 222 are on.
- High frequency operation occurs because the relatively wide, short channel (low resistance) transconductance transistors 214 and 218 provide high current and pull node 106 high and low much faster than the relatively narrow, very long channel (high resistance) transconductance transistors 88 and 92 .
- the high frequency is perhaps 20 MHz and the low frequency is perhaps 200 KHz.
- initially oscillator 28 operates in the low frequency mode.
- comparator 56 detects the substrate voltage being above the desired negative bias voltage level, and during periods of possibly high substrate current, the signals are provided on SPUMP line 70 and NSPUMP line 72 for turning transistors 210 and 222 on. This causes the oscillator signal to occur at a much higher frequency as shown by the center portion of the wave-form in FIG. 7 (not to scale), and with a smooth transition between the low and high frequency modes.
- the signals are provided on SPUMP line 70 and NSPUMP line 72 for turning transistors 210 and 222 off. Oscillator 28 then reverts to its low frequency mode, again with a smooth transition between the modes.
- FIG. 9 is a schematic diagram showing the construction of timing signal generator 34 and how it is coupled to dual frequency oscillator 28 . To save power, all of the circuitry shown in FIG. 9 operates preferably from the reduced power supply voltage provided by low voltage generator 24 .
- Timing signal generator 34 includes an inverter 300 having an input terminal coupled to the output terminal of inverter 84 A in oscillator 28 and an output terminal coupled to an input terminal of an inverter 304 .
- the output terminal of inverter 304 is coupled to one input terminal of a 2-input NAND gate 308 .
- the other input terminal of NAND gate 308 is coupled to the output terminal of an inverter 312 which, in turn, has an input terminal coupled to an output terminal of inverter 84 C in oscillator 28 .
- an inverter 316 has an input terminal coupled to the output terminal of inverter 84 B in oscillator 28 and an output terminal coupled to an input terminal of an inverter 320 .
- the output terminal of inverter 320 is coupled to one input terminal of a 2-input NAND gate 324 .
- the other input terminal of NAND gate 324 is coupled to an output terminal of an inverter 328 which, in turn, has an input terminal coupled to an output terminal of inverter 84 D in oscillator 28 .
- the output terminal of NAND gate 308 is coupled to an input terminal of an inverter 332 , to one input terminal of a 2-input NAND gate 310 , and to one input terminal of a 2-input NAND gate 356 .
- the output terminal of inverter 332 is coupled to an input terminal of an inverter 336 which has an output terminal connected to an input terminal of an inverter 340 .
- An output terminal of inverter 340 is coupled to an input terminal of an inverter 344 which has an output terminal coupled to an input terminal of an inverter 348 .
- An output terminal of inverter 348 is coupled to an input terminal of an inverter 352 which has an output terminal coupled to the other input terminal of NAND gate 356 and to an “X” signal line 354 .
- An output terminal of NAND gate 356 is coupled to a input terminal of an inverter 360 which has an output terminal coupled to an input terminal of an inverter 364 .
- An output terminal of inverter 364 is coupled to a “Y” signal line 368 .
- An output terminal of NAND gate 310 is coupled to one input terminal of a 2-input NAND gate 370 and to an input terminal of an inverter 374 .
- the other input terminal of NAND gate 370 is coupled to an output terminal of NAND gate 324 .
- An output terminal of inverter 374 is coupled to an input terminal of an inverter 378 , and an output terminal of inverter 378 is coupled to a “Z” signal line 382 .
- An output terminal of NAND gate 370 is coupled to the other input terminal of NAND gate 310 and to an input terminal of an inverter 390 .
- An output terminal of inverter 390 is coupled to an input terminal of an inverter 394 , and an output terminal of inverter 394 is coupled to a “W” signal line 398 .
- “X” signal line 354 , “Y” signal line 368 , “Z” signal line 382 , and “W” signal line 398 together comprise bus 48 (FIG. 2).
- FIG. 10 is a timing diagram showing the sequence of signals on “X” signal line 364 , “Y” signal line 368 , “Z” signal line 382 , and “W” signal line 398 , respectively.
- the signals on the “X” signal line 354 and on the “Y” signal line 368 are complimentary, but with timing such that the signal on “X” signal line 354 goes high before the signal on “Y” signal line 368 goes low and vice versa.
- the signals on “Z” signal line 382 and “W” signal line 398 that is, the signals on the lines each have a high portion (+1.5 volts) and a low portion (0 volts), and the low portions of the signals are mutually exclusive.
- FIG. 13 is a schematic diagram of a particular embodiment of logic voltage level translator 40 .
- “X” signal line 354 , Y signal line 368 , “W” signal line 398 and “Z” signal line 382 are received from timing signal generator 34 .
- the logic voltage level translator receives logic input signals “X”, “Y”, “W” and “Z”, in which the low logic level is V ss (0 volts) and the high logic level is about 1.5 volts. Its purpose is to provide output signals which switch between V ss and V cc .
- NMOS transistor 450 functioning as a capacitor, has both its source and drain terminals connected to “X” signal line 354 and its gate terminal 461 connected to a node 488 .
- NMOS transistor 452 also functioning as a capacitor, has both its source and drain terminals connected to “Y” signal line 368 and its gate terminal 463 connected to a node 440 .
- NMOS transistor 454 also functioning as a capacitor, has both its source and drain terminals connected to “W” signal line 398 and its gate terminal connected to a node 650 .
- NMOS transistor 456 also functioning as a capacitor, has both its source and drain terminals connected to “Z” signal line 382 and its gate terminal 560 connected to a node 652 .
- a PMOS transistor 460 has a source terminal 464 coupled to (V cc ), a drain terminal 468 coupled to another terminal 461 of capacitance 450 and a gate terminal 472 coupled to node 490 .
- a PMOS transistor 476 has a source terminal 480 coupled to (V cc ), a drain terminal 484 coupled to node 490 and a gate terminal 482 coupled to node 488 .
- An NMOS transistor 500 has a drain terminal 504 coupled to (V cc ), a source terminal 508 coupled to node 488 and a gate terminal 512 coupled to a (V cc ⁇
- an NMOS transistor 520 has a drain terminal 524 coupled to (V cc ), a source terminal 528 coupled to node 490 , and a gate terminal 532 coupled to the (V cc ⁇
- a PMOS transistor 550 has a source terminal 554 coupled to (V cc ), a gate terminal 558 coupled to node 652 , and a drain terminal 564 coupled to node 650 .
- a PMOS transistor 572 has a source terminal 574 coupled to (V cc ), a drain terminal 576 coupled to node 652 , and a gate terminal 580 coupled to node 650 .
- An NMOS transistor 600 has a drain terminal 604 coupled to (V cc ), a source terminal 608 coupled to node 650 , and a gate terminal 612 coupled to the (V cc ⁇
- An NMOS transistor 630 has a drain terminal 634 coupled to (V cc ), a source terminal 638 coupled to node 652 , and a gate terminal 642 coupled to the (V cc ⁇
- a PMOS transistor 660 has a source terminal 664 coupled to (V cc ), a drain terminal 668 coupled to a node 672 , and a gate terminal 676 coupled to node 488 .
- An NMOS transistor 680 has a drain terminal 684 coupled to node 672 , a source terminal 688 coupled to (V ss ), and a gate terminal 692 coupled to “X” signal line 354 .
- Node 672 is coupled to an input terminal of an inverter 700 having an output terminal coupled to an input terminal of an inverter 704 .
- An output terminal of inverter 704 is coupled to a line 706 which provides signals to substrate voltage translator 44 .
- a PMOS transistor 710 has a source terminal 714 coupled to (V cc ), a drain terminal 718 coupled to a node 720 , and a gate terminal 724 coupled to node 490 .
- An NMOS transistor 730 has a drain terminal 734 coupled to node 720 , a source terminal 738 coupled to (V ss ), and a gate terminal 742 coupled to “Y” signal line 368 .
- Node 720 is coupled to an input terminal of an inverter 750 which has an output terminal coupled to an input terminal of an inverter 754 .
- An output terminal of inverter 754 is coupled to a line 760 which provides signals to substrate voltage translator 44 .
- Lines 650 , 706 , and 760 together comprise bus 50 (FIG. 2).
- the function of the part of the logic voltage level translator 40 shown in the left hand part of FIG. 13 is to generate signals that transition from V ss to V cc on nodes 706 and 760 from the low voltage signals “X” and “Y” on signal lines 354 and 368 , respectively.
- the function of the remainder of the logic voltage level translator 40 is to generate a signal on node 650 that transitions between V cc ⁇ 1.5 volts and V cc from the low voltage signals “W” and “Z”.
- Both the left and right portions of the circuitry of FIG. 13 work in the same manner. Nodes “X” on signal line 354 and “Y” on signal line 368 transition between V ss (0 volts) and 1.5 volts, and are generally complements of one another.
- timing signal generator 34 of FIG. 2 shown in detail in FIG. 9 provides that node “X” will transition high before mode “Y” transitions low and that node “Y” will transition high before node “X” transitions low, as seen in FIG. 10.
- capacitor (NMOS transistor) 452 drives node 490 low turning on PMOS transistor 460 , and pulling node 488 to V cc .
- node “X” is high at +1.5 volts
- capacitor 450 is charged to 3.5 volts.
- node “Y” transitions high to +1.5 volts, capacitor 452 drives node 490 high, turning off PMOS transistor 460 , but with node 488 remaining at V cc .
- node “X” transitions low from 1.5 volts to 0 volts and capacitor 450 drives node 488 down by 1.5 volts to 1.5 volts below V cc , turning on PMOS transistor 476 .
- node 488 is again returned to V cc , turning off PMOS transistor 476 , but with node 490 remaining at V cc . This completes one full cycle.
- V cc a high level of V cc exists on node 488 when node “X” is high at +1.5 volts and a low level of V cc ⁇ 1.5 volts exists on node 488 when node “X” is at a low level of 0 volts.
- NMOS transistor 680 is on and pulls the input of inverter 700 to 0 volts.
- node 488 is at V cc so PMOS transistor 660 is off and no current flows through transistors 660 and 680 .
- node 488 When node “X” is low at 0 volts, node 488 is low at V cc ⁇ 1.5 volts, turning on PMOS transistor 660 and pulling the input of inverter 700 to V cc . At this time, NMOS transistor 680 is off and again no current flows through transistors 660 and 680 .
- this circuitry generates on the input of inverter 700 a full logic swing between V ss and V cc from low level inputs on nodes “X” and “Y”, and does so without establishing any current path from V cc to V ss .
- output 706 of the logic voltage level translator of FIG. 13 is a high level compliment of the low level signal on node “X”. If node “X” instead went directly to a normal inverter whose PMOS source voltage was +5 volts, the inverter would consume substantial power whenever node “X” is at +1.5 volts. In an identical manner, the low-level signal on node “Y” generates its compliment as a high level signal on node 760 .
- NMOS transistors 500 and 520 are used to start the circuit when power is first applied, and are not needed or functional thereafter. Each establishes a voltage of at least V cc ⁇
- ⁇ Vtn V cc ⁇ 1.15 volts on its respective node 488 or 490 , sufficient to establish a channel in each of NMOS transistors (capacitors) 450 and 452 , which in turn causes the circuit to function as described above.
- the circuitry on the right side of FIG. 13 translates the 0 to +1.5 volt logic levels on node “W” to V cc ⁇ 1.5 to V cc volt logic levels on node 650 . These levels on node 650 will be used to turn on or off a PMOS transistor whose source is at V cc .
- This circuitry functions in an identical manner to the corresponding portions of the circuitry on the left side of FIG. 13 already described.
- Voltage comparator 300 includes a very narrow, very long channel PMOS transistor 304 having a source terminal 308 coupled to (V cc ), a gate terminal 312 coupled to (V ss ), and a drain terminal 316 coupled to a node 320 .
- Transistor 304 functions as a very high resistance or very low current source.
- An NMOS transistor 324 has a drain terminal 328 coupled to node 320 , a gate terminal 332 coupled to a reference voltage V ref (typically ground), and a source terminal 336 coupled to a node 340 .
- An NMOS transistor 344 has a drain terminal 348 and a gate terminal 352 together coupled to node 340 , and a source terminal 356 coupled to a node 360 .
- an NMOS transistor 364 has a drain terminal 368 and a gate terminal 372 together coupled to node 360 , and a source terminal 376 coupled to the substrate V bb . All the NMOS transistors, 324 , 344 , and 364 are relatively wide, short channel transistors.
- V bb is less than (more positive voltage than) 3 NMOS threshold voltages below V ref (ground)
- diode connected transistors 364 and 344 cannot pull node 340 low enough to cause conduction through transistor 324 .
- This V cc level on node 320 is the other logic state for the output on node 320 , signifying that pumping is necessary.
- the signal at node 320 is communicated to the charge pump.
- the charge pump turns on for transferring charge to the substrate when node 320 is at (V cc ) volts, and the charge pump is turned off when node 320 is at V bb +2(V tn ).
- V bb is low enough to turn off the charge pump, there is current flowing through comparator 300 into the substrate.
- the comparator 300 itself causes a substrate current which must be pumped away.
- the substrate voltage comparison circuitry according to the present invention avoids this problem.
- FIG. 12 is a conceptual schematic diagram of a particular embodiment of substrate voltage comparison circuitry according to the present invention.
- a switch 400 is coupled between ground (V ss ) and a terminal 404 of a capacitance C 2 .
- a switch 408 is coupled between the substrate voltage V bb and a terminal 412 of capacitance C 2 .
- a switch 414 is coupled between the power supply voltage (V cc ) and terminal 404 of capacitance C 2 , and one input terminal 418 of comparator 56 is coupled to terminal 412 of capacitance C 2 via bus 58 .
- the other input terminal of comparator 56 is coupled to reference voltage (V ref ) through bus 60 .
- switch and capacitance circuitry shown in FIG. 12 The purpose of the switch and capacitance circuitry shown in FIG. 12 is to translate the substrate voltage V bb to a level which may be compared by comparator 56 . Initially, switches 400 and 408 are closed for charging capacitance C 2 to a voltage equal to (V ss ⁇
- V cc equals +5 volts
- V bb is more positive than ⁇ 5 volts
- the voltage on bus 58 is now a positive voltage which may be conveniently compared by comparator 56 .
- switch 414 is opened and switch 400 is closed.
- Terminal 404 of capacitance C 2 falls to V ss
- terminal 412 falls to V bb .
- Switch 408 then may be closed with no transfer of charge to or from the substrate. The circuit thus operates without the disadvantage discussed for known comparators.
- FIG. 14 is a schematic diagram of a particular embodiment of substrate voltage translator 44 and comparator 56 .
- Voltage level translator 44 corresponds to the switch and capacitor of FIG. 12, while comparator 56 of FIG. 14 more or less corresponds to comparator 56 of FIG. 12.
- line 760 is coupled to source and drain terminals of PMOS transistors functioning as capacitances 804 and 812 .
- line 706 is coupled to source and drain terminals of a PMOS transistor functioning as a capacitance 820 .
- An NMOS transistor 830 has a drain terminal 834 coupled to a gate terminal 838 of capacitance 812 , a source terminal 842 coupled to the substrate V bb , and a gate terminal 846 coupled to a gate terminal 850 of capacitance 820 .
- An NMOS transistor 854 has a drain terminal 858 coupled to gate terminal 850 of capacitance 820 , a source terminal 862 coupled to V bb , and a gate terminal 866 coupled to gate terminal 838 of capacitance 812 .
- the circuit described thus far operates in the same manner as in the circuit shown in FIG. 13 except all polarities are reversed.
- the voltage on gate terminals 838 and 850 swing between V bb and V bb +V cc volts as nodes 760 and 706 swing between V ss (0 volts) and V cc . That is, when terminal 838 is high as a result of a high (e.g., +5 volts) signal on line 760 , transistor 854 turns on pulling gate terminal 850 to V bb during which time the signal on line 706 is low. Thereafter, the signal on line 760 goes low turning off transistor 854 . Then when the signal on line 706 goes high (e.g., +5 volts), the voltage on gate terminal 850 rises to V bb +5 volts, turning on transistor 830 and pulling gate terminal 838 to V bb .
- a high e.g., +5 volts
- An NMOS transistor 880 has a drain terminal 884 coupled to a gate terminal 888 of capacitance 804 and to a node 885 , a source terminal 892 coupled to a node 896 , and a gate terminal 900 coupled to gate terminal 850 of capacitance 820 .
- Another NMOS transistor 904 has a drain terminal 908 coupled to node 896 , a source terminal 912 coupled to V bb , and a gate terminal 916 coupled to gate terminal 850 of capacitance 820 .
- an NMOS transistor 930 has a drain terminal 934 coupled to V cc , a source terminal 938 coupled to node 896 , and a gate terminal 942 coupled to node 885 .
- the switches and capacitor of FIG. 12 correspond to the following transistors of FIGS. 13 and 14.
- Switches 400 and 414 of FIG. 12 correspond to the NMOS and PMOS transistors respectively of inverter 754 of FIG. 13 which generates node 760 .
- Capacitor CZ of FIG. 12 corresponds to capacitor (PMOS transistor) 804 of FIG. 14.
- Switch 408 of FIG. 12 corresponds to the series combination of NMOS transistors 880 and 904 of the substrate voltage translator 44 in FIG. 14.
- the translated substrate voltage on bus 58 of FIG. 12 corresponds to the translated substrate voltage bus 58 of FIG. 14.
- the voltages on the gate terminals of capacitors (PMOS transistors) 812 and 820 alternate between V bb and (V bb +V cc ).
- node 706 When node 706 is high, node 760 is low.
- gate terminal 850 of capacitor 850 is at (V bb +V cc ), turning on transistors 880 and 904 , pulling node 885 to V bb .
- node 706 goes low, the gate terminal 850 of capacitor 820 returns to V bb , and transistors 880 and 904 hopefully turn off.
- NMOS transistor 904 has its source at V bb and has no back bias or body effect to raise its threshold voltage as do NMOS transistors whose source is at V ss , well above the V bb potential. Without any body effect, transistor 904 may not shut off completely.
- Transistors 880 and 930 are included to prevent this problem from leaking charge off node 885 .
- source follower NMOS transistor 930 pulls node 896 up to a voltage of [(V bb +V cc ) ⁇ V tn] .
- Transistor 880 with its source 892 well above V bb and its gate 900 at V bb , is fully off and has totally negligible leakage current. Therefore as node 885 rises to (V bb +V cc ), its level remains intact, and substrate voltage translator 44 provides a voltage level of (V bb +V cc ) into comparator 56 .
- the reference voltage V ref on bus 60 into comparator 56 of FIG. 14 may be generated by a simple capacitive divider (not shown). If, for example, two capacitors are in series between ground and a node that switches from ground to V cc , the intermediate node (between the capacitors) will switch by a fraction of V cc depending on the ratio of the capacitances. The intermediate node is discharged to ground (by an NMOS transistor) when the switching node is at ground. Thus the voltage on the intermediate node switches up to a fraction of V cc depending on the capacitance ratio. This reference voltage is compared to the (V bb +V cc ) voltage provided by substrate voltage translator 44 .
- this intermediate node voltage is V cc /2.
- the translated substrate voltage signal on bus 58 is communicated to comparator 56 where it is compared to the reference voltage V ref received on bus 60 .
- the comparison is triggered by the signals on “W” signal line 398 from timing signal generator 34 .
- the W signals occur once per oscillator cycle to provide the once-per-cycle comparison discussed above. If the substrate voltage is more positive than the reference voltage, then a pump activating signal in the form of a positive pulse appears on line 68 .
- the differential SPUMP/NSPUMP signals are generated on SPUMP signal line 70 and NSPUMP signal line 72 upon each comparison and remain valid until the next cycle.
- the SPUMP/NSPUMP signals control PMOS transistor 210 and NMOS transistor 222 , respectively, in each oscillator stage (FIG. 8) for setting the oscillator frequency.
- NMOS transistor 1004 has a source terminal 1008 coupled to V ss and a drain terminal 1012 coupled to a node 1016 .
- Node 1016 is, in turn, coupled to a source terminal 1020 of an NMOS transistor 1024 and to a source terminal 1028 of an NMOS transistor 1032 .
- a gate terminal 1036 of NMOS transistor 1024 is coupled for receiving the reference voltage V ref (which may be generated via a capacitive divider coupled between V cc and V ss as previously discussed) on bus 60 , and a gate terminal 1040 of NMOS transistor 1032 is coupled for receiving the translated substrate voltage on bus 58 .
- NMOS transistor 1024 has a drain terminal 1044 coupled to a source terminal 1048 of an NMOS transistor 1052 .
- NMOS transistor 1052 has a gate terminal 1056 coupled to a node 1060 and a drain terminal 1064 coupled to a node 1068 .
- Node 1068 is coupled to a drain terminal 1072 of a PMOS transistor 1076 and to a drain terminal 1080 of a PMOS transistor 1084 .
- a gate terminal 1088 of PMOS transistor 1076 is coupled to line 650 , and a gate terminal 1092 of transistor 1084 is coupled to node 1060 .
- a source terminal 1096 of transistor 1076 and a source terminal 1100 of transistor 1084 are both coupled to V cc .
- a drain terminal 1104 of transistor 1032 is coupled to a source terminal 1108 of an NMOS transistor 1112 .
- NMOS transistor 1112 has a gate terminal 1116 coupled to a node 1120 (which is coupled to node 1068 ) and a drain terminal 1124 coupled to a node 1128 (which is coupled to node 1060 ).
- Node 1128 is coupled to a drain terminal 1132 of a PMOS transistor 1136 and to a drain terminal 1140 of a PMOS transistor 1144 .
- a gate terminal 1148 of PMOS transistor 1136 is coupled to node 1120 , and a gate terminal 1152 of PMOS transistor 1144 is coupled to line 650 .
- a source terminal 1156 of transistor 1136 and a source terminal 1160 of transistor 1144 are both coupled to V cc .
- Node 1128 is coupled to an input terminal of an inverter 1180 which has an output terminal coupled to bus 68 and to an input terminal of a 2-input NOR gate 1188 .
- node 1068 is coupled to an input terminal of an inverter 1192 which has an output terminal coupled to an input terminal of a 2-input NOR gate 1200 .
- An output terminal of NOR gate 1188 is coupled to another input terminal of NOR gate 1200 , and an output terminal of NOR gate 1200 is coupled to another input terminal of NOR gate 1188 .
- NOR gates 1188 and 1200 thus function as a latch so that the signals at the output terminals of inverters 1180 and 1192 are maintained until the next comparison function.
- the output terminal of NOR gate 1200 is coupled to an input terminal of a 2-input NOR gate 1204 .
- Another input terminal of NOR gate 1204 is coupled for receiving an active high DRAM RAS signal.
- the output terminal of NOR gate 1204 is coupled to SPUMP (Slow Pump) signal line 70 and to an input terminal of an inverter 1208 .
- An output terminal of inverter 1208 is coupled to NSPUMP signal line 72 .
- node 650 from logic voltage level translator 40 in FIG. 13 switches between V cc ⁇ 1.5 volts and V cc as node “W” switches between 0 volts V ss and +1.5 volts, respectively.
- comparator 56 in FIG. 14 Between sensing cycles node “W” is low, and NMOS transistor 1004 is off. At this time, signal 650 is also low and PMOS transistors 1076 and 1144 are on, charging nodes 1068 and 1128 up to V cc . No current is drawn during this time because there is no conductive path to V ss .
- node 650 When signal “W” transitions high (to +1.5 volts) node 650 also transitions high (to V cc ).
- NMOS transistors 1076 and 1144 turn off. As NMOS transistor 1004 turns on, node 1016 transitions low. If the translated substrate voltage (V bb +V cc ) on bus 58 is at a higher voltage than V ref , transistor 1032 starts to conduct before transistor 1024 , since their source terminals are connected together. As transistor 1032 conducts, its drain 1104 discharges toward ground faster than the drain of transistor 1024 discharges toward ground. Preceding this, nodes 1068 and 1128 (the gate connections of transistors 1112 and 1052 ) were each at the same voltage, V cc .
- transistor 1112 conducts pulling node 1128 to ground. This turns off NMOS transistor 1052 preventing it from pulling node 1068 to ground while turning on PMOS transistor 1084 to maintain node 1068 at V cc .
- node 1128 goes to ground while node 1068 remains at V cc .
- the output of inverter 1180 goes high (to V cc . Note that after this initial switching transient but with nodes W and 650 still high, there is again no current path.
- a positive pulse on “W” (and on bus 650 ), when node 58 is above V ref , causes a positive pulse on node 68 while the output of inverter 1192 remains at ground.
- This positive pulse indicates pumping is required. (The translated substrate voltage is too positive.)
- This pulse does two things. First it provides a single pump cycle on node 68 delivered to the charge pump itself which will be described below. And second, it sets a flip flop comprised of NOR gates 1188 and 1200 into the appropriate state to insure the oscillator will operate at high frequency.
- the oscillator stage of FIG. 8 when transistors 210 and 222 of the oscillator stage of FIG. 8 are turned on, the oscillator operates at high frequency which in turn permits high pumping current. When these transistors are off, the oscillator operates at a much lower frequency, as does the logic voltage level translator 40 of FIG. 13, the substrate voltage translator 44 of FIG. 14 and the comparator 56 of FIG. 14.
- the low frequency operation of approximately 200 kilohertz, with much of the circuitry operating from a 1.5 volt supply, permits the pump to consume less than 1 microamp of total current when no pumping is required. Yet when pumping is required, the circuit automatically switches to high frequency, and at high frequency is capable of pumping more than 1 milliamp of current out of the substrate.
- FIG. 15 is a schematic diagram of a particular embodiment of pump signal generator 64 .
- the pump signal received on bus 68 is coupled to an input terminal of an inverter 1300 which has an output terminal coupled to an input terminal of an inverter 1304 .
- An output terminal of inverter 1304 is coupled to an input terminal of an inverter 1308 , to an input terminal of an inverter 1312 , and to an input terminal of an inverter 1316 .
- An output terminal of inverter 1308 is coupled to an input terminal of an inverter 13 20 .
- An output terminal of inverter 1320 is coupled to an input terminal of an inverter 1328 , to an input terminal of an inverter 1332 , and to an input terminal of an inverter 1336 .
- An output terminal of inverter 1328 is coupled to an input terminal of an inverter 1340 .
- a n output terminal of inverter 1340 is coupled to an input terminal of an inverter 1344 , to an input terminal of an inverter 1348 , and to an input terminal of an inverter 1352 .
- An output terminal of inverter 134 8 is coupled to an input terminal of inverter 1356 , and the output terminal of an inverter 13 56 is coupled to an input terminal of an inverter 1360 .
- An output terminal of inverter 1344 is coupled to an input terminal of an inverter 1364 .
- An output terminal of inverter 1364 is coupled to an input terminal of an inverter 1368 and to an input terminal of an inverter 1372 .
- An output terminal of inverter 1368 is coupled to an input terminal of an inverter 1376 , and an output terminal of inverter 1376 is coupled to an input terminal of an inverter 1380 .
- An output terminal of inverter 1380 is coupled to one input of a 2-input NAND gate 1384 .
- Another input terminal of NAND gate 1384 is coupled to an output terminal of inverter 1312 .
- An output terminal of NAND gate 1384 is coupled to an input terminal of an inverter 1388 , and an output terminal of inverter 1388 is coupled to a “D” signal line 1392 .
- An output terminal of inverter 1316 is coupled to an input terminal of a 2-input NAND gate 1396 .
- Another input terminal of NAND gate 1396 is coupled to an output terminal of a inverter 1372 .
- An output terminal of NAND gate 1396 is coupled to an input terminal of an inverter 1400 , and an output terminal of inverter 1400 is coupled to an input terminal of an inverter 1404 .
- An output terminal of inverter 1404 is coupled to an “A” signal line 1408 .
- An output terminal of inverter 1360 is coupled to an input terminal of a 2-input NAND gate 1412 .
- Another input terminal of NAND gate 1412 is coupled to an output terminal of inverter 1332 .
- An output terminal of NAND gate 1412 is coupled to an input terminal of an inverter 1416 , and an output terminal of inverter 1416 is coupled to a “B” signal line 1420 .
- An output terminal of inverter 1352 is coupled to an input terminal of a 2-input NAND gate 1424 .
- Another input terminal of NAND gate 1424 is coupled to an output terminal of inverter 1336 .
- An output terminal of NAND gate 1424 is coupled to an input terminal of an inverter 1428 , and an output terminal of inverter 1428 is coupled to an input terminal of an inverter 1432 .
- An output terminal of inverter 1432 is coupled to a “C” signal line 1436 .
- the various number of inverters in each of the logic paths to generate each of the signals “A”, “B”, “C”, and “D” are chosen to insure that when node 68 transitions high, node “D” transitions low before node “C” transitions high and that when node 68 transitions low, node “C” transitions low before node “D” transitions high. See FIGS. 15 and 16. Furthermore node “A” transitions high before node “B” transitions low and node “B” transitions high before node “A” transitions low. Also, node “D” transitions low before node “B” transitions low and node “B” transitions high before node “D” transitions high.
- node 68 When no pumping is required, node 68 remains as low as previously discussed, and nodes “A”, “B”, “C” and “D” don't move.
- comparator 56 determines that a pump cycle is required, nodes 68 , “A”, “B”, “C”, and “D” execute a single pump cycle with the relative timing indicated in FIG. 16.
- FIG. 17 is a schematic diagram of a particular embodiment of charge pump 80 .
- “A” signal line 1408 is coupled to a terminal 1450 of a capacitance 1454
- “B” signal line 1420 is coupled to a terminal 1458 of a capacitance 1462 .
- Capacitances 1454 and 1462 each comprise a PMOS transistor having its source and drain terminals coupled together.
- a gate terminal 1550 of capacitance 1454 is coupled to a gate terminal 1554 of a PMOS transistor 1558 .
- PMOS transistor 1558 has a source terminal 1562 coupled to V ss and a drain terminal 1566 coupled to a gate terminal 1570 of a PMOS transistor 1574 and to a gate terminal 1578 of capacitance 1462 .
- PMOS transistor 1574 has a source terminal 1582 coupled to V ss and a drain terminal 1586 coupled to gate terminal 1554 of transistor 1558 .
- the signals on “A” signal line 1408 and “B” signal line 1420 swing from 0 volts to +5 volts
- the signals on terminals 1550 and 1578 swing from ⁇ 5 volts to 0 volts, respectively.
- Capacitances 1478 and 1494 each comprise a PMOS transistor having its source and drain terminals coupled together.
- a gate terminal 1628 of capacitance 1478 is coupled to a gate terminal 1632 of an NMOS transistor 1636 .
- NMOS transistor 1636 has a source terminal 1668 coupled to V bb and a drain terminal 1664 coupled to a gate terminal 1652 of an NMOS transistor 1644 and to a gate terminal 1660 of capacitance 1494 .
- NMOS transistor 1644 has a source terminal 1648 coupled to V bb and a drain terminal 1640 coupled to gate terminal 1628 of capacitance 1478 .
- the signals on “D” signal line 1392 and “C” signal line 1436 swing from 0 volts to + 5 volts
- the signals on terminals 1628 and 1660 swing from V bb volts to V bb +5 volts, respectively.
- a capacitance 1524 has one terminal 1520 coupled to a node 1508 and a gate terminal 1604 coupled to a node 1610 .
- Capacitance 1524 comprises a PMOS transistor having its source and drain terminals coupled together, and it functions as capacitance C 1 in FIG. 1.
- a PMOS transistor 1470 has a source terminal 1500 coupled to V cc , a gate terminal 1466 coupled to “B” signal line 1420 , and a drain terminal 1504 coupled to node 1508 .
- PMOS transistor 1470 functions as switch 4 in FIG. 1. It turns on when “B” signal line 1420 is at 0 volts and turns off when “B” signal line is at +5 volts.
- a PMOS transistor 1594 has a source terminal 1598 coupled to V ss , a gate terminal 1590 coupled to gate terminal 1578 of capacitance 1462 , and a drain terminal 1602 coupled to node 1610 .
- PMOS transistor 1594 functions as switch 8 in FIG. 1. It turns on when its gate terminal 1590 is at ⁇ 5 volts and turns off when gate terminal 1590 is at 0 volts.
- a 50 micron wide NMOS transistor 1486 has a drain terminal 1512 coupled to node 1508 , a gate terminal 1482 coupled to “D” signal line 1392 , and a source terminal 1516 coupled to V ss .
- NMOS transistor 1486 functions as switch 12 in FIG. 1. It turns on when “D” signal line 1392 is at +5 volts and turns off when “D” signal line 1392 is at 0 volts.
- a 350 micron wide NMOS transistor 1612 has a drain terminal 1608 coupled to node 1610 , a gate terminal 1620 coupled to terminal 1628 of capacitance 1478 , and a source terminal 1616 coupled to V bb .
- NMOS transistor 1612 functions as switch 14 in FIG. 1. It turns on when its gate terminal 1620 is at (V bb +5) volts and turns off when its gate terminal 1620 is at V bb volts.
- a unique feature of charge pump 80 is the use of NMOS transistor 1612 as switch 14 for enabling the transfer of charge from terminal 1604 of capacitance 1524 to the substrate.
- NMOS transistor 1612 is 0.0 volts.
- V cc +5.0 volts
- V ss 0.0 volts.
- terminal 1520 of capacitance 1524 is coupled to V ss after the capacitance is charged
- terminal 1604 is driven toward ⁇ 5.0 volts.
- V bb is some voltage between 0.0 volts and ⁇ 5.0 volts.
- FIG. 18 is a schematic diagram of a known embodiment of switch 14 .
- switch 14 comprises a diode-connected NMOS transistor 1700 having a source terminal 1704 coupled to terminal 1604 of capacitance C 1 , a drain terminal 1708 coupled to the substrate V bb , and a gate terminal 1712 coupled to drain terminal 1708 .
- NMOS transistor conducts whenever the voltage on terminal 1604 is V tn below V bb .
- the source region of NMOS transistor 1700 is an N-type region located in the P-type substrate. The N-type source and P-type substrate thus form a PN junction. Therefore, as terminal 1604 becomes more negative than V bb , the PN junction becomes forward biased.
- NMOS threshold voltage V tn is very low, the forward bias of the PN diode is high enough to cause substantial injection of electrons into the P-type substrate. This increases the likelihood of latchup of CMOS devices and creates leakage of charge from the memory nodes in a DRAM. Therefore, use of NMOS transistors for switch 14 has been generally unsuccessful.
- FIG. 19 is a schematic diagram of another known embodiment of switch 14 .
- switch 14 comprises a diode-connected PMOS transistor 1750 having a drain terminal 1754 coupled to terminal 1604 of capacitance 1524 , a gate terminal 1758 coupled to drain terminal 1754 , and a source terminal 1762 coupled to V bb .
- PMOS transistor 1750 conducts whenever the voltage on terminal 1604 is one
- FIG. 20 is a schematic diagram of a possible embodiment of switch 14 which overcomes the problems noted above.
- switch 14 comprises a PMOS transistor 1780 having a first current flowing terminal 1784 coupled to terminal 1604 of capacitance 1524 , a second current flowing terminal 1788 coupled to V bb , and a gate terminal 1792 for controlling the operation of the transistor.
- V bb is at ⁇ 4.9 volts.
- first current flowing terminal 1784 functions as a drain terminal
- second current flowing terminal 1788 functions as a source terminal (since, by definition, the source is positive relative to the drain in PMOS transistors).
- 0.8 volts.
- a signal of (V bb ⁇ 0.8) volts (or more negative) must be applied to gate terminal 1792 .
- V bb ⁇ 4.9 volts
- a ⁇ 5.7 volt (or more negative) signal must be applied to gate terminal 1792 .
- first current flowing terminal 1784 functions as a source terminal
- second current flowing terminal 1788 functions as a drain terminal.
- a signal of ⁇ 0.8 volts (or more positive) must be applied to gate terminal 1792 .
- the signal generator for gate terminal 1792 must produce a signal which must vary by approximately 5 volts or more, which is difficult given a 5 volt power supply. Thus, this circuit is not widely used.
- NMOS transistor 1612 has a drain terminal 1608 coupled to terminal 1604 of capacitance 1524 , a source terminal 1616 coupled to V bb , and a gate terminal 1620 coupled to terminal 1628 of capacitance 1478 .
- Terminal 1628 of capacitance 1478 provides a signal which swings between V bb and (V bb +V cc ) for turning NMOS transistor 1612 off and on.
- NMOS transistor 1612 is substantially wider than NMOS transistor 1486 (e.g., 350 microns vs. 50 microns).
- NMOS transistor 1486 turns on.
- capacitor 1478 drives the gate terminal 1620 of NMOS transistor 1612 above the substrate voltage V bb , turning transistor 1612 on.
- the capacitance of capacitor 1478 is much larger than the gate capacitance of transistor 1612 . Therefore, at any given instant during the positive switching transition of node “D”, the gate of transistor 1612 is almost as much above V bb (the source of transistor 1612 ) as node “D” (the gate of transistor 1486 ) is above V ss (the source of transistor 1486 ).
- the threshold voltage of transistor 1486 is increased by its body effect; that is, by the fact that its source voltage (0 volts) is above its substrate voltage, V bb .
- the threshold voltage of transistor 1612 is not increased by body effect since its source is connected to the common substrate of all NMOS transistors V bb .
- the threshold voltage of transistor 1486 is greater than the threshold voltage of transistor 1612 .
- transistor 1612 starts to turn on before transistor 1486 starts to turn on because of its lower threshold voltage (assuming capacitor 1478 is large enough).
- transistor 1486 conducts a current no greater than its saturation current at that gate voltage.
- the saturation current of transistor 1486 pulls node 1508 toward 0 volts, providing a displacement current through capacitor 1524 , trying to drive node 1610 below the substrate V bb .
- transistor 1612 has close to the same gate-to-source voltage as does transistor 1486 .
- transistor 1612 is, for example, seven times as wide as is transistor 1486 (e.g., 350 microns vs. 50 microns).
- Transistor 1612 is designed to have a low resistance, by making it very wide. Its resistance is low enough that the saturation current through transistor 1486 (and through capacitor 1524 ) can only develop a voltage of about 0.3 volts across transistor 1612 . Thus, node 1610 is never driven more than 0.3 volts below the substrate voltage V bb . Although the first current flowing terminal 1608 of NMOS transistor 1612 is driven negative with respect to the substrate, forward biasing the P-N diode, the injection current is totally negligible. It takes about 0.7 volts of forward bias to get substantial current through a silicon P-N diode. Every 60 millivolts reduction in forward bias decreases the current by a factor of 10. At a forward bias of 0.3 volts, 400 mv below 0.7 volts, the current is more than one million times smaller than it would be at a forward bias at 0.7 volts.
- transistor 1612 By designing transistor 1612 to have a much greater width than that of transistor 1486 and by designing capacitor 1478 to have a much greater capacitance than that of the gate of transistor 1612 , forward bias injection current is made completely negligible. Yet, this is accomplished with the gate terminal 1620 of transition 1612 only switching from V bb to (V bb +V cc ), and without the drop of a threshold voltage across transistor 1612 .
- the lack of a threshold drop makes pump 80 substantially more efficient than prior-art pumps, using less V cc current to obtain a given substrate pump current, and achieving greater pump current for a given capacitor 1524 size.
- NMOS transistor 1612 may not completely turn off even with its gate voltage equal to its source voltage of V bb . Therefore, during standby, when no pumping is taking place, node “D” is high so that transistor 1612 is on. At this time, node “B” is high, and PMOS transistor 1594 is off with negligible leakage current, as is PMOS transistor 1470 . That is, the standby condition is that shown at the start or end of FIG. 16. The substrate is actually pumped negative after node “D”, FIG. 16, rises. Any leakage current through transistor 1612 only remains during the pump cycle pulse during which time capacitor is being charged and node “D”, FIG. 16, is low.
- a signal of (V bb +0.8) volts (or more negative) must be applied to gate terminal 1620 . That is, a voltage more positive than ⁇ 4.1 volts turns transistor 1612 on while a voltage more negative than ⁇ 4.1 volts turns it off. Thus, the voltage need not switch by an amount close to an above as was required for a PMOS transistor switch doing the job of NMOS transistor 1612 . Instead, a voltage charge less than V cc is more than adequate.
- the various innovative circuit techniques disclosed herein include: operating the pump oscillator from a reduced supply voltage to save power; increasing this reduced supply voltage level if substrate is not reasonably negative; operating the pump oscillator at a low frequency when pumping is not necessary to save power and at a high frequency when pumping may be necessary to achieve high pump current; translating the low voltage swing logic nodes to high voltage swing nodes without any power-consuming direct current paths; translating the V bb voltage up to (V bb +V cc ) with a capacitor and switches to provide for easy comparison to a reference voltage to determine if pumping is needed; employing an NMOS transistor 1612 of FIG. 17 for switch 14 of FIG.
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Abstract
Description
- 1. This invention relates to electronic circuitry and, more particularly, to a charge pump for producing a negative substrate bias in a complementary metal oxide semiconductor (CMOS) integrated circuit.
- 2. MOS transistors are commonly used in electronic circuits such as dynamic random access memories (DRAMS). In an NMOS transistor, an N-type source region is separated from an N-type drain region by a P-type channel region. All three regions are formed in a P-type semiconductor substrate. By applying a positive voltage to a gate electrode disposed above the channel region, electrons gather in the channel region between the source region and the drain region to allow current to flow from the drain region to the source region. PMOS transistors have the same structure except the conductivity types of the various regions are reversed and a negative gate voltage is required to allow current to flow from the source region to the drain region.
- 3. It has been found that NMOS transistors operate better when the P-type substrate of the NMOS (or of the NMOS transistors in a CMOS circuit) is driven negative with respect to circuit ground, in other words there is a negative substrate bias. Such a negative substrate bias provides a number of advantages in terms of the overall circuit performance. More specifically, a negative substrate bias decreases the NMOS transistor source and drain capacitance, decreases the likelihood of latchup, decreases PN diode injection when a node is driven below ground, and decreases the effective body effect, all of which are desirable in CMOS circuits.
- 4. Typically a charge pump circuit is used to create the negative substrate bias. Once a negative substrate bias is achieved, however, it does not last forever. For example, when an NMOS transistor is conductive with a relatively high drain to source voltage, some of the electrons traveling from the source region to the drain region collide with atoms in the channel region with enough energy to cause electron/hole pairs to form. The positive gate voltage attracts the generated electrons to the surface of the channel while the positive drain voltage attracts them to the drain where they simply add to the normal flow of electrons from source to drain. The positively charged holes, by contrast, are repelled by the positively charged gate away from the channel region into the substrate. The substrate current created by the excess holes makes the substrate more positively charged, thus counteracting the negative substrate bias. In DRAMS, a substantial amount of substrate current is generated whenever the memory is read or written, since many transistors are switched on and off at that time. This component of substrate current may be orders of magnitude above the background (i.e., standby) leakage current of all the reverse biased P-N diodes throughout the circuit. Therefore, the charge pump must remove low substrate current during standby and high substrate current during high activity to maintain the negative substrate bias.
- 5.FIG. 1 is a conceptual schematic diagram of a
charge pump 2 which includes a first switch 4 coupled between a positive power supply voltage (Vcc) and a first terminal 6 of a capacitance C1. A second switch 8 is coupled between a ground potential (Vss) and asecond terminal 10 of capacitance C1. Athird switch 12 is coupled between (Vss) and terminal 6 of capacitance C1, and afourth switch 14 is coupled between the substrate (represented by the voltage (Vbb)) andterminal 10 of capacitance C1. In operation, switches 4 and 8 are both closed (made conductive) for charging capacitance C1 to a voltage equal to the difference between (Vcc) and (Vss). In FIG. 1, (Vcc)=+5 volts and (Vss)=0 volts, so capacitance C1 charges with node 6 five volts more positive thannode 10. Thereafter, switches 4 and 8 are opened and switches 12 and 14 are both closed. Since the positive terminal 6 of capacitance C1 is now coupled to a ground potential, thenegative terminal 10 of capacitance C1 tries to drive Vbb to negative 5 volts throughswitch 14. Thereafter,switches - 6. As discussed in more detail below, known charge pumps consume a substantial amount of power (often 1 milliwatt or more even when no further pumping is required), often work against themselves by adding positive substrate current as they operate, and generally operate inefficiently.
- 7. The present invention is directed to a charge pump which consumes only a very small amount of power (approximately 50 microwatts or less in the exemplary embodiment described herein when no additional pumping is required). The charge pump according to the present invention does not add substrate current as it operates, and operates more efficiently than known charge pumps. In one embodiment of the present invention, a low voltage regulator on the integrated circuit generates a low voltage supply on the integrated circuit for powering a variable frequency oscillator, whose nodes oscillate between ground and the regulated low voltage supply of, for example, about 1.5 volts. The low voltage regulator provides a slightly higher voltage until some negative substrate bias is achieved, assuring proper start-up operation of the oscillator. The low voltage supply dramatically reduces power consumption of the oscillator compared to known oscillators. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed (i.e., when the substrate voltage is at or below the desired negative bias voltage level and the circuit is in standby), and operates at a much higher frequency when charge pumping is needed or likely will be needed. For example, the charge pump will be needed when the substrate voltage is more positive than the desired negative bias voltage level, and may be needed when the integrated circuit is operating in a mode which typically generates high substrate currents. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump.
- 8. Voltage translation circuitry translates the negative substrate voltage into a positive voltage signal (e.g., between 0 and +5 volts). This allows the (translated) substrate voltage to be compared to a positive reference voltage using a conventional comparator, without adding substrate current as it operates. When the substrate voltage is more positive than the desired level, the comparator generates a pump activating signal to a pump signal generator which turns on the charge pump.
- 9. In one embodiment, the charge pump itself uses an NMOS transistor to perform the switching function of
switch 14 of FIG. 1 in a configuration that neither loses a threshold voltage when conducting nor allows P-N diode injection into the substrate when node 6 of capacitor C1 is driven low byswitch 12. Likewise, allother switches 4, 8, and 14 do not exhibit a threshold voltage drop. In an exemplary embodiment, the one-stage pump of the present invention is capable of pumping the substrate to a voltage of −4.9 volts when operating from a supply of +5.0 volts (with the regulator disabled). - 10. A better understanding of the nature and advantages of the charge pump circuit of the present invention may be had with reference to the detailed description and the drawings below.
- 11.FIG. 1 is a conceptual schematic diagram of a known charge pump;
- 12.FIG. 2 is a block diagram of a particular embodiment of a charge pumping system according to the present invention;
- 13.FIG. 3 is a block diagram of a particular embodiment of the variable frequency oscillator shown in FIG. 2;
- 14.FIG. 4 is a schematic diagram of a known oscillator stage;
- 15.FIG. 5 is a schematic diagram of a particular embodiment of the low voltage generator shown in FIG. 2;
- 16.FIG. 6 is a schematic diagram of an alternative embodiment of the low voltage generator shown in FIG. 5;
- 17.FIG. 7 is a waveform showing the operation of the dual frequency oscillator shown in FIG. 3;
- 18.FIG. 8 is a schematic diagram of a particular embodiment of a variable frequency oscillator stage shown in FIG. 3;
- 19.FIG. 9 is a schematic diagram of a timing signal generator shown in FIG. 2;
- 20.FIG. 10 is a timing diagram illustrating the timing of signals generated by the timing signal generator shown in FIG. 9;
- 21.FIG. 11 is a schematic diagram of a known substrate voltage comparator;
- 22.FIG. 12 is a conceptual schematic diagram of a particular embodiment of a substrate voltage detector according to the present invention;
- 23.FIG. 13 is a schematic diagram of a particular embodiment of the logic voltage level translator shown in FIG. 2;
- 24.FIG. 14 is a schematic diagram of particular embodiments of the substrate voltage translator and comparator shown in FIG. 2;
- 25.FIG. 15 is a schematic diagram of a particular embodiment of the pump signal generator shown in FIG. 2;
- 26.FIG. 16 is a timing diagram illustrating the timing of the input signal and of the signals generated by the pump signal generator shown in FIG. 15;
- 27.FIG. 17 is a schematic diagram of a particular embodiment of the charge pump shown in FIG. 2;
- 28.FIG. 18 is a schematic diagram of a known substrate charge switch comprising a diode-connected NMOS transistor;
- 29.FIG. 19 is a schematic diagram of a known substrate charge switch comprising a diode-connected PMOS transistor; and
- 30.FIG. 20 is a schematic diagram of a particular embodiment of a substrate charge switch comprising a serially connected PMOS transistor.
- 31. OVERVIEW
- 32.FIG. 2 is a block diagram of a particular embodiment of a substrate
charge pumping system 20 according to the present invention. Alow voltage generator 24 provides a reduced potential source (for power saving) throughbus 32 to power a variable (e.g., dual)frequency oscillator 28 andtiming signal generator 34.Variable frequency oscillator 28 provides oscillation signals of high or low frequency through abus 36 totiming signal generator 34. High frequency is for fast pumping and low frequency is for reduced power. In response,timing signal generator 34 provides timing signals to control the operation of the remaining portions of the circuit. In particular,generator 34 provides timing signals to logicvoltage level translator 40,comparator 56 andsubstrate voltage translator 44 throughbus 48. - 33. Logic
level voltage translator 40 translates the low voltage signals, for example 0 to +1.5 volts, produced byoscillator 28 andtiming generator 34 into higher voltage signals, of for example 0 to +5 volts. The higher voltage signals are supplied tocomparator 56 through abus 50.Substrate voltage translator 44 translates the substrate voltage from a level below ground to a level above ground and supplies the translated voltage tocomparator 56 through abus 58.Comparator 56 compares the translated voltage received onbus 58 to a reference voltage received on abus 60 and provides, when needed, pump activating signals to apump signal generator 64 through abus 68.Comparator 56 also provides complimentary SPUMP/NSPUMP (Slow pump/Not Slow pump=Low Frequency/Not Low Frequency) signals onSPUMP signal line 70 andNSPUMP signal line 72 tooscillator 28. The SPUMP and NSPUMP signals are used to control the frequency of the oscillator.Pump signal generator 64 generates timing signals on abus 76 for controlling the operation of acharge pump 80.Charge pump 80 creates and maintains a negative substrate bias.Charge pump 80 uses special circuitry which does not experience an undesirable threshold drop in any diode-connected transistor. - 34. OSCILLATOR
- 35.FIG. 3 is a block diagram of a particular embodiment of a dual frequency free-running
oscillator 28.Oscillator 28 comprises an odd number ofoscillator stages 84A-E in the form of inverters. The output terminal of each oscillator stage is coupled to the input terminal of the next oscillator stage, and the output terminal ofoscillator stage 84E is coupled to the input terminal ofoscillator stage 84A, thus forming a ring oscillator. The ring oscillator generates a free-running oscillating signal as each node in the ring alternates a logic “1” and a logic “0”. Eachoscillator stage 84A-E is coupled tobus 32 for receiving power from source 24 (not shown). - 36.FIG. 4 is a schematic diagram of a known oscillator stage suitable for use as oscillator stages 84A-E. The oscillator stage comprises a
PMOS transistor 88 coupled to anNMOS transistor 92. Thesource terminal 94 oftransistor 88 is coupled to Vcc, thedrain terminal 96 is coupled tooutput node 98, and thegate terminal 102 is coupled toinput node 104.Node 104 receives signals from the output node of the previous stage, i.e., stage 84B, if this isstage 84C.NMOS transistor 92 has itsdrain terminal 106 coupled tooutput node 98, itssource terminal 108 coupled to Vss, and itsgate terminal 110 coupled toinput node 104. - 37. The operation of the stage is described below using exemplary values of −5 volts and ground (0 volts) for Vcc and Vss, respectively. Assume
PMOS transistor 88 has a threshold voltage |Vtp| of approximately 0.7 volts below its source voltage andNMOS transistor 92 has a threshold voltage Vtn of approximately 0.8 volts above its source voltage. Wheninput node 104 is at 0 volts,PMOS transistor 88 is on,NMOS transistor 92 is off, andoutput node 98 is at +5 volts. When the potential atinput node 104 rises above +0.8 volts,NMOS transistor 98 turns on. When the potential atinput node 104 reaches or exceeds +4.3 volts,PMOS transistor 88 turns off. Thereafter, onlyNMOS transistor 92 conducts, andoutput node 98 is at 0 volts. The reverse occurs as the voltage atinput node 104 swings from +5 volts to 0 volts. - 38. The problem with this stage is that both
PMOS transistor 88 andNMOS transistor 92 simultaneously conduct during the time theinput node 104 is between +0.8 volts and +4.3 volts, thus drawing a substantial amount of current, on the order of perhaps one hundred microamps. - 39. According to the present invention,
low voltage generator 24 provides a low voltage signal onbus 32 for poweringoscillator 28. The low voltage is equal to the sum of the absolute magnitudes of the threshold voltages Vtn and Vtp. Using the values of Vtp and Vtn noted above,source terminal 94 ofPMOS transistor 88 is coupled to a +1.5 volt potential rather than a +5 volt potential, according to the present invention. Therefore, wheninput node 104 is at 0 volts,PMOS transistor 88 conducts,NMOS transistor 92 is off, andoutput node 98 is at +1.5 volts. When the voltage atinput node 104 rises to +0.8 volts,NMOS transistor 92 turns on, andPMOS transistor 88 turns off. As the voltage atinput node 104 continues to rise to +1.5 volts, onlyNMOS transistor 92 conducts. BecausePMOS transistor 88 andNMOS transistor 92 do not conduct at the same time while the voltage atinput node 104 swings between 0 and +1.5 V, the excessive power consumption of known inverter stages is eliminated. Additionally, operating these transistors at a low voltage means less charge is needed to charge and discharge the gates, thus further reducing power consumption. The logic oftiming signal generator 34 also operates at low voltage to save power. - 40. LOW VOLTAGE GENERATOR
- 41.FIG. 5 is a schematic diagram of a particular embodiment of
low voltage generator 24. A very narrow, very long channel, and thus weak,PMOS transistor 100 has asource terminal 102 coupled to (Vcc), adrain terminal 104 coupled to anode 108, and agate terminal 112 coupled to (Vss). A moderately wide, shortchannel NMOS transistor 114 has agate terminal 118 and drain terminal 122 together coupled tonode 108 and asource terminal 126 coupled to anode 130. Anothersimilar NMOS transistor 134 has agate terminal 138 and adrain terminal 142 together coupled tonode 130 and asource terminal 144 coupled to anode 148. A moderately wide, shortchannel PMOS transistor 152 has asource terminal 164 coupled tonode 148 and to its N Well (schematically represented by a line 168). Agate terminal 154 and adrain terminal 158 ofPMOS transistor 152 is coupled to anode 162 which, in turn, is coupled to (Vss). - 42. In operation,
transistors Transistor 100 provides a very small current through diode-connectedtransistors node 162 is 0 volts, the voltage atnode 148 is |Vtp| volts, the voltage atnode 130 is |Vtp|+Vtn volts, and the voltage atnode 108 is |Vtp|+Vtn+Vtn volts. - 43. A wide, short
channel NMOS transistor 170 has agate terminal 174 coupled tonode 108, adrain terminal 178 coupled to (Vcc), and asource terminal 180 coupled tobus 32.Transistor 170 is connected as a source follower, so the voltage onbus 32 is one NMOS threshold voltage below the voltage onnode 108. Thus, the voltage onbus 32 is |Vtp|+(Vtn) or +1.5 volts for the values noted above. - 44. Because the preferred embodiment uses a low voltage signal to
power oscillator 28,oscillator 28 may malfunction if, for example,NMOS transistor 92 is in depletion mode with a negative threshold voltage. This could happen only in the absence of a negative substrate voltage; that is before the pump establishes the negative substrate bias. Consequently, an alternative embodiment of lowvoltage power supply 24 shown in FIG. 6 may be employed to ensure proper operation ofoscillator 28. The only difference between the circuit shown in FIG. 6 and the one shown in FIG. 5 is the addition of a moderately wide, shortchannel PMOS transistor 200 disposed betweennode 162 and (Vss). As shown in FIG. 6,PMOS transistor 200 has agate terminal 204 coupled to the substrate (designated by the substrate voltage (Vbb)), asource terminal 208 coupled tonode 162 and to its N Well (represented by a line 212), and adrain terminal 216 coupled to (Vss). - 45. Before the substrate has a negative bias, the gate of
PMOS transistor 200 is equal to 0 volts, and the current throughtransistor 200 causesnode 162 to be one PMOS threshold voltage above Vss. The voltage atnode 108 is |Vtp|+|Vtp|+(Vtn)+(Vtn) producing a voltage of |Vtp|+|Vtp|+(Vtn) onbus 32. This higher voltage is sufficient to ensure proper operation of each oscillator stage, even if the NMOS transistors have a slightly negative threshold voltage. Once the charge pump begins pumping and a negative substrate bias is established, the higher voltage onbus 32 is no longer needed. As Vbb goes negative, sourcefollower PMOS transistor 200 pullsnode 162 to (Vss). This produces the |Vtp|+(Vtm)+(Vtn) voltage atnode 108 and the low |Vtp|+(Vtn) voltage onbus 32 to minimize power consumption after initial start up. - 46. DUAL FREQUENCY OSCILLATOR
- 47. In known systems, charge pumping is often accomplished using two separate charge pumps. A smaller charge pump consuming lower power is activated during periods of low substrate current, and both it and a larger charge pump is activated during periods of high substrate current. Using a DRAM as an example, the smaller charge pump is used when the memory is in standby mode, and both pumps are used whenever the memory is in an active cycle, i.e., read or write. Instead of two separate oscillator circuits, the present invention employs a single charge pump, such that both the pump current into the substrate, as well as the current consumed by the pump may be controlled by varying the frequency of
oscillator 28. - 48. During standby,
oscillator 28 generates a relatively low frequency (e.g., ˜200 KHz) oscillator signal (see FIG. 7) so that all components in the system consume low power. The substrate voltage is compared to the reference voltage once per cycle (e.g., at the leading edge of each cycle as shown). As long as the substrate voltage is at or below the desired negative substrate bias voltage,oscillator 28 continues operating at this low frequency. When a voltage comparison indicates pumping is required (i.e., the substrate voltage is more positive than the desired negative substrate bias voltage),oscillator 28 switches to a higher frequency (e.g., ˜20 MHz) via the signals onSPUMP line 70 andNSPUMP line 72 as discussed below. Additionally, a single pump activating positive pulse is generated bycomparator 56 onbus 68 so thatcharge pump 80 may execute a single pumping cycle as discussed above for FIG. 1. The comparison function still occurs on the leading edge of each oscillator signal, and a corresponding pump activating signal is generated eachtime comparator 56 determines pumping is required. Whencomparator 56 determines pumping is no longer needed, it issues the appropriate signals onSPUMP line 70 andNSPUMP line 72 to causeoscillator 28 to return to the low frequency, low power mode. In this embodiment,oscillator 28 also operates at the higher frequency whenever the associated circuit operates in a mode typically associated with high substrate current (e.g., when a DRAM; is in an active cycle) whether or not pumping is actually required. Pumping thus occurs on an as-needed basis, and the high frequency mode ofoscillator 28 allowscharge pump 80 to accommodate high substrate current conditions. - 49. Dual frequency operation of
oscillator 28 is accomplished by addingtransistors transistors source terminal 228 coupled to source terminal 94 of PMOS transistor 88 (which, in this embodiment, is a very narrow, long channel transistor), agate terminal 230 coupled to SPUMP (Slow Pump)line 70, and adrain terminal 232 coupled to anode 234.PMOS transistor 214 has asource terminal 236 coupled tonode 234, agate terminal 240 coupled togate terminal 102 ofPMOS transistor 88, and adrain terminal 244 coupled tonode 106.NMOS transistor 218 has adrain terminal 250 coupled tonode 106, agate terminal 254 coupled togate terminal 110 of NMOS transistor 92 (which, in this embodiment, is a very narrow, long channel transistor), and asource terminal 258 coupled to anode 260. Finally,NMOS transistor 222 has adrain terminal 264 coupled tonode 260, agate terminal 268 coupled to NSPUMP (Not Slow Pump)line 72, and asource terminal 272 coupled to (Vss). - 50. The signals on
lines transistors Oscillator 28 operates at a lower frequency determined by the very high resistances oftransistors transistors oscillator 28 operates at a much higher frequency determined by the much lower combined resistances oftransistors transistors transconductance transistors node 106 high and low much faster than the relatively narrow, very long channel (high resistance)transconductance transistors - 51. As discussed above with reference to FIG. 8, initially oscillator 28 operates in the low frequency mode. When
comparator 56 detects the substrate voltage being above the desired negative bias voltage level, and during periods of possibly high substrate current, the signals are provided onSPUMP line 70 andNSPUMP line 72 for turningtransistors SPUMP line 70 andNSPUMP line 72 for turningtransistors Oscillator 28 then reverts to its low frequency mode, again with a smooth transition between the modes. - 52. TIMING SIGNAL GENERATOR
- 53.FIG. 9 is a schematic diagram showing the construction of
timing signal generator 34 and how it is coupled todual frequency oscillator 28. To save power, all of the circuitry shown in FIG. 9 operates preferably from the reduced power supply voltage provided bylow voltage generator 24.Timing signal generator 34 includes aninverter 300 having an input terminal coupled to the output terminal ofinverter 84A inoscillator 28 and an output terminal coupled to an input terminal of aninverter 304. The output terminal ofinverter 304 is coupled to one input terminal of a 2-input NAND gate 308. The other input terminal ofNAND gate 308 is coupled to the output terminal of aninverter 312 which, in turn, has an input terminal coupled to an output terminal ofinverter 84C inoscillator 28. - 54. Similarly, an
inverter 316 has an input terminal coupled to the output terminal of inverter 84B inoscillator 28 and an output terminal coupled to an input terminal of aninverter 320. The output terminal ofinverter 320 is coupled to one input terminal of a 2-input NAND gate 324. The other input terminal ofNAND gate 324 is coupled to an output terminal of aninverter 328 which, in turn, has an input terminal coupled to an output terminal ofinverter 84D inoscillator 28. - 55. The output terminal of
NAND gate 308 is coupled to an input terminal of aninverter 332, to one input terminal of a 2-input NAND gate 310, and to one input terminal of a 2-input NAND gate 356. The output terminal ofinverter 332 is coupled to an input terminal of aninverter 336 which has an output terminal connected to an input terminal of aninverter 340. An output terminal ofinverter 340 is coupled to an input terminal of aninverter 344 which has an output terminal coupled to an input terminal of aninverter 348. An output terminal ofinverter 348 is coupled to an input terminal of aninverter 352 which has an output terminal coupled to the other input terminal ofNAND gate 356 and to an “X”signal line 354. - 56. An output terminal of
NAND gate 356 is coupled to a input terminal of aninverter 360 which has an output terminal coupled to an input terminal of aninverter 364. An output terminal ofinverter 364 is coupled to a “Y”signal line 368. - 57. An output terminal of
NAND gate 310 is coupled to one input terminal of a 2-input NAND gate 370 and to an input terminal of an inverter 374. The other input terminal ofNAND gate 370 is coupled to an output terminal ofNAND gate 324. An output terminal of inverter 374 is coupled to an input terminal of an inverter 378, and an output terminal of inverter 378 is coupled to a “Z”signal line 382. - 58. An output terminal of
NAND gate 370 is coupled to the other input terminal ofNAND gate 310 and to an input terminal of aninverter 390. An output terminal ofinverter 390 is coupled to an input terminal of an inverter 394, and an output terminal of inverter 394 is coupled to a “W”signal line 398. “X”signal line 354, “Y”signal line 368, “Z”signal line 382, and “W”signal line 398 together comprise bus 48 (FIG. 2). - 59.FIG. 10 is a timing diagram showing the sequence of signals on “X”
signal line 364, “Y”signal line 368, “Z”signal line 382, and “W”signal line 398, respectively. In general, the signals on the “X”signal line 354 and on the “Y”signal line 368 are complimentary, but with timing such that the signal on “X”signal line 354 goes high before the signal on “Y”signal line 368 goes low and vice versa. The same is true for the signals on “Z”signal line 382 and “W”signal line 398. That is, the signals on the lines each have a high portion (+1.5 volts) and a low portion (0 volts), and the low portions of the signals are mutually exclusive. - 60. LOGIC VOLTAGE LEVEL TRANSLATOR
- 61.FIG. 13 is a schematic diagram of a particular embodiment of logic
voltage level translator 40. “X”signal line 354,Y signal line 368, “W”signal line 398 and “Z”signal line 382 are received from timingsignal generator 34. The logic voltage level translator receives logic input signals “X”, “Y”, “W” and “Z”, in which the low logic level is Vss (0 volts) and the high logic level is about 1.5 volts. Its purpose is to provide output signals which switch between Vss and Vcc. - 62.
NMOS transistor 450, functioning as a capacitor, has both its source and drain terminals connected to “X”signal line 354 and itsgate terminal 461 connected to anode 488.NMOS transistor 452, also functioning as a capacitor, has both its source and drain terminals connected to “Y”signal line 368 and itsgate terminal 463 connected to a node 440.NMOS transistor 454, also functioning as a capacitor, has both its source and drain terminals connected to “W”signal line 398 and its gate terminal connected to anode 650.NMOS transistor 456, also functioning as a capacitor, has both its source and drain terminals connected to “Z”signal line 382 and itsgate terminal 560 connected to anode 652. APMOS transistor 460 has asource terminal 464 coupled to (Vcc), adrain terminal 468 coupled to anotherterminal 461 ofcapacitance 450 and agate terminal 472 coupled tonode 490. APMOS transistor 476 has asource terminal 480 coupled to (Vcc), adrain terminal 484 coupled tonode 490 and agate terminal 482 coupled tonode 488. AnNMOS transistor 500 has adrain terminal 504 coupled to (Vcc), a source terminal 508 coupled tonode 488 and agate terminal 512 coupled to a (Vcc−|Vtp|) volt signal. Similarly, anNMOS transistor 520 has adrain terminal 524 coupled to (Vcc), a source terminal 528 coupled tonode 490, and a gate terminal 532 coupled to the (Vcc−|Vtp|) volt signal. - 63. A
PMOS transistor 550 has asource terminal 554 coupled to (Vcc), agate terminal 558 coupled tonode 652, and adrain terminal 564 coupled tonode 650. APMOS transistor 572 has asource terminal 574 coupled to (Vcc), adrain terminal 576 coupled tonode 652, and agate terminal 580 coupled tonode 650. AnNMOS transistor 600 has adrain terminal 604 coupled to (Vcc), asource terminal 608 coupled tonode 650, and agate terminal 612 coupled to the (Vcc−|Vtp|) volt signal. AnNMOS transistor 630 has adrain terminal 634 coupled to (Vcc), a source terminal 638 coupled tonode 652, and agate terminal 642 coupled to the (Vcc−|Vtp|) volt signal. - 64. A
PMOS transistor 660 has asource terminal 664 coupled to (Vcc), adrain terminal 668 coupled to anode 672, and a gate terminal 676 coupled tonode 488. AnNMOS transistor 680 has adrain terminal 684 coupled tonode 672, asource terminal 688 coupled to (Vss), and agate terminal 692 coupled to “X”signal line 354.Node 672 is coupled to an input terminal of an inverter 700 having an output terminal coupled to an input terminal of an inverter 704. An output terminal of inverter 704 is coupled to aline 706 which provides signals tosubstrate voltage translator 44. - 65. Similarly, a
PMOS transistor 710 has asource terminal 714 coupled to (Vcc), adrain terminal 718 coupled to anode 720, and agate terminal 724 coupled tonode 490. AnNMOS transistor 730 has a drain terminal 734 coupled tonode 720, asource terminal 738 coupled to (Vss), and agate terminal 742 coupled to “Y”signal line 368.Node 720 is coupled to an input terminal of an inverter 750 which has an output terminal coupled to an input terminal of aninverter 754. An output terminal ofinverter 754 is coupled to aline 760 which provides signals tosubstrate voltage translator 44.Lines - 66. The function of the part of the logic
voltage level translator 40 shown in the left hand part of FIG. 13 is to generate signals that transition from Vss to Vcc onnodes signal lines voltage level translator 40 is to generate a signal onnode 650 that transitions between Vcc−1.5 volts and Vcc from the low voltage signals “W” and “Z”. Both the left and right portions of the circuitry of FIG. 13 work in the same manner. Nodes “X” onsignal line 354 and “Y” onsignal line 368 transition between Vss (0 volts) and 1.5 volts, and are generally complements of one another. That is, when one is low the other is high and visa versa. Buttiming signal generator 34 of FIG. 2 shown in detail in FIG. 9 provides that node “X” will transition high before mode “Y” transitions low and that node “Y” will transition high before node “X” transitions low, as seen in FIG. 10. - 67. Referring again to FIG. 13, when node “Y” transitions low, capacitor (NMOS transistor) 452 drives
node 490 low turning onPMOS transistor 460, and pullingnode 488 to Vcc. Throughout this time, node “X” is high at +1.5 volts, andcapacitor 450 is charged to 3.5 volts. Next, node “Y” transitions high to +1.5 volts,capacitor 452drives node 490 high, turning offPMOS transistor 460, but withnode 488 remaining at Vcc. Next, node “X” transitions low from 1.5 volts to 0 volts andcapacitor 450drives node 488 down by 1.5 volts to 1.5 volts below Vcc, turning onPMOS transistor 476. This pullsnode 490 up to Vcc at a time when node “Y” is high at +1.5 volts, chargingcapacitor 452 to 3.5 volts. When node “X” then transitions high,node 488 is again returned to Vcc, turning offPMOS transistor 476, but withnode 490 remaining at Vcc. This completes one full cycle. - 68. Thus a high level of Vcc exists on
node 488 when node “X” is high at +1.5 volts and a low level of Vcc−1.5 volts exists onnode 488 when node “X” is at a low level of 0 volts. When node “X” is high at +1.5 volts,NMOS transistor 680 is on and pulls the input of inverter 700 to 0 volts. At this time,node 488 is at Vcc soPMOS transistor 660 is off and no current flows throughtransistors node 488 is low at Vcc−1.5 volts, turning onPMOS transistor 660 and pulling the input of inverter 700 to Vcc. At this time,NMOS transistor 680 is off and again no current flows throughtransistors - 69. Thus, this circuitry generates on the input of inverter 700 a full logic swing between Vss and Vcc from low level inputs on nodes “X” and “Y”, and does so without establishing any current path from Vcc to Vss. Logically,
output 706 of the logic voltage level translator of FIG. 13 is a high level compliment of the low level signal on node “X”. If node “X” instead went directly to a normal inverter whose PMOS source voltage was +5 volts, the inverter would consume substantial power whenever node “X” is at +1.5 volts. In an identical manner, the low-level signal on node “Y” generates its compliment as a high level signal onnode 760. - 70.
NMOS transistors respective node - 71. The circuitry on the right side of FIG. 13 translates the 0 to +1.5 volt logic levels on node “W” to Vcc−1.5 to Vcc volt logic levels on
node 650. These levels onnode 650 will be used to turn on or off a PMOS transistor whose source is at Vcc. This circuitry functions in an identical manner to the corresponding portions of the circuitry on the left side of FIG. 13 already described. - 72. SUBSTRATE VOLTAGE COMPARISON OVERVIEW
- 73. A discussion of a known substrate voltage detector is in order to appreciate the inventive aspects of some of the remaining portions of the charge pumping system of the present invention.
- 74.FIG. 11 is a schematic diagram of a known
substrate voltage comparator 300.Voltage comparator 300 includes a very narrow, very longchannel PMOS transistor 304 having asource terminal 308 coupled to (Vcc), agate terminal 312 coupled to (Vss), and adrain terminal 316 coupled to anode 320.Transistor 304 functions as a very high resistance or very low current source. AnNMOS transistor 324 has adrain terminal 328 coupled tonode 320, agate terminal 332 coupled to a reference voltage Vref (typically ground), and asource terminal 336 coupled to anode 340. AnNMOS transistor 344 has adrain terminal 348 and agate terminal 352 together coupled tonode 340, and asource terminal 356 coupled to anode 360. Finally, anNMOS transistor 364 has adrain terminal 368 and agate terminal 372 together coupled tonode 360, and asource terminal 376 coupled to the substrate Vbb. All the NMOS transistors, 324, 344, and 364 are relatively wide, short channel transistors. - 75. If the substrate voltage is more negative than three NMOS threshold voltages below Vref (ground), there will be conduction through
transistors transistor 364 will preventnode 360 from rising above Vbb plus one NMOS threshold voltage, andtransistor 344 will preventnode 340 from rising more than one NMOS threshold voltage above that, i.e. Vbb+2(Vtn). With the source voltage of NMOS transistor 324 (Vbb+2(Vtn)) its gate voltage Vref is one andtransistor 324 pullsnode 320 down to essentially the voltage onnode 340, i.e. Vbb+2(Vtn). This voltage, below ground, is one logic state for the output onnode 320 signifying that no pumping is necessary. - 76. If, on the other hand, Vbb is less than (more positive voltage than) 3 NMOS threshold voltages below Vref(ground), then diode connected
transistors node 340 low enough to cause conduction throughtransistor 324. In this case, there is no current through the circuit andPMOS transistor 304 pullsnode 320 up to Vcc. This Vcc level onnode 320 is the other logic state for the output onnode 320, signifying that pumping is necessary. The signal atnode 320 is communicated to the charge pump. The charge pump turns on for transferring charge to the substrate whennode 320 is at (Vcc) volts, and the charge pump is turned off whennode 320 is at Vbb+2(Vtn). Unfortunately, whenever Vbb is low enough to turn off the charge pump, there is current flowing throughcomparator 300 into the substrate. Thus, thecomparator 300 itself causes a substrate current which must be pumped away. The substrate voltage comparison circuitry according to the present invention avoids this problem. - 77.FIG. 12 is a conceptual schematic diagram of a particular embodiment of substrate voltage comparison circuitry according to the present invention. A
switch 400 is coupled between ground (Vss) and aterminal 404 of a capacitance C2. Aswitch 408 is coupled between the substrate voltage Vbb and a terminal 412 of capacitance C2. Aswitch 414 is coupled between the power supply voltage (Vcc) andterminal 404 of capacitance C2, and one input terminal 418 ofcomparator 56 is coupled to terminal 412 of capacitance C2 viabus 58. As noted previously, the other input terminal ofcomparator 56 is coupled to reference voltage (Vref) throughbus 60. - 78. The purpose of the switch and capacitance circuitry shown in FIG. 12 is to translate the substrate voltage Vbb to a level which may be compared by
comparator 56. Initially, switches 400 and 408 are closed for charging capacitance C2 to a voltage equal to (Vss−|Vbb|). Thereafter, switches 400 and 408 are opened.Switch 414 is then closed which causesterminal 404 of capacitance C2 to rise from Vss to Vcc. This, in turn, causes the voltage at terminal 412 to rise from Vbb to Vbb+Vcc, assuming Vss equals 0 volts. If Vcc equals +5 volts, and if Vbb is more positive than −5 volts, then the voltage onbus 58 is now a positive voltage which may be conveniently compared bycomparator 56. After the voltage onbus 58 is compared bycomparator 56,switch 414 is opened and switch 400 is closed.Terminal 404 of capacitance C2 falls to Vss, and terminal 412 falls to Vbb. Switch 408 then may be closed with no transfer of charge to or from the substrate. The circuit thus operates without the disadvantage discussed for known comparators. - 79. SUBSTRATE VOLTAGE TRANSLATOR
- 80.FIG. 14 is a schematic diagram of a particular embodiment of
substrate voltage translator 44 andcomparator 56.Voltage level translator 44 corresponds to the switch and capacitor of FIG. 12, whilecomparator 56 of FIG. 14 more or less corresponds to comparator 56 of FIG. 12. Referring to thesubstrate voltage translator 44 portion of FIG. 14,line 760 is coupled to source and drain terminals of PMOS transistors functioning ascapacitances line 706 is coupled to source and drain terminals of a PMOS transistor functioning as acapacitance 820. An NMOS transistor 830 has a drain terminal 834 coupled to a gate terminal 838 ofcapacitance 812, asource terminal 842 coupled to the substrate Vbb, and agate terminal 846 coupled to agate terminal 850 ofcapacitance 820. AnNMOS transistor 854 has a drain terminal 858 coupled togate terminal 850 ofcapacitance 820, asource terminal 862 coupled to Vbb, and a gate terminal 866 coupled to gate terminal 838 ofcapacitance 812. The circuit described thus far operates in the same manner as in the circuit shown in FIG. 13 except all polarities are reversed. The voltage ongate terminals 838 and 850 swing between Vbb and Vbb+Vcc volts asnodes line 760,transistor 854 turns on pullinggate terminal 850 to Vbb during which time the signal online 706 is low. Thereafter, the signal online 760 goes low turning offtransistor 854. Then when the signal online 706 goes high (e.g., +5 volts), the voltage ongate terminal 850 rises to Vbb+5 volts, turning on transistor 830 and pulling gate terminal 838 to Vbb. - 81. An NMOS transistor 880 has a drain terminal 884 coupled to a
gate terminal 888 ofcapacitance 804 and to a node 885, asource terminal 892 coupled to anode 896, and agate terminal 900 coupled togate terminal 850 ofcapacitance 820. AnotherNMOS transistor 904 has adrain terminal 908 coupled tonode 896, asource terminal 912 coupled to Vbb, and agate terminal 916 coupled togate terminal 850 ofcapacitance 820. Finally, anNMOS transistor 930 has adrain terminal 934 coupled to Vcc, asource terminal 938 coupled tonode 896, and agate terminal 942 coupled to node 885. - 82. The switches and capacitor of FIG. 12 correspond to the following transistors of FIGS. 13 and 14.
Switches inverter 754 of FIG. 13 which generatesnode 760. Capacitor CZ of FIG. 12 corresponds to capacitor (PMOS transistor) 804 of FIG. 14. Switch 408 of FIG. 12 corresponds to the series combination ofNMOS transistors 880 and 904 of thesubstrate voltage translator 44 in FIG. 14. The translated substrate voltage onbus 58 of FIG. 12 corresponds to the translatedsubstrate voltage bus 58 of FIG. 14. - 83. As previously discussed, the voltages on the gate terminals of capacitors (PMOS transistors) 812 and 820 alternate between Vbb and (Vbb+Vcc). When
node 706 is high,node 760 is low. At thistime gate terminal 850 ofcapacitor 850 is at (Vbb+Vcc), turning ontransistors 880 and 904, pulling node 885 to Vbb. Then whennode 706 goes low, thegate terminal 850 ofcapacitor 820 returns to Vbb, andtransistors 880 and 904 hopefully turn off. Finallynode 760 rises to Vcc and node 885 is driven to (Vbb+Vcc) as the translated substrate voltage onbus 58 tocomparator 56. To maintain integrity of this (Vbb+Vcc) voltage between the time node 885 rises and thetime comparator 56 is sensed, it is important that the voltage on node 885 not be allowed to leak off. ButNMOS transistor 904 has its source at Vbb and has no back bias or body effect to raise its threshold voltage as do NMOS transistors whose source is at Vss, well above the Vbb potential. Without any body effect,transistor 904 may not shut off completely. That is, it may have a small leakage current even when its gate terminal is at Vbb. Transistors 880 and 930 are included to prevent this problem from leaking charge off node 885. When node 885 rises to (Vbb+Vcc), sourcefollower NMOS transistor 930 pullsnode 896 up to a voltage of [(Vbb+Vcc)−Vtn]. Transistor 880, with itssource 892 well above Vbb and itsgate 900 at Vbb, is fully off and has totally negligible leakage current. Therefore as node 885 rises to (Vbb+Vcc), its level remains intact, andsubstrate voltage translator 44 provides a voltage level of (Vbb+Vcc) intocomparator 56. - 84. The reference voltage Vref on
bus 60 intocomparator 56 of FIG. 14 may be generated by a simple capacitive divider (not shown). If, for example, two capacitors are in series between ground and a node that switches from ground to Vcc, the intermediate node (between the capacitors) will switch by a fraction of Vcc depending on the ratio of the capacitances. The intermediate node is discharged to ground (by an NMOS transistor) when the switching node is at ground. Thus the voltage on the intermediate node switches up to a fraction of Vcc depending on the capacitance ratio. This reference voltage is compared to the (Vbb+Vcc) voltage provided bysubstrate voltage translator 44. If these capacitors are of equal value, then this intermediate node voltage is Vcc/2. In this case the regulator will turn on the charge pump whenever Vbb is more positive than −(Vcc)/2 and turn it off otherwise. That is, the regulator will strive to maintain a substrate voltage such that the voltage onbus 58=(Vbb+Vcc)=½(Vcc)=Vref, or (Vbb)=−½(Vcc). - 85. COMPARATOR
- 86. The translated substrate voltage signal on
bus 58 is communicated tocomparator 56 where it is compared to the reference voltage Vref received onbus 60. The comparison is triggered by the signals on “W”signal line 398 from timingsignal generator 34. In this embodiment, the W signals occur once per oscillator cycle to provide the once-per-cycle comparison discussed above. If the substrate voltage is more positive than the reference voltage, then a pump activating signal in the form of a positive pulse appears online 68. Additionally, the differential SPUMP/NSPUMP signals are generated onSPUMP signal line 70 andNSPUMP signal line 72 upon each comparison and remain valid until the next cycle. As noted previously, the SPUMP/NSPUMP signals controlPMOS transistor 210 andNMOS transistor 222, respectively, in each oscillator stage (FIG. 8) for setting the oscillator frequency. - 87. The detailed capacity of
comparator 56 is shown in FIG. 14. The “W” signals on “W”signal line 398 are communicated to agate terminal 1000 of anNMOS transistor 1004 for executing the comparison function.NMOS transistor 1004 has asource terminal 1008 coupled to Vss and adrain terminal 1012 coupled to a node 1016. Node 1016 is, in turn, coupled to a source terminal 1020 of an NMOS transistor 1024 and to asource terminal 1028 of anNMOS transistor 1032. Agate terminal 1036 of NMOS transistor 1024 is coupled for receiving the reference voltage Vref (which may be generated via a capacitive divider coupled between Vcc and Vss as previously discussed) onbus 60, and agate terminal 1040 ofNMOS transistor 1032 is coupled for receiving the translated substrate voltage onbus 58. NMOS transistor 1024 has adrain terminal 1044 coupled to asource terminal 1048 of anNMOS transistor 1052.NMOS transistor 1052 has agate terminal 1056 coupled to anode 1060 and adrain terminal 1064 coupled to anode 1068.Node 1068 is coupled to adrain terminal 1072 of aPMOS transistor 1076 and to adrain terminal 1080 of aPMOS transistor 1084. Agate terminal 1088 ofPMOS transistor 1076 is coupled toline 650, and agate terminal 1092 oftransistor 1084 is coupled tonode 1060. Asource terminal 1096 oftransistor 1076 and asource terminal 1100 oftransistor 1084 are both coupled to Vcc. - 88. A
drain terminal 1104 oftransistor 1032 is coupled to a source terminal 1108 of an NMOS transistor 1112. NMOS transistor 1112 has agate terminal 1116 coupled to a node 1120 (which is coupled to node 1068) and adrain terminal 1124 coupled to a node 1128 (which is coupled to node 1060).Node 1128 is coupled to adrain terminal 1132 of aPMOS transistor 1136 and to adrain terminal 1140 of a PMOS transistor 1144. A gate terminal 1148 ofPMOS transistor 1136 is coupled tonode 1120, and agate terminal 1152 of PMOS transistor 1144 is coupled toline 650. Asource terminal 1156 oftransistor 1136 and asource terminal 1160 of transistor 1144 are both coupled to Vcc. - 89.
Node 1128 is coupled to an input terminal of aninverter 1180 which has an output terminal coupled tobus 68 and to an input terminal of a 2-input NORgate 1188. Similarly,node 1068 is coupled to an input terminal of an inverter 1192 which has an output terminal coupled to an input terminal of a 2-input NORgate 1200. An output terminal of NORgate 1188 is coupled to another input terminal of NORgate 1200, and an output terminal of NORgate 1200 is coupled to another input terminal of NORgate 1188. NORgates inverters 1180 and 1192 are maintained until the next comparison function. - 90. The output terminal of NOR
gate 1200 is coupled to an input terminal of a 2-input NORgate 1204. Another input terminal of NORgate 1204 is coupled for receiving an active high DRAM RAS signal. The output terminal of NORgate 1204 is coupled to SPUMP (Slow Pump)signal line 70 and to an input terminal of aninverter 1208. An output terminal ofinverter 1208 is coupled toNSPUMP signal line 72. - 91. As previously discussed,
node 650 from logicvoltage level translator 40 in FIG. 13 switches between Vcc−1.5 volts and Vcc as node “W” switches between 0 volts Vss and +1.5 volts, respectively. Refer once again to thecomparator 56 in FIG. 14. Between sensing cycles node “W” is low, andNMOS transistor 1004 is off. At this time, signal 650 is also low andPMOS transistors 1076 and 1144 are on, chargingnodes - 92. When signal “W” transitions high (to +1.5 volts)
node 650 also transitions high (to Vcc).NMOS transistors 1076 and 1144 turn off. AsNMOS transistor 1004 turns on, node 1016 transitions low. If the translated substrate voltage (Vbb+Vcc) onbus 58 is at a higher voltage than Vref,transistor 1032 starts to conduct before transistor 1024, since their source terminals are connected together. Astransistor 1032 conducts, itsdrain 1104 discharges toward ground faster than the drain of transistor 1024 discharges toward ground. Preceding this,nodes 1068 and 1128 (the gate connections of transistors 1112 and 1052) were each at the same voltage, Vcc. Thus, as thedrain node 1104 oftransistor 1032 discharges towards Vss, transistor 1112 conducts pullingnode 1128 to ground. This turns offNMOS transistor 1052 preventing it from pullingnode 1068 to ground while turning onPMOS transistor 1084 to maintainnode 1068 at Vcc. Thus under this condition with the translated substrate voltage (Vbb+Vcc) onbus 58 above the reference voltage,node 1128 goes to ground whilenode 1068 remains at Vcc. Whennode 1128 goes to ground, the output ofinverter 1180 goes high (to Vcc. Note that after this initial switching transient but with nodes W and 650 still high, there is again no current path. There is no current in the right hand side of the circuit becausePMOS transistors 1136 and 1144 are both off and there is no current in the left hand side becauseNMOS transistor 1052 is off. For as long as nodes “W” and 650 remain high,node 1128 remains low andnode 68 remains high. - 93. Thus, a positive pulse on “W” (and on bus 650), when
node 58 is above Vref, causes a positive pulse onnode 68 while the output of inverter 1192 remains at ground. This positive pulse indicates pumping is required. (The translated substrate voltage is too positive.) This pulse does two things. First it provides a single pump cycle onnode 68 delivered to the charge pump itself which will be described below. And second, it sets a flip flop comprised of NORgates - 94. The positive pulse on
node 68 causes the output of NORgate 1188 to go low. This low combined with the low out of inverter 1192 causes the output of NORgate 1200 to go high. This high maintains the output of NORgate 1188 low even after the positive pulse onnode 68 terminates. Thus the output of NORgate 1200 remains high (until such time that inverter 1192 provides a high output). - 95. If, instead, the translated substrate voltage (Vbb+Vcc) on
bus 58 is below the reference voltage, no pumping is required. In this case,node 1068 pulses to ground whilenode 1128 remains high. Withnode 1128 remaining high, there is no change in the low voltage onnode 68, and no pump cycle is executed. At the same time, the positive pulse on the output of inverter 1192 causes NORgate 1200 to have a low output. This low output combined with a low onnode 68 causes a high output of NORgate 1188. The high output of NORgate 1188 maintains a low on the output of NORgate 1200 even after the positive pulse on the output of inverter 1192 terminates. - 96. Thus, if the comparator most recently determined that the substrate was too positive (i.e., pumping is required) the output of NOR
gate 1200 will be high. If, instead, the comparator most recently determined that the substrate was sufficiently negative (i.e, no pumping required), the output of NORgate 1200 will be low. The signal RASD is high whenever the circuit is in its active state. For a DRAM, this would be high during an active cycle and low during precharge between cycles. When either the comparator most recently determined that pumping is required or when the circuit is active (RASD is high) then the output of NOR gate 1204 (SPUMP) is low. A low output on SPUMP (Slow Pump) causes the oscillator not to oscillate slow but rather fast. That is, a low on SPUMP turns onPMOS transistor 210 of FIG. 8, while the high out of inverter 1208 (FIG. 14) on NSPUMP turns onNMOS transistor 222 of FIG. 8. - 97. As previously discussed, when
transistors voltage level translator 40 of FIG. 13, thesubstrate voltage translator 44 of FIG. 14 and thecomparator 56 of FIG. 14. The low frequency operation of approximately 200 kilohertz, with much of the circuitry operating from a 1.5 volt supply, permits the pump to consume less than 1 microamp of total current when no pumping is required. Yet when pumping is required, the circuit automatically switches to high frequency, and at high frequency is capable of pumping more than 1 milliamp of current out of the substrate. - 98. PUMP SIGNAL GENERATOR
- 99.FIG. 15 is a schematic diagram of a particular embodiment of
pump signal generator 64. The pump signal received onbus 68 is coupled to an input terminal of an inverter 1300 which has an output terminal coupled to an input terminal of an inverter 1304. An output terminal of inverter 1304 is coupled to an input terminal of an inverter 1308, to an input terminal of aninverter 1312, and to an input terminal of aninverter 1316. An output terminal of inverter 1308 is coupled to an input terminal of an inverter 13 20. An output terminal of inverter 1320 is coupled to an input terminal of an inverter 1328, to an input terminal of aninverter 1332, and to an input terminal of aninverter 1336. An output terminal of inverter 1328 is coupled to an input terminal of an inverter 1340. A n output terminal of inverter 1340 is coupled to an input terminal of an inverter 1344, to an input terminal of aninverter 1348, and to an input terminal of aninverter 1352. An output terminal ofinverter 134 8 is coupled to an input terminal ofinverter 1356, and the output terminal of an inverter 13 56 is coupled to an input terminal of aninverter 1360. An output terminal of inverter 1344 is coupled to an input terminal of an inverter 1364. An output terminal of inverter 1364 is coupled to an input terminal of an inverter 1368 and to an input terminal of aninverter 1372. An output terminal of inverter 1368 is coupled to an input terminal of an inverter 1376, and an output terminal of inverter 1376 is coupled to an input terminal of aninverter 1380. - 100. An output terminal of
inverter 1380 is coupled to one input of a 2-input NAND gate 1384. Another input terminal ofNAND gate 1384 is coupled to an output terminal ofinverter 1312. An output terminal ofNAND gate 1384 is coupled to an input terminal of aninverter 1388, and an output terminal ofinverter 1388 is coupled to a “D”signal line 1392. - 101. An output terminal of
inverter 1316 is coupled to an input terminal of a 2-input NAND gate 1396. Another input terminal of NAND gate 1396 is coupled to an output terminal of ainverter 1372. An output terminal of NAND gate 1396 is coupled to an input terminal of an inverter 1400, and an output terminal of inverter 1400 is coupled to an input terminal of an inverter 1404. An output terminal of inverter 1404 is coupled to an “A”signal line 1408. - 102. An output terminal of
inverter 1360 is coupled to an input terminal of a 2-input NAND gate 1412. Another input terminal ofNAND gate 1412 is coupled to an output terminal ofinverter 1332. An output terminal ofNAND gate 1412 is coupled to an input terminal of aninverter 1416, and an output terminal ofinverter 1416 is coupled to a “B”signal line 1420. - 103. An output terminal of
inverter 1352 is coupled to an input terminal of a 2-input NAND gate 1424. Another input terminal ofNAND gate 1424 is coupled to an output terminal ofinverter 1336. An output terminal ofNAND gate 1424 is coupled to an input terminal of an inverter 1428, and an output terminal of inverter 1428 is coupled to an input terminal of an inverter 1432. An output terminal of inverter 1432 is coupled to a “C”signal line 1436. - 104. As can be seen by inspection, there are an odd number of inverters between
node 68 and each input of each of theNAND gates node 68. That is, ifnode 68 is high, these NAND gate outputs are all high. Nodes “B” and “D”, each having one inversion after its respective NAND gate, are opposite in polarity tonode 68. Nodes “A” and “C”, each having two inversions after its respective NAND gate are the same polarity as isnode 68. - 105. When
node 68 goes high, node “O” goes low after 5 logic delays. That is, in sequence, the output of inverter 1300 goes low, 1304 goes high, 1312 goes low,NAND 1384 out goes high andinverter 1388 out goes low. But whennode 68 goes low, node “O” goes high after 13 logic delays. That is, the output of inventer 1300 goes high, 1304 goes low, 1308 goes high, 1320 goes low, 1328 goes high, 1340 goes low, 1344 goes high, 1364 goes low, 1368 goes high, 1376 goes low, 1380 goes high,NAND 1384 out goes low, and finally inverter 1388 goes high. - 106. The various number of inverters in each of the logic paths to generate each of the signals “A”, “B”, “C”, and “D” are chosen to insure that when
node 68 transitions high, node “D” transitions low before node “C” transitions high and that whennode 68 transitions low, node “C” transitions low before node “D” transitions high. See FIGS. 15 and 16. Furthermore node “A” transitions high before node “B” transitions low and node “B” transitions high before node “A” transitions low. Also, node “D” transitions low before node “B” transitions low and node “B” transitions high before node “D” transitions high. - 107. When no pumping is required,
node 68 remains as low as previously discussed, and nodes “A”, “B”, “C” and “D” don't move. Whencomparator 56 determines that a pump cycle is required,nodes 68, “A”, “B”, “C”, and “D” execute a single pump cycle with the relative timing indicated in FIG. 16. - 108. CHARGE PUMP
- 109.FIG. 17 is a schematic diagram of a particular embodiment of
charge pump 80. “A”signal line 1408 is coupled to aterminal 1450 of acapacitance 1454, and “B”signal line 1420 is coupled to aterminal 1458 of acapacitance 1462.Capacitances capacitance 1454 is coupled to agate terminal 1554 of a PMOS transistor 1558. PMOS transistor 1558 has asource terminal 1562 coupled to Vss and adrain terminal 1566 coupled to agate terminal 1570 of a PMOS transistor 1574 and to agate terminal 1578 ofcapacitance 1462. PMOS transistor 1574 has asource terminal 1582 coupled to Vss and adrain terminal 1586 coupled togate terminal 1554 of transistor 1558. As the signals on “A”signal line 1408 and “B”signal line 1420 swing from 0 volts to +5 volts, the signals onterminals 1550 and 1578 swing from −5 volts to 0 volts, respectively. - 110. “D”
signal line 1392 is coupled to aterminal 1474 of acapacitance 1478, and “C”signal line 1436 is coupled to aterminal 1490 of acapacitance 1494.Capacitances gate terminal 1628 ofcapacitance 1478 is coupled to agate terminal 1632 of anNMOS transistor 1636.NMOS transistor 1636 has asource terminal 1668 coupled to Vbb and adrain terminal 1664 coupled to agate terminal 1652 of anNMOS transistor 1644 and to agate terminal 1660 ofcapacitance 1494.NMOS transistor 1644 has asource terminal 1648 coupled to Vbb and adrain terminal 1640 coupled togate terminal 1628 ofcapacitance 1478. As the signals on “D”signal line 1392 and “C”signal line 1436 swing from 0 volts to +5 volts, the signals onterminals - 111. A
capacitance 1524 has one terminal 1520 coupled to a node 1508 and agate terminal 1604 coupled to anode 1610.Capacitance 1524 comprises a PMOS transistor having its source and drain terminals coupled together, and it functions as capacitance C1 in FIG. 1. - 112. A
PMOS transistor 1470 has asource terminal 1500 coupled to Vcc, agate terminal 1466 coupled to “B”signal line 1420, and adrain terminal 1504 coupled to node 1508.PMOS transistor 1470 functions as switch 4 in FIG. 1. It turns on when “B”signal line 1420 is at 0 volts and turns off when “B” signal line is at +5 volts. - 113. A
PMOS transistor 1594 has asource terminal 1598 coupled to Vss, agate terminal 1590 coupled togate terminal 1578 ofcapacitance 1462, and adrain terminal 1602 coupled tonode 1610.PMOS transistor 1594 functions as switch 8 in FIG. 1. It turns on when itsgate terminal 1590 is at −5 volts and turns off whengate terminal 1590 is at 0 volts. - 114. A 50 micron
wide NMOS transistor 1486 has a drain terminal 1512 coupled to node 1508, agate terminal 1482 coupled to “D”signal line 1392, and asource terminal 1516 coupled to Vss. NMOS transistor 1486 functions asswitch 12 in FIG. 1. It turns on when “D”signal line 1392 is at +5 volts and turns off when “D”signal line 1392 is at 0 volts. - 115. A 350 micron
wide NMOS transistor 1612 has adrain terminal 1608 coupled tonode 1610, agate terminal 1620 coupled to terminal 1628 ofcapacitance 1478, and asource terminal 1616 coupled to Vbb. NMOS transistor 1612 functions asswitch 14 in FIG. 1. It turns on when itsgate terminal 1620 is at (Vbb+5) volts and turns off when itsgate terminal 1620 is at Vbb volts. - 116. The signals on “A”
signal line 1408, “B”signal line 1420, “C”signal line 1436, and “D”signal line 1392 cause the transistor switches to open and close in the manner discussed for FIG. 1, thus removing positive charge from the substrate as needed. - 117. (Vbb) SWITCH
- 118. A unique feature of
charge pump 80 is the use ofNMOS transistor 1612 asswitch 14 for enabling the transfer of charge from terminal 1604 ofcapacitance 1524 to the substrate. To fully appreciate the inventive aspects of usingNMOS transistor 1612 in the manner discussed, a review of known switches for transferring charge to the substrate is in order. In each case, assume Vcc is +5.0 volts and Vss is 0.0 volts. Thus, when terminal 1520 ofcapacitance 1524 is coupled to Vss after the capacitance is charged, terminal 1604 is driven toward −5.0 volts. Also assume Vbb is some voltage between 0.0 volts and −5.0 volts. - 119.FIG. 18 is a schematic diagram of a known embodiment of
switch 14. In this embodiment, switch 14 comprises a diode-connected NMOS transistor 1700 having asource terminal 1704 coupled to terminal 1604 of capacitance C1, adrain terminal 1708 coupled to the substrate Vbb, and agate terminal 1712 coupled to drain terminal 1708. NMOS transistor conducts whenever the voltage on terminal 1604 is Vtn below Vbb. However, it should be noted that the source region of NMOS transistor 1700 is an N-type region located in the P-type substrate. The N-type source and P-type substrate thus form a PN junction. Therefore, as terminal 1604 becomes more negative than Vbb, the PN junction becomes forward biased. Unless the NMOS threshold voltage Vtn is very low, the forward bias of the PN diode is high enough to cause substantial injection of electrons into the P-type substrate. This increases the likelihood of latchup of CMOS devices and creates leakage of charge from the memory nodes in a DRAM. Therefore, use of NMOS transistors forswitch 14 has been generally unsuccessful. - 120.FIG. 19 is a schematic diagram of another known embodiment of
switch 14. In this embodiment, switch 14 comprises a diode-connectedPMOS transistor 1750 having adrain terminal 1754 coupled to terminal 1604 ofcapacitance 1524, agate terminal 1758 coupled to drain terminal 1754, and asource terminal 1762 coupled to Vbb. PMOS transistor 1750 conducts whenever the voltage on terminal 1604 is one |Vtp| below Vbb, and no electrons are injected into the substrate. However, the fact that terminal 1604 must be driven one |Vtp| below Vbb to establish conduction means that ascomparator 1524 drivesnode 1604 to −5 volts, the substrate, Vbb is only driven to −4.2 volts if |Vtp|=0.8 volts. Thus, the pump is not very efficient. Yet, this configuration is widely used. - 121.FIG. 20 is a schematic diagram of a possible embodiment of
switch 14 which overcomes the problems noted above. In this embodiment, switch 14 comprises aPMOS transistor 1780 having a first current flowing terminal 1784 coupled to terminal 1604 ofcapacitance 1524, a second current flowing terminal 1788 coupled to Vbb, and a gate terminal 1792 for controlling the operation of the transistor. Assume Vbb is at −4.9 volts. When terminal 1604 is at −5.0 volts, first current flowing terminal 1784 functions as a drain terminal and second current flowing terminal 1788 functions as a source terminal (since, by definition, the source is positive relative to the drain in PMOS transistors). Assume |Vtp|=0.8 volts. To turnPMOS transistor 1780 on, a signal of (Vbb−0.8) volts (or more negative) must be applied to gate terminal 1792. With Vbb=−4.9 volts, then a −5.7 volt (or more negative) signal must be applied to gate terminal 1792. When the comparator is being recharged and terminal 1604 is at 0.0 volts, first current flowing terminal 1784 functions as a source terminal and second current flowing terminal 1788 functions as a drain terminal. To turnPMOS transistor 1780 off, a signal of −0.8 volts (or more positive) must be applied to gate terminal 1792. Thus, the signal generator for gate terminal 1792 must produce a signal which must vary by approximately 5 volts or more, which is difficult given a 5 volt power supply. Thus, this circuit is not widely used. - 122. As noted in the discussion of FIG. 17,
NMOS transistor 1612 has adrain terminal 1608 coupled to terminal 1604 ofcapacitance 1524, asource terminal 1616 coupled to Vbb, and agate terminal 1620 coupled to terminal 1628 ofcapacitance 1478.Terminal 1628 ofcapacitance 1478 provides a signal which swings between Vbb and (Vbb+Vcc) for turningNMOS transistor 1612 off and on.NMOS transistor 1612 is substantially wider than NMOS transistor 1486 (e.g., 350 microns vs. 50 microns). - 123. As the “D” signal on
node 1392 transitions from 0 volts to the Vcc voltage,NMOS transistor 1486 turns on. Simultaneously,capacitor 1478 drives thegate terminal 1620 ofNMOS transistor 1612 above the substrate voltage Vbb, turningtransistor 1612 on. The capacitance ofcapacitor 1478 is much larger than the gate capacitance oftransistor 1612. Therefore, at any given instant during the positive switching transition of node “D”, the gate oftransistor 1612 is almost as much above Vbb (the source of transistor 1612) as node “D” (the gate of transistor 1486) is above Vss (the source of transistor 1486). The threshold voltage oftransistor 1486 is increased by its body effect; that is, by the fact that its source voltage (0 volts) is above its substrate voltage, Vbb. The threshold voltage oftransistor 1612 is not increased by body effect since its source is connected to the common substrate of all NMOS transistors Vbb. Thus, the threshold voltage oftransistor 1486 is greater than the threshold voltage oftransistor 1612. As node “D” rises,transistor 1612 starts to turn on beforetransistor 1486 starts to turn on because of its lower threshold voltage (assumingcapacitor 1478 is large enough). - 124. During any arbitrary time during the rise of node “D” (including the final voltage of Vcc),
transistor 1486 conducts a current no greater than its saturation current at that gate voltage. The saturation current oftransistor 1486 pulls node 1508 toward 0 volts, providing a displacement current throughcapacitor 1524, trying to drivenode 1610 below the substrate Vbb. At this time,transistor 1612 has close to the same gate-to-source voltage as doestransistor 1486. And most importantly,transistor 1612 is, for example, seven times as wide as is transistor 1486 (e.g., 350 microns vs. 50 microns). - 125.
Transistor 1612 is designed to have a low resistance, by making it very wide. Its resistance is low enough that the saturation current through transistor 1486 (and through capacitor 1524) can only develop a voltage of about 0.3 volts acrosstransistor 1612. Thus,node 1610 is never driven more than 0.3 volts below the substrate voltage Vbb. Although the first current flowingterminal 1608 ofNMOS transistor 1612 is driven negative with respect to the substrate, forward biasing the P-N diode, the injection current is totally negligible. It takes about 0.7 volts of forward bias to get substantial current through a silicon P-N diode. Every 60 millivolts reduction in forward bias decreases the current by a factor of 10. At a forward bias of 0.3 volts, 400 mv below 0.7 volts, the current is more than one million times smaller than it would be at a forward bias at 0.7 volts. - 126. Thus, by designing
transistor 1612 to have a much greater width than that oftransistor 1486 and by designingcapacitor 1478 to have a much greater capacitance than that of the gate oftransistor 1612, forward bias injection current is made completely negligible. Yet, this is accomplished with thegate terminal 1620 oftransition 1612 only switching from Vbb to (Vbb+Vcc), and without the drop of a threshold voltage acrosstransistor 1612. The lack of a threshold drop makespump 80 substantially more efficient than prior-art pumps, using less Vcc current to obtain a given substrate pump current, and achieving greater pump current for a givencapacitor 1524 size. - 127. With no body effect,
NMOS transistor 1612 may not completely turn off even with its gate voltage equal to its source voltage of Vbb. Therefore, during standby, when no pumping is taking place, node “D” is high so thattransistor 1612 is on. At this time, node “B” is high, andPMOS transistor 1594 is off with negligible leakage current, as isPMOS transistor 1470. That is, the standby condition is that shown at the start or end of FIG. 16. The substrate is actually pumped negative after node “D”, FIG. 16, rises. Any leakage current throughtransistor 1612 only remains during the pump cycle pulse during which time capacitor is being charged and node “D”, FIG. 16, is low. This leakage current, multiplied by the pulse width, gives a leakage charge per pump cycle. Because the leakage is low and the pulse width is low (perhaps 20 nanoseconds), the leakage charge per cycle is very low, negligible compared to the pump charge per cycle. If the pump were instead stopped with node “D”, low andtransistor 1612 presumably off but possibly slightly on andPMOS transistor 1594 definitely on, there could be a substantial leakage path from the substrate to ground. - 128. Finally, when terminal 1604 is driven below Vbb, first current flowing terminal 1608 functions as a source terminal and second current flowing terminal 1616 functions as a drain terminal (since, by definition, the drain is positive relative to the source in NMOS transistors). Assume V=0.8 volts and Vbb−4.9 volts. To turn
NMOS transistor 1612 on, a signal of −4.1 volts (or more positive) must be applied togate terminal 1620. When terminal 1604 is at 0.0 volts, first current flowing terminal 1608 functions as a drain terminal and second current flowing terminal 1616 functions as a source terminal. To turnNMOS transistor 1612 off, a signal of (Vbb+0.8) volts (or more negative) must be applied togate terminal 1620. That is, a voltage more positive than −4.1 volts turnstransistor 1612 on while a voltage more negative than −4.1 volts turns it off. Thus, the voltage need not switch by an amount close to an above as was required for a PMOS transistor switch doing the job ofNMOS transistor 1612. Instead, a voltage charge less than Vcc is more than adequate. - 129. In conclusion, a number of independent innovations together provide the full benefits that have been taught herein. Each makes its own contribution and taken alone, advances the prior art. Used together, they provide a pump consuming very low standby power, yet capable of pumping high current and also capable of achieving, with a one stage pump, a substrate voltage almost as far below ground as the positive supply Vcc is above ground. The various innovative circuit techniques disclosed herein include: operating the pump oscillator from a reduced supply voltage to save power; increasing this reduced supply voltage level if substrate is not reasonably negative; operating the pump oscillator at a low frequency when pumping is not necessary to save power and at a high frequency when pumping may be necessary to achieve high pump current; translating the low voltage swing logic nodes to high voltage swing nodes without any power-consuming direct current paths; translating the Vbb voltage up to (Vbb+Vcc) with a capacitor and switches to provide for easy comparison to a reference voltage to determine if pumping is needed; employing an
NMOS transistor 1612 of FIG. 17 forswitch 14 of FIG. 1; limiting the voltage developed across this transistor to an acceptable level in which P-N diode injection current is negligible; providing thattransistor 1612 of FIG. 17 remains on during the potentially long time periods between pump cycles so that any off leakage current that may be present has very limited time to pull the substrate high. - 130. While the above is a complete description of specific embodiments of the present invention, various modifications may be employed. For example, assumed voltages and the sizes of the various transistors may vary without departing from the principles of operation. Consequently, the scope of the invention should not be limited except as described in the claims.
Claims (81)
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US09/732,793 US6326839B2 (en) | 1996-07-29 | 2000-12-07 | Apparatus for translating a voltage |
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US2272496P | 1996-07-29 | 1996-07-29 | |
US08/882,564 US6064250A (en) | 1996-07-29 | 1997-07-03 | Various embodiments for a low power adaptive charge pump circuit |
US09/516,399 US6323722B1 (en) | 1996-07-29 | 2000-03-01 | Apparatus for translating a voltage |
US09/732,793 US6326839B2 (en) | 1996-07-29 | 2000-12-07 | Apparatus for translating a voltage |
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US09/516,399 Division US6323722B1 (en) | 1996-07-29 | 2000-03-01 | Apparatus for translating a voltage |
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US08/882,564 Expired - Lifetime US6064250A (en) | 1996-07-26 | 1997-07-03 | Various embodiments for a low power adaptive charge pump circuit |
US09/324,932 Expired - Lifetime US6137335A (en) | 1996-07-29 | 1999-06-03 | Oscillator receiving variable supply voltage depending on substrate voltage detection |
US09/516,879 Expired - Lifetime US6323721B1 (en) | 1996-07-26 | 2000-03-01 | Substrate voltage detector |
US09/516,399 Expired - Lifetime US6323722B1 (en) | 1996-07-29 | 2000-03-01 | Apparatus for translating a voltage |
US09/732,793 Expired - Lifetime US6326839B2 (en) | 1996-07-29 | 2000-12-07 | Apparatus for translating a voltage |
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US08/882,564 Expired - Lifetime US6064250A (en) | 1996-07-26 | 1997-07-03 | Various embodiments for a low power adaptive charge pump circuit |
US09/324,932 Expired - Lifetime US6137335A (en) | 1996-07-29 | 1999-06-03 | Oscillator receiving variable supply voltage depending on substrate voltage detection |
US09/516,879 Expired - Lifetime US6323721B1 (en) | 1996-07-26 | 2000-03-01 | Substrate voltage detector |
US09/516,399 Expired - Lifetime US6323722B1 (en) | 1996-07-29 | 2000-03-01 | Apparatus for translating a voltage |
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- 1997-07-25 EP EP97112808A patent/EP0822477B1/en not_active Expired - Lifetime
- 1997-07-25 DE DE69719097T patent/DE69719097T2/en not_active Expired - Lifetime
- 1997-07-29 KR KR1019970035968A patent/KR100514024B1/en not_active IP Right Cessation
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2000
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US20050195669A1 (en) * | 2002-09-18 | 2005-09-08 | Jae-Yoon Sim | Memory device that recycles a signal charge |
US7333378B2 (en) * | 2002-09-18 | 2008-02-19 | Samsung Electronics Co., Ltd | Memory device that recycles a signal charge |
WO2007062354A2 (en) * | 2005-11-21 | 2007-05-31 | Atmel Corporation | Charge pump for intermediate voltage |
WO2007062354A3 (en) * | 2005-11-21 | 2008-06-12 | Atmel Corp | Charge pump for intermediate voltage |
US7479915B1 (en) * | 2007-12-19 | 2009-01-20 | Texas Instruments Incorporated | Comparator architecture |
US7429850B1 (en) | 2008-03-31 | 2008-09-30 | International Business Machines Corporation | Bias voltage converter |
US8810283B2 (en) * | 2012-05-22 | 2014-08-19 | Analog Devices, Inc. | CMOS transistor linearization method |
CN105027439A (en) * | 2013-03-06 | 2015-11-04 | 高通股份有限公司 | Voltage level shifter with a low-latency voltage boost circuit |
US20160098049A1 (en) * | 2014-10-03 | 2016-04-07 | M31 Technology Corporation | Voltage generating circuit |
US9465395B2 (en) * | 2014-10-03 | 2016-10-11 | M31 Technology Corporation | Voltage generating circuit |
CN112448577A (en) * | 2019-08-28 | 2021-03-05 | 圣邦微电子(北京)股份有限公司 | Resistance bleeder circuit |
Also Published As
Publication number | Publication date |
---|---|
DE69725078D1 (en) | 2003-10-30 |
DE69719097D1 (en) | 2003-03-20 |
DE69719097T2 (en) | 2003-11-27 |
US6326839B2 (en) | 2001-12-04 |
US6137335A (en) | 2000-10-24 |
EP0822477A3 (en) | 1998-04-01 |
KR100514024B1 (en) | 2005-12-28 |
US6323722B1 (en) | 2001-11-27 |
EP0822477A2 (en) | 1998-02-04 |
DE69725078T2 (en) | 2004-06-09 |
US6064250A (en) | 2000-05-16 |
US6323721B1 (en) | 2001-11-27 |
KR980011440A (en) | 1998-04-30 |
EP0822477B1 (en) | 2003-09-24 |
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