CN112448577A - Resistance bleeder circuit - Google Patents
Resistance bleeder circuit Download PDFInfo
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- CN112448577A CN112448577A CN201910803005.0A CN201910803005A CN112448577A CN 112448577 A CN112448577 A CN 112448577A CN 201910803005 A CN201910803005 A CN 201910803005A CN 112448577 A CN112448577 A CN 112448577A
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- voltage
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- dividing
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Abstract
The utility model provides a combination in order to reduce quiescent current or reduce the consumption, can reduce the consumption, does not lose circuit response speed again through adopting the little resistance bleeder circuit that answers input voltage rapid change with the big resistance bleeder circuit of guaranteeing circuit rapid response speed and answering input voltage steady state to resistance bleeder circuit to be favorable to realizing high-speed low-power consumption resistance bleeder circuit.
Description
Technical Field
The invention relates to a resistance voltage division technology, in particular to a resistance voltage division circuit, which adopts a combination of a small-resistance voltage division circuit for responding to the rapid change of input voltage to ensure the rapid response speed of the circuit and a large-resistance voltage division circuit for responding to the stable state of the input voltage to reduce quiescent current or reduce power consumption, can reduce power consumption, does not lose the response speed of the circuit, and is favorable for realizing the high-speed low-power consumption resistance voltage division circuit.
Background
The resistance voltage division circuit has high precision and simple structure, and is widely applied to various circuit structures. In the application of low power consumption circuit structure, the quiescent current is usually reduced in the form of increasing the resistance value of the resistor. However, the resistance value of the resistor increases, and the delay time inevitably increases, resulting in a slow response speed. Therefore, it is necessary to design a resistor divider circuit that can reduce power consumption without losing circuit speed. The inventor believes that if the structural combination of two groups of voltage dividing circuits is adopted, one group is a small-resistance value rapid sampling voltage dividing resistor to deal with rapid change of input voltage and simultaneously ensures rapid response speed of the circuit, and the other group is a large-resistance value slow sampling voltage dividing resistor to deal with stable state of the input voltage, namely, the static current can be reduced or the power consumption of the circuit can be reduced under normal state, and the high-speed low-power consumption voltage dividing circuit can be favorably realized. In view of the above, the present inventors have invented the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides the resistance voltage division circuit, which adopts the combination of ensuring the quick response speed of the circuit by adopting the small-resistance voltage division circuit for responding to the quick change of the input voltage and reducing the quiescent current or the power consumption by adopting the large-resistance voltage division circuit for responding to the stable state of the input voltage, thereby not only reducing the power consumption, but also not losing the response speed of the circuit, and being beneficial to realizing the high-speed low-power-consumption resistance voltage division circuit.
The technical scheme of the invention is as follows:
the resistor voltage-dividing circuit is characterized by comprising a voltage output end, wherein the voltage output end is respectively connected with one end of a third voltage-dividing resistor, one end of the fourth voltage-dividing resistor, a source electrode of a first NMOS (N-channel metal oxide semiconductor) switching tube and a source electrode of a second PMOS (P-channel metal oxide semiconductor) switching tube, the other end of the third voltage-dividing resistor is connected with a voltage input end, the other end of the fourth voltage-dividing resistor is connected with a grounding end, a drain electrode of the first NMOS switching tube and a drain electrode of the second PMOS switching tube are interconnected to form a fourth node, the fourth node is respectively connected with one end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor, the other end of the first voltage-dividing resistor is connected with a drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the.
The first voltage dividing resistor and the second voltage dividing resistor are both small-resistance resistors, and the third voltage dividing resistor and the fourth voltage dividing resistor are both large-resistance resistors.
The resistance value of the first divider resistor is 1: n, n is an integer greater than 1.
The resistance value of the second divider resistor is 1: n, n is an integer greater than 1.
The grid of first NMOS switch tube is connected with the output end of the second in-phase buffer, the input end of the second in-phase buffer is connected with the first node, the grid of the second PMOS switch tube is connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the first node, the first node is respectively connected with the voltage input end through the first capacitor, the grounding end is connected through the first resistor, and the grounding end is connected through the first voltage stabilizing diode.
The first node is connected with a drain electrode of a first PMOS (P-channel metal oxide semiconductor) tube and a grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube respectively, the grid electrode of the first PMOS tube is connected with the voltage input end, a source electrode of the first PMOS tube is connected with a second node, the second node is connected with the voltage input end through a second voltage stabilizing diode respectively, connected with the voltage input end through a second resistor and connected with a grounding end through a second capacitor.
The source electrode of the first NMOS tube is connected with the grounding end, the drain electrode of the first NMOS tube is connected with a third node, and the third node is respectively connected with the voltage input end through a third voltage-stabilizing diode, connected with the voltage input end through a third resistor and directly connected with the grid electrode of the second PMOS tube.
The negative electrode of the first voltage stabilizing diode is connected with the first node, the positive electrode of the first voltage stabilizing diode is connected with the ground terminal, the negative electrode of the second voltage stabilizing diode is connected with the second node, the positive electrode of the second voltage stabilizing diode is connected with the voltage input end, the positive electrode of the third voltage stabilizing diode is connected with the third node, and the negative electrode of the third voltage stabilizing diode is connected with the voltage input end.
The invention has the following technical effects: the invention provides a resistance voltage division circuit, which can realize a high-speed low-power consumption resistance voltage division circuit, wherein the high speed means that the resistance voltage division circuit can keep the response speed of the circuit, and the low power consumption means that the current consumed by a resistance voltage division path can be ignored when the circuit needs the quick response speed due to the quick change of the input voltage.
Drawings
Fig. 1 is a schematic diagram of a resistor divider circuit according to the present invention.
Fig. 2 is a schematic diagram of waveforms of the first node V0, the second node V1, the third node V2, the fourth node VOUT0, the input voltage terminal VIN, and the output voltage terminal VOUT in fig. 1. In fig. 2, the ordinate represents voltage, and the abscissa represents time. In the 2 nd period in fig. 2: VIN decreases rapidly, V0 is pulled high, V2 is pulled low, VOUT0 equals VOUT. In the 3 rd time period in fig. 2: VIN remains low, VOUT0 and V0 are pulled low to ground, and V2 is raised to VIN hold. In the 4 th period in fig. 2: VIN rises rapidly, VOUT and VOUT0 both rise, VOUT and VOUT0 are equal, V0 goes high, namely goes low, V2 goes high, namely goes low, goes flat and rises. In the 5 th period in fig. 2: VIN and VOUT and V2 are both held high, and V0 and VOUT0 are both pulled low to ground.
The reference numbers are listed below: VIN-input voltage or input voltage terminal; VOUT-output voltage or output voltage terminal; GND-ground; v0 — first node or first node voltage; v1 — second node or second node voltage; v2-third node or third node voltage; VOUT0 — fourth node or fourth node voltage; c0 — first capacitance; c1 — second capacitance; z0 — first zener diode; z1 — second zener diode; z2-third zener diode; r0 — first resistance; r1 — second resistance; r2 — third resistance; rdiv0 — first divider resistor; rdiv 1-second voltage dividing resistor; rdiv 2-third voltage dividing resistor; rdiv 3-fourth voltage dividing resistor; mp 0-first PMOS transistor; mp 1-second PMOS transistor; mn 0-first NMOS tube; mns-first NMOS switch tube; mps-a second PMOS switching tube; INV0 — first inverter; buffer-second in-phase Buffer; 1: n-represents a resistance ratio of Rdiv0 to Rdiv2 or a resistance ratio of Rdiv1 to Rdiv3, and n is an integer greater than 1.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic diagram of a resistor divider circuit according to the present invention. Fig. 2 is a schematic diagram of waveforms of the first node V0, the second node V1, the third node V2, the fourth node VOUT0, the input voltage terminal VIN, and the output voltage terminal VOUT in fig. 1. As shown in fig. 1 to 2, a resistor divider circuit includes a voltage output terminal VOUT, which is connected to one end of a third divider resistor Rdiv2, one end of a fourth divider resistor Rdiv3, a source of a first NMOS switch Mns, and the source of the second PMOS switch tube Mps, the other end of the third voltage dividing resistor Rdiv2 is connected to the voltage input terminal VIN, the other end of the fourth voltage dividing resistor Rdiv3 is connected to the ground GND, the drain of the first NMOS switch tube Mns and the drain of the second PMOS switch tube Mps are interconnected to form a fourth node VOUT0, the fourth node VOUT0 is respectively connected to one end of the first voltage-dividing resistor Rdiv0 and one end of the second voltage-dividing resistor Rdiv1, the other end of the first divider resistor Rdiv0 is connected with the drain of the second PMOS tube Mp1, the source of the second PMOS transistor Mp1 is connected to the voltage input terminal VIN, and the other end of the second voltage-dividing resistor Rdiv1 is connected to the ground GND. The first voltage dividing resistor Rdiv0 and the second voltage dividing resistor Rdiv1 are both small-resistance resistors, and the third voltage dividing resistor Rdiv2 and the fourth voltage dividing resistor Rdiv3 are both large-resistance resistors.
The resistance value of the first divider resistor Rdiv0 is 1: n, n is an integer greater than 1. The resistance value of the second divider resistor Rdiv1 is 1: n, n is an integer greater than 1. The gate of first NMOS switch tube Mns is connected the output of second cophase Buffer, first node V0 is connected to the input of second cophase Buffer, the output of first phase inverter INV0 is connected to the gate of second PMOS switch tube Mps, the input of first phase inverter INV0 is connected first node V0, first node V0 is connected voltage input VIN through first electric capacity C0 respectively, connects ground terminal GND through first resistance R0, connects ground terminal GND through first zener diode Z0. The first node V0 is connected to the drain of the first PMOS transistor Mp0 and the gate of the first NMOS transistor Mn0, the gate of the first PMOS transistor Mp0 is connected to the voltage input terminal VIN, the source of the first PMOS transistor Mp0 is connected to the second node V1, the second node V1 is connected to the voltage input terminal VIN through the second zener diode Z1, the voltage input terminal VIN through the second resistor R1, and the ground terminal GND through the second capacitor C1. The source electrode of the first NMOS transistor Mn0 is connected to a ground terminal GND, the drain electrode of the first NMOS transistor Mn0 is connected to a third node V2, the third node V2 is connected to the voltage input terminal VIN through a third zener diode Z2, is connected to the voltage input terminal VIN through a third resistor R2, and is directly connected to the gate electrode of the second PMOS transistor Mp 1. The negative electrode of the first zener diode Z0 is connected to the first node V0, the positive electrode of the first zener diode Z0 is connected to the ground GND, the negative electrode of the second zener diode Z1 is connected to the second node V1, the positive electrode of the second zener diode Z1 is connected to the voltage input terminal VIN, the positive electrode of the third zener diode Z2 is connected to the third node V2, and the negative electrode of the third zener diode Z2 is connected to the voltage input terminal VIN.
Fig. 1 is a high-speed low-power consumption resistor divider circuit, and as shown in fig. 1, Rdiv2 and Rdiv3 are always-on divider resistors, and their resistance values can be designed to be relatively large in order to reduce power consumption. The Rdiv0 and Rdiv1 are fast voltage dividing resistors, and the resistance values are designed to be small, so that the response speed is fast, and the Rdiv0/Rdiv1 is Rdiv2/Rdiv 3. However, the pmos tube Mp1 is connected in series with the Rdiv0, and Mp1 is cut off in normal operation, so that no current is consumed in the circuit. R0, R1, C0, C1 and Mp0 are used to detect the change of the input voltage VIN, when VIN changes rapidly, Mp1 is opened through Mn0 tube and R2, and at the same time, the switching tubes Mps and Mns are opened, so that Rdiv0 and Rdiv1 sample the change of VIN rapidly and transmit it to VOUT, thus realizing rapid sampling of VIN, and then after a time delay of R0C 0 or R1C 1, the Mp1 tube is cut off to block the current, but at this time, the output voltage VOUT has completed sampling of VIN.
Referring to fig. 2, when VIN changes slowly, the change in VIN can be directly detected by Rdiv2 and Rdiv 3. FIG. 2 is a schematic diagram of waveforms of main nodes of the circuit when VIN changes rapidly. As shown, when VIN is rapidly decreased, the gate of the Mp0 transistor is equal to VIN, the source voltage is held by C1, and a resistor R1 is connected in series with VIN, so the potential at V1 lags behind the change of VIN by the order of R1 × C1, which causes the gate-source voltage Vgs of Mp0 to rapidly increase and turn on, the potential at V0 is pulled up and higher than the threshold voltage Vth of Mn0 transistor, the Mn0 transistor is turned on and the potential at V2 is pulled down, the Mp1 transistor is turned on, so the rapid divider resistor Rdiv0 is turned on with the Rdiv1 path, VOUT0 rapidly follows the change of VIN, and the switching transistors Mps and Mns are turned on, so VOUT is equal to VOUT0, V367 makes VIN equal to potential through R1 after a delay time of the order of R1 × C1, the p0 is cut off, the V0 is pulled down to ground potential, Mn0 is cut off, and the voltage is cut off similarly to be changed into a rapid sampling path VOUT 874. When VIN rises rapidly, the rapid resistance voltage division path is also rapidly conducted and is cut off after a period of time, so that the circuit can briefly consume larger current only when VIN changes rapidly to achieve the effect of rapidly sampling VIN, the current disappears rapidly after VIN is stabilized, and the current consumed by the rapid resistance voltage division path can be ignored averagely, thereby realizing high speed and low power consumption.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalent, modified and/or simplified implementations as described above, e.g., implementations using other oscillator regulation circuits, etc., without departing from the spirit of the present invention, are intended to fall within the scope of the present invention.
Claims (8)
1. The resistor voltage-dividing circuit is characterized by comprising a voltage output end, wherein the voltage output end is respectively connected with one end of a third voltage-dividing resistor, one end of the fourth voltage-dividing resistor, a source electrode of a first NMOS (N-channel metal oxide semiconductor) switching tube and a source electrode of a second PMOS (P-channel metal oxide semiconductor) switching tube, the other end of the third voltage-dividing resistor is connected with a voltage input end, the other end of the fourth voltage-dividing resistor is connected with a grounding end, a drain electrode of the first NMOS switching tube and a drain electrode of the second PMOS switching tube are interconnected to form a fourth node, the fourth node is respectively connected with one end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor, the other end of the first voltage-dividing resistor is connected with a drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the.
2. The resistor voltage divider circuit according to claim 1, wherein the first voltage divider resistor and the second voltage divider resistor are both small-resistance resistors, and the third voltage divider resistor and the fourth voltage divider resistor are both large-resistance resistors.
3. The resistor voltage-dividing circuit according to claim 1, wherein the first voltage-dividing resistor has a resistance value of 1: n, n is an integer greater than 1.
4. The resistor voltage-dividing circuit according to claim 3, wherein the second voltage-dividing resistor has a resistance value of 1: n, n is an integer greater than 1.
5. The resistor voltage-dividing circuit according to claim 4, wherein a gate of the first NMOS switch tube is connected to an output terminal of a second in-phase buffer, an input terminal of the second in-phase buffer is connected to a first node, a gate of the second PMOS switch tube is connected to an output terminal of a first inverter, an input terminal of the first inverter is connected to the first node, and the first node is respectively connected to the voltage input terminal through a first capacitor, the ground terminal through a first resistor, and the ground terminal through a first voltage-stabilizing diode.
6. The resistance voltage divider circuit according to claim 5, wherein the first node is connected to a drain of a first PMOS transistor and a gate of a first NMOS transistor, respectively, the gate of the first PMOS transistor is connected to the voltage input terminal, the source of the first PMOS transistor is connected to a second node, the second node is connected to the voltage input terminal through a second zener diode, the voltage input terminal through a second resistance, and the ground terminal through a second capacitance.
7. The resistor voltage divider circuit according to claim 6, wherein a source of the first NMOS transistor is connected to a ground terminal, a drain of the first NMOS transistor is connected to a third node, and the third node is respectively connected to the voltage input terminal through a third zener diode, the voltage input terminal through a third resistor, and the third node is directly connected to the gate of the second PMOS transistor.
8. The resistor divider circuit according to claim 7, wherein a cathode of the first zener diode is connected to the first node, an anode of the first zener diode is connected to ground, a cathode of the second zener diode is connected to the second node, an anode of the second zener diode is connected to the voltage input terminal, an anode of the third zener diode is connected to the third node, and a cathode of the third zener diode is connected to the voltage input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910803005.0A CN112448577B (en) | 2019-08-28 | 2019-08-28 | Resistance bleeder circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910803005.0A CN112448577B (en) | 2019-08-28 | 2019-08-28 | Resistance bleeder circuit |
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| Publication Number | Publication Date |
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| CN112448577A true CN112448577A (en) | 2021-03-05 |
| CN112448577B CN112448577B (en) | 2021-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910803005.0A Active CN112448577B (en) | 2019-08-28 | 2019-08-28 | Resistance bleeder circuit |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010001230A1 (en) * | 1996-07-29 | 2001-05-17 | Proebsting Robert J. | Apparatus for translating a voltage |
| US7609049B1 (en) * | 2008-05-28 | 2009-10-27 | Vimicro Corporation | Accurate scan-mode voltage detection circuit |
| US20100090727A1 (en) * | 2008-10-15 | 2010-04-15 | Kabushiki Kaisha Toshiba | Voltage detection circuit and bgr voltage detection circuit |
| CN103344822A (en) * | 2013-06-26 | 2013-10-09 | 天津成科自动化工程技术有限公司 | Battery voltage monitoring circuit used for battery powered equipment |
| CN103809646A (en) * | 2014-03-07 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Voltage division circuit and control method thereof |
| CN105486912A (en) * | 2015-12-22 | 2016-04-13 | 上海爱信诺航芯电子科技有限公司 | High precision rapid over-current detection circuit for low dropout regulator |
| CN109256158A (en) * | 2018-08-16 | 2019-01-22 | 歌尔股份有限公司 | sensing circuit |
-
2019
- 2019-08-28 CN CN201910803005.0A patent/CN112448577B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010001230A1 (en) * | 1996-07-29 | 2001-05-17 | Proebsting Robert J. | Apparatus for translating a voltage |
| US7609049B1 (en) * | 2008-05-28 | 2009-10-27 | Vimicro Corporation | Accurate scan-mode voltage detection circuit |
| US20100090727A1 (en) * | 2008-10-15 | 2010-04-15 | Kabushiki Kaisha Toshiba | Voltage detection circuit and bgr voltage detection circuit |
| CN103344822A (en) * | 2013-06-26 | 2013-10-09 | 天津成科自动化工程技术有限公司 | Battery voltage monitoring circuit used for battery powered equipment |
| CN103809646A (en) * | 2014-03-07 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Voltage division circuit and control method thereof |
| CN105486912A (en) * | 2015-12-22 | 2016-04-13 | 上海爱信诺航芯电子科技有限公司 | High precision rapid over-current detection circuit for low dropout regulator |
| CN109256158A (en) * | 2018-08-16 | 2019-01-22 | 歌尔股份有限公司 | sensing circuit |
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| CN112448577B (en) | 2021-12-07 |
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