KR20090011183A - Oscillator and internal voltage generator using same - Google Patents

Abstract

An oscillator and an internal voltage generating circuit using the same are provided to generate an oscillation signal with a desired frequency and a pumping voltage without increasing chip area. An oscillator includes a plurality of delay units. Each of the delay units includes the following elements. A source-drain path of a first pull-up MOS transistor(PM1) is connected between a voltage supply terminal and a first node and a gate of the first pull-up MOS transistor is connected to an input terminal. A source-drain path of a second pull-up MOS transistor(PM2) is connected between the first node and an output node and a gate of the second pull-up MOS transistor is connected to the input terminal. A first capacitor(C2) is connected between the first node and the input terminal. A source-drain path of a first pull-down MOS transistor(NM1) is connected between the output terminal and a second node and a gate of the first pull-down MOS transistor is connected to the input terminal. A source-drain path of a second pull-down MOS transistor(NM2) is connected between the second node and a ground and a gate of the second pull-down MOS transistor is connected to the input terminal. A second capacitor(C3) is connected between the second node and the input terminal.

Description

OSCILLATOR AND INTERNAL VOLTAGE GENERATOR USING SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to an oscillator and an internal voltage generation circuit using the same.

In general, semiconductor devices including DDR SDRAM (Double Data Rate Synchronous DRAM) are provided with an internal voltage generation circuit, and internally generate and use an internal voltage having a desired voltage level. The internal voltage generation circuit can be designed in various configurations. Among the circuits that generate the internal voltage using the charge pumping operation, the internal voltage generation circuit has an oscillator as a component.

1 is a circuit diagram illustrating a general oscillator.

Referring to FIG. 1, an oscillator includes a plurality of inverters and a plurality of delay units. For convenience of description, only three inverters 110, 150, and 170 and two delay units 130 and 170 are illustrated in FIG. 1.

First, the first and second delay units 130 and 170 will be omitted and a brief operation will be described.

The first inverter 110 inverts and outputs the input signal OSC_OUT, and the second inverter 150 receives an output signal of the first inverter 110 and inverts and outputs the third signal. The output signal of the second inverter 150 is input and inverted to feed back to the first inverter 110.

As a result, the output signal OSC_OUT of the third inverter 170 is changed from logic 'high' to logic 'low' and then to logic 'low' to logic 'high' through the inversion operation and the feedback feedback. Oscillation. That is, it becomes an oscillation signal.

Meanwhile, in order to generate the oscillation signal OSC_OUT oscillating at a low frequency, RC delay circuits such as the first and second delay units 130 and 170 are used. Each of the first and second delay units 130 and 170 includes a resistor R1 and a capacitor C1 to increase the oscillation period of the oscillation signal OSC_OUT. That is, as the delay time (hereinafter, referred to as "RC delay time") reflected by the first and second delay units 130 and 170 becomes longer, the oscillation signal OSC_OUT of the low frequency may be generated.

In this case, the important factors that determine the RC delay time are resistors and capacitors. For convenience of description, the first delay unit 130 will be described as a representative.

Increasing the value of the resistor R1 increases the delay time of the signal passing through the resistor R1. Increasing the capacitance of the capacitor C1 increases the delay time due to charging / discharging. That is, to increase the RC delay time, the value of the resistor R1 may be increased or the capacity of the capacitor C1 may be increased.

However, if the value of the resistor R1 is increased, the chip area is increased accordingly, and if the capacity of the capacitor C1 is increased, the amount of current consumed while charging / discharging is increased. In other words, in order to increase the RC delay time, it is necessary to bear the burden of increasing chip area and increasing power consumption.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an oscillator capable of generating an oscillation signal having a predetermined frequency while minimizing power consumption.

Another object is to provide an oscillator capable of generating an oscillation signal having a predetermined frequency without increasing the chip area.

In addition, another object of the present invention is to provide a pumping voltage generator capable of generating a pumping voltage while minimizing power consumption without increasing chip area.

According to an aspect of the present invention for achieving the above object, in the oscillator having a plurality of delay units, each of the plurality of delay units, a source-drain path is formed between the power supply voltage terminal and the first node and the gate at the input terminal; A first pull-up MOS transistor connected thereto; A second pull-up MOS transistor having a source-drain path formed between the first node and an output terminal and having a gate connected to the input terminal; A first capacitor connected between the first node and the input terminal; A first pull-down MOS transistor having a source-drain path formed between the output terminal and the second node and having a gate connected to the input terminal; A second pull-down MOS transistor having a source-drain path formed between the second node and a ground voltage terminal and gated to the input terminal; And a second capacitor connected between the second node and the input terminal.

According to another aspect of the present invention for achieving the above object, the voltage detection means for detecting the internal voltage corresponding to the reference voltage; An oscillator responsive to an output signal of the voltage detecting means and having a plurality of delay units for generating an oscillation signal having a predetermined frequency; And charge pumping means for generating the internal voltage through charge pumping in response to the oscillation signal, wherein each of the plurality of delay units has a source-drain path formed between a power supply voltage terminal and a first node and is delayed. A first pull-up MOS transistor having a gate connected to the negative input terminal; A second pull-up MOS transistor having a source-drain path formed between the first node and an output terminal of the delay unit and having a gate connected to the input terminal; A first capacitor connected between the first node and the input terminal; A first pull-down MOS transistor having a source-drain path formed between the output terminal and the second node and having a gate connected to the input terminal; A second pull-down MOS transistor having a source-drain path formed between the second node and a ground voltage terminal and having a gate connected to the input terminal; And a second capacitor connected between the second node and the input terminal.

The present invention uses the RC delay time due to the coupling effect in securing a delay time for the oscillation signal output from the oscillator to have a predetermined frequency, thereby reducing the burden on the chip area and consumed power. Can be minimized.

In the present invention described above, by securing the delay time by using the coupling effect, the power consumed to secure the delay time can be reduced, and the effect of preventing the chip area from increasing can be obtained.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a circuit diagram illustrating an oscillator according to the present invention.

Referring to FIG. 2, the oscillator according to the present invention may include a plurality of delay units, and for convenience of description, one of the delay units is shown as a representative.

The delay unit includes a first pull-up PMOS transistor PM1 having a source-drain path formed between the external voltage terminal VDD and the first node NOD1 and having a gate connected to the input terminal IN, and the first node NOD1 and the input terminal. A second pull-down NMOS transistor having a source-drain path formed between the first capacitor C2 connected between the first terminal C1 and the second node NOD2 and the ground voltage terminal VSS, and having a gate connected to the input terminal IN; A signal input through the input terminal IN using the NM2, the second capacitor C3 connected between the second node NOD2 and the input terminal IN, and the first and second nodes NOD1 and NOD2 as power sources. Inverter INV1 for inverting and a resistor R2 connected between the output terminal of the inverter INV1 and the input terminal of the next delay unit.

In this case, the inverter INV1 includes a second pull-up PMOS transistor PM2 having a source-drain path formed between the first node NOD1 and the output terminal of the inverter INV1 and having a gate connected to the input terminal IN, and the inverter INV1. The first pull-down NMOS transistor NM1 may be provided between a source-drain path and an output terminal of the () and a gate connected to the input terminal IN.

FIG. 3 is an operation timing diagram for describing an operation of the delay unit illustrated in FIG. 2. For convenience of explanation, the delay time caused by the resistor R2 will not be considered. That is, it is assumed that the 'OUT' terminal and the output terminal of the inverter INV1 shown in FIG. 2 are the same.

3 illustrates an operation timing diagram of the input terminal IN, the output terminal OUT, the first node NOD1, and the second node NOD2 of FIG. 2. Let's take a look at each node. Section A is the section where the input terminal IN is logic 'low', Section B is the section where the input terminal IN transitions from logic 'low' to logic 'high', and section C is the section where the input terminal IN is logical 'high'. The 'in' section, the 'D' section is the section where the input terminal IN transitions from logic 'high' to the logic 'low', and the section E is the section where the input terminal IN becomes logic 'low' again.

First, in a period in which the input terminal IN becomes logic 'low', the first and second pull-up PMOS transistors PM1 and PM2 are turned on, and the first node NOD1 is connected to the external voltage terminal VDD. ) And the first and second pull-down NMOS transistors NM1 and NM2 are turned off, and the second node NOD2 floats to the voltage level of the ground voltage terminal VSS. floating state.

In a section B, in which the input terminal IN transitions from logic 'low' to logic 'high', the first node NOD1 has a voltage level raised by α due to a coupling effect at the voltage level of the external voltage terminal VDD. The second node NOD2 also becomes a voltage level raised by β to the voltage level of the ground voltage terminal VSS due to the coupling effect. Thus, when the first and second pull-down NMOS transistors NM1 and NM2 are turned on, the output signal OUT transitions from logic 'high' to logic 'low' after a delay time due to the influence of β.

In the C section where the input terminal IN becomes logic 'high', the first and second pull-up PMOS transistors PM1 and PM2 are turned off, and the first node NOD1 is at the voltage level of the external voltage terminal VDD. The floating voltage level is increased by. The first and second pull-down NMOS transistors NM1 and NM2 are turned on, and the second node NOD2 is at the voltage level of the ground voltage terminal VSS.

In the section D, in which the input terminal IN transitions from logic 'high' to logic 'low', the first node NOD1 is coupled to a voltage level raised by α from the voltage level of the external voltage terminal VDD by a coupling effect. The voltage level is lowered by β, and the second node NOD2 is also lowered by α from the voltage level of the ground voltage terminal VSS due to the coupling effect. Thus, when the first and second pull-up PMOS transistors PM1 and PM2 are turned on, the output signal OUT transitions from logic 'low' to logic 'high' after a delay time due to the influence of β.

The first node NOD1 is at the voltage level of the external voltage terminal VDD while the first and second pull-up PMOS transistors PM1 and PM2 are turned on in the E period when the input terminal IN becomes logic 'low'. The first and second pull-down NMOS transistors NM1 and NM2 are turned off, and the second node NOD2 is floating at a voltage level lowered by α from the voltage level of the ground voltage terminal VSS.

As described above, according to the present invention, the delay time may be reflected in the output signal OUT by using the coupling effect of the first and second capacitors C2 and C3. Therefore, in securing the RC delay time, it is possible to secure the predetermined RC delay time without consuming power or designing a large resistance value of the resistor.

Thus, an oscillator having a large number of such delay units can generate an oscillation signal having a desired low frequency without unnecessary power consumption and burden of chip area.

On the other hand, the oscillator for generating a low frequency oscillation signal may be used in the pumping voltage generation circuit, Figure 4 is a block diagram illustrating a pumping voltage generation circuit having an oscillator of the present invention.

Referring to FIG. 4, the pumping voltage generation circuit may include a voltage detector 410, an oscillator 430, and a charge pumping unit 450.

The voltage detector 410 detects the pumping voltage VPP corresponding to the reference voltage V_REF and outputs it as the detection signal DET. For example, the detection signal DET becomes logic 'high' to enable the oscillator 430 when the voltage level of the reference voltage V_REF is higher than the voltage level of the pumping voltage VPP, and the reference voltage V_REF. If the voltage level is lower than the voltage level of the pumping voltage VPP, the logic becomes 'low' to disable the oscillator 430.

The oscillator 430 generates an oscillation signal OSC_OUT having a predetermined frequency in response to the detection signal DET. The oscillator 430 may include a plurality of delay units, and at least one of the plurality of delay units has the configuration of FIG. 2. This will be described later with reference to FIG. 5.

The charge pumping unit 450 generates the pumping voltage VPP through the charge pumping operation in response to the oscillation signal OSC_OUT. That is, when the oscillation signal OSC oscillated by operating the oscillator 430 is input to the charge pumping unit 450, the charge pumping unit 450 generates the pumping voltage VPP through the charge pumping operation.

Thus, the generated pumping voltage VPP is input to the voltage detector 410 again, and the voltage detector 410 compares the voltage level of the reference voltage V_REF and the pumping voltage VPP to activate or activate the oscillator 430. The detection signal DET for determining the deactivation is output.

FIG. 5 is a block diagram illustrating the oscillator 430 of FIG. 4.

Referring to FIG. 5, the oscillator 430 includes an oscillator activator 432 for activating an oscillation operation of the oscillator 430 in response to the detection signal DET and the oscillation signal OSC_OUT, and a plurality of delayed chains. It may be provided. Here, only the first and second delay units 434 and 436 are shown for convenience of description. The first and second delay units 434 and 436 have the configuration as shown in FIG. 2, respectively.

Technical implementation and operation of each delay unit has already been described with reference to FIG. 2 and will be apparent to those skilled in the art. Hereinafter, detailed descriptions thereof will be omitted.

As a result, the pumping voltage generation circuit according to the present invention can generate the pumping voltage without unnecessary power consumption and without burdening the chip area.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although the case of using the first pull-up PMOS transistor PM1 and the second pull-down NMOS transistor NM2 has been described as an example in FIG. 2, the present invention is also applicable to the case of replacing this with another type of transistor. In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

In addition, FIG. 4 illustrates an example in which the pumping voltage VPP having the voltage level higher than the external power supply voltage is generated by using the oscillator 430. However, the present invention uses the oscillator 430 to generate a pumping voltage VPP. In addition to the low voltage level, it can be applied to a circuit using a low frequency oscillation signal generated through the RC delay time.

1 is a circuit diagram for explaining a general oscillator.

2 is a circuit diagram for explaining an oscillator according to the present invention.

3 is an operation timing diagram for explaining the operation of the delay unit shown in FIG. 2;

4 is a block diagram for explaining a pumping voltage generation circuit having an oscillator of the present invention.

FIG. 5 is a block diagram illustrating the oscillator of FIG. 4. FIG.

* Explanation of symbols for the main parts of the drawings

PM1, PM2: first and second pullup PMOS transistors

NM1, NM2: first and second pulldown NMOS transistors

C2, C3: first and second capacitor R2: resistor

Claims (10)

In an oscillator having a plurality of delay units, Each of the plurality of delay units, A first pull-up MOS transistor having a source-drain path formed between the power supply voltage terminal and the first node and having a gate connected to the input terminal; A second pull-up MOS transistor having a source-drain path formed between the first node and an output terminal and having a gate connected to the input terminal; A first capacitor connected between the first node and the input terminal; A first pull-down MOS transistor having a source-drain path formed between the output terminal and the second node and having a gate connected to the input terminal; A second pull-down MOS transistor having a source-drain path formed between the second node and a ground voltage terminal and gated to the input terminal; And A second capacitor connected between the second node and the input terminal An oscillator having a. The method of claim 1, And a resistor coupled between the output stage and the input stage of the next delay section. The method according to claim 1 or 2, And said first pull-up MOS transistor comprises a PMOS transistor. The method according to claim 1 or 2, And said second pull-down MOS transistor comprises an NMOS transistor. Voltage detecting means for detecting an internal voltage corresponding to the reference voltage; An oscillator responsive to an output signal of the voltage detecting means and having a plurality of delay units for generating an oscillation signal having a predetermined frequency; And Charge pumping means for generating the internal voltage through the charge pump in response to the oscillation signal, Each of the plurality of delay units, A first pull-up MOS transistor having a source-drain path formed between a power supply voltage terminal and a first node and having a gate connected to an input terminal of the delay unit; A second pull-up MOS transistor having a source-drain path formed between the first node and an output terminal of the delay unit and having a gate connected to the input terminal; A first capacitor connected between the first node and the input terminal; A first pull-down MOS transistor having a source-drain path formed between the output terminal and the second node and having a gate connected to the input terminal; A second pull-down MOS transistor having a source-drain path formed between the second node and a ground voltage terminal and having a gate connected to the input terminal; And A second capacitor connected between the second node and the input terminal Internal voltage generation circuit having a. The method of claim 5, And a resistor connected between the output terminal and the input terminal of the next delay unit. The method according to claim 5 or 6, And the first pull-up MOS transistor comprises a PMOS transistor. The method according to claim 5 or 6, And the second pull-down MOS transistor comprises an NMOS transistor. The method according to claim 5 or 6, The oscillator, The plurality of delay units chained together; And an oscillator activator for activating an oscillation operation of the oscillator in response to an output signal of the voltage detecting means. The method according to claim 5 or 6, And the internal voltage has a voltage level higher than an external power supply voltage.

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