US11791934B2 - Communication device, communication method, program, and communication system - Google Patents

Communication device, communication method, program, and communication system Download PDF

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US11791934B2
US11791934B2 US16/092,240 US201716092240A US11791934B2 US 11791934 B2 US11791934 B2 US 11791934B2 US 201716092240 A US201716092240 A US 201716092240A US 11791934 B2 US11791934 B2 US 11791934B2
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data
transmission
error
communication device
preamble
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US20190097757A1 (en
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Hiroo Takahashi
Takashi Yokokawa
Sonfun Lee
Naohiro Koshisaka
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Sony Group Corp
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Sony Group Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Definitions

  • IF bus interface
  • I2C Inter-Integrated Circuit
  • I3C Inter-Integrated Circuit
  • Patent Literature 1 discloses a digital data processing system in which a host processor and a subsystem controller are interconnected by I2C.
  • Patent Literature 2 discloses a method of realizing a communication protocol deployed in a higher layer above the standard I2C protocol.
  • the present disclosure has been devised in light of such circumstances, and enables communication to be conducted more reliably.
  • a communication method or a program includes: transmitting and receiving a signal with an other communication device; detecting an occurrence of an error by having a preamble specifying a type of data to be transmitted next be received, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble; and if the occurrence of an error is detected, transmitting a clock corresponding to a certain number of bits following the preamble, and then transmitting an abort signal giving an instruction to terminate communication partway through.
  • transmitting and receiving of a signal is performed with an other communication device, and an occurrence of an error is detected by having a preamble specifying a type of data to be transmitted next be received, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble. Then, if the occurrence of an error is detected, a clock corresponding to a certain number of bits following the preamble is transmitted, and then an abort signal giving an instruction to terminate communication partway through is transmitted.
  • a system includes: a first communication device having a control initiative on a bus; and a second communication device that conducts communication under control by the first communication device.
  • the first communication device includes a transmission and reception unit that transmits and receives a signal with the second communication device, an error detection unit that detects an occurrence of an error by having the transmission and reception unit receive a preamble specifying a type of data to be transmitted next, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble, and a conflict avoidance unit that, if the occurrence of an error is detected by the error detection unit, instructs the transmission and reception unit to transmit a clock corresponding to a certain number of bits following the preamble, and then transmit an abort signal giving an instruction to terminate communication partway through.
  • communication is conducted by a first communication device having a control initiative on a bus, and a second communication device that communicates in accordance with control by the first communication device.
  • signals are transmitted and received to and from the second communication device, a preamble specifying the type of data to be transmitted next is received, and the occurrence of an error is detected by comparing the bit sequence of the signal received following the preamble to the bit sequence that should be transmitted for the type specified for transmission by the preamble. Subsequently, if the occurrence of an error is detected, after a clock corresponding to a certain number of bits following the preamble is transmitted, an abort signal giving an instruction to terminate communication partway through is transmitted.
  • FIG. 1 is a block diagram illustrating an example configuration of an embodiment of a bus IF applying the present technology.
  • FIG. 2 is a diagram explaining a conflict error.
  • FIG. 3 is a diagram illustrating an example of a format that avoids a conflict error.
  • FIG. 4 is a flowchart that explains a communication process in a DDR mode of a master.
  • FIG. 5 is a circuit diagram illustrating an example configuration of a master.
  • FIG. 6 is a diagram illustrating another example of a format that avoids a conflict error.
  • FIG. 7 is a diagram illustrating another example of a format that avoids a conflict error.
  • FIG. 8 is a block diagram illustrating an example configuration of an embodiment of a computer applying the present technology.
  • FIG. 1 is a block diagram illustrating an example configuration of an embodiment of a bus IF applying the present technology.
  • the bus IF 11 illustrated in FIG. 1 is made up of a master 12 and three slaves 13 - 1 to 13 - 3 connected to each other via a data signal line 14 - 1 and a clock signal line 14 - 2 .
  • the master 12 has control initiative on the bus IF 11 , and is able to communicate with the slaves 13 - 1 to 13 - 3 via the data signal line 14 - 1 and the clock signal line 14 - 2 .
  • the slaves 13 - 1 to 13 - 3 under control by the master 12 , are able to communicate with the master 12 via the data signal line 14 - 1 and the clock signal line 14 - 2 .
  • the slaves 13 - 1 to 13 - 3 are configured similarly to each other, and hereinafter will be designated simply the slave 13 when not being individually distinguished. This applies similarly to the respective blocks constituting the slave 13 .
  • the data signal line 14 - 1 and the clock signal line 14 - 2 are used to relay signals between the master 12 and the slave 13 .
  • serial data SDA
  • SCL serial clock
  • the master 12 is provided with a transmission and reception unit 21 , an error detection unit 22 , a confirmation signal detection unit 23 , and a conflict avoidance unit 24 .
  • the transmission and reception unit 21 transmits and receives signals to and from the slave 13 via the data signal line 14 - 1 and the clock signal line 14 - 2 .
  • the transmission and reception unit 21 transmits a signal to the slave 13 by driving the data signal line 14 - 1 (switching the electric potential to H level or L level) in accordance with the timings of the serial clock transmitted by driving the clock signal line 14 - 2 .
  • the transmission and reception unit 21 receives a signal transmitted from the slave 13 as a result of the slave 13 driving the data signal line 14 - 1 in accordance with the timings of the serial clock on the clock signal line 14 - 2 .
  • the driving of the clock signal line 14 - 2 is continually conducted by the master 12 side.
  • the error detection unit 22 detects an error occurring in a signal received by the transmission and reception unit 21 .
  • the error detection unit 22 is able to detect an error by conducting a check such as a parity check or a cyclic redundancy check (CRC) on a signal received by the transmission and reception unit 21 , or by confirming a token issued when shifting the transmission right from the slave 13 to the master 12 .
  • CRC cyclic redundancy check
  • the error detection unit 22 is able to instruct the transmission and reception unit 21 to restart communication with the slave 13 from the beginning.
  • the error detection unit 22 may treat one as even parity and the other as odd parity, and detect the occurrence of an error by conducting a parity check on data received by the transmission and reception unit 21 . Consequently, even if a state occurs in which the data signal line 14 - 1 is not being driven by either the master 12 or the slave 13 , the error detection unit 22 is still able to detect whether or not the data is correct.
  • the confirmation signal detection unit 23 detects an acknowledgement signal (ACK) or a negative acknowledgement signal (NACK) transmitted from the slave 13 that receives a signal transmitted from the transmission and reception unit 21 , and thereby confirms whether or not the slave 13 successfully received information such as a command or data.
  • ACK acknowledgement signal
  • NACK negative acknowledgement signal
  • the confirmation signal detection unit 23 detects an acknowledgement signal (ACK) or a negative acknowledgement signal (NACK) transmitted from the slave 13 that receives a signal transmitted from the transmission and reception unit 21 , and thereby confirms whether or not the slave 13 successfully received information such as a command or data.
  • ACK acknowledgement signal
  • NACK negative acknowledgement signal
  • the confirmation signal detection unit 23 is able to confirm that the slave 13 has successfully received the information such as a command or data.
  • the confirmation signal detection unit 23 is able to confirm that the slave 13 has failed to receive the information such as a command or data.
  • the conflict avoidance unit 24 when the transmission and reception unit 21 receives a preamble with an instruction to transmit a CRC word, and the error detection unit 22 detects the occurrence of a token error or a CRC error in the signal received following the preamble, after a clock corresponding to a certain number of bits following the preamble is transmitted, the conflict avoidance unit 24 instructs the transmission and reception unit 21 to transmit an abort signal giving an instruction to terminate communication partway through. Consequently, the conflict avoidance unit 24 is able to avoid the occurrence of a conflict due to read data transmitted from the slave 13 and an HDR exit command transmitted from the master 12 , for example.
  • the transmission and reception unit 31 transmits and receives signals to and from the master 12 via the data signal line 14 - 1 and the clock signal line 14 - 2 .
  • the transmission and reception unit 31 receives a signal transmitted from the master 12 as a result of the master 12 driving the data signal line 14 - 1 in accordance with the timings of the serial clock on the clock signal line 14 - 2 .
  • the transmission and reception unit 31 transmit to the master 12 by driving the data signal line 14 - 1 in accordance with the timings of the serial clock on the clock signal line 14 - 2 .
  • the error detection unit 32 detects an error occurring in a signal received by the transmission and reception unit 31 , similarly to the error detection unit 22 of the master 12 . Additionally, when an error does not occur in a signal received by the transmission and reception unit 31 , the error detection unit 32 causes the transmission and reception unit 31 to transmit to the master 12 an ACK informing the master 12 that the information relayed by the signal, such as a command or data, has been received successfully. On the other hand, when an error occurs in a signal received by the transmission and reception unit 31 , the error detection unit 32 causes the transmission and reception unit 31 to transmit to the master 12 a NACK informing the master 12 that the information relayed by the signal, such as a command or data, has failed to be received.
  • the slave 13 drives the first bit of the preamble at 1, and transmits the read data (DDR Data) following the preamble.
  • DDR Data read data
  • the portion with gray hatching applied represents the portion driven by the slave 13
  • the portion with diagonal hatching applied represents the portion kept at H level.
  • DDR CRC CRC word
  • HDR Exit HDR exit command
  • the master 12 in the bus IF 11 , if the master 12 infers that an error occurred in the preamble following read data (DDR Data) transmitted from the slave 13 , it is stipulated that the master 12 transmits a 9-bit additional clock corresponding to the difference between the CRC word and the read data. Additionally, data received during the transmission of the additional clock is ignored.
  • DDR Data preamble following read data
  • the master 12 infers a preamble error. Subsequently, as illustrated in FIG. 2 , the master 12 does not transmit the HDR exit command immediately after transmitting the CRC word, but instead, as illustrated in FIG. 3 , transmits an additional clock following the CRC word, transmits the preamble following the additional clock, and then transmits the HDR exit command.
  • step S 12 the transmission and reception unit 21 of the master 12 drives the data signal line 14 - 1 and the clock signal line 14 - 2 to transmit a read command.
  • step S 13 the transmission and reception unit 21 receives read data transmitted from the slave 13 in response to the read command transmitted in step S 12 , and in addition, also receives a preamble transmitted following the read data.
  • step S 15 the transmission and reception unit 21 receives a signal transmitted following the preamble received in step S 13 , and the error detection unit 22 determines whether or not an error is occurring in the signal.
  • step S 15 if the error detection unit 22 determines that an error is occurring in the signal transmitted following the preamble specifying the transmission of a CRC word, the process proceeds to step S 16 .
  • the conflict avoidance unit 24 infers that an error has occurred in the preamble.
  • step S 16 the error detection unit 22 transmits an additional clock as described with reference to FIG. 3 , and after that, instructs the transmission and reception unit 21 to transmit an abort signal giving an instruction to terminate communication partway through.
  • the transmission and reception unit 21 transmits an abort signal to the slave 13 after transmitting the additional clock.
  • step S 16 After the processing in step S 16 , the transmission and reception unit 21 transmits an HDR exit command following the additional clock. Also, even in the case of determining that an error is not occurring in step S 15 , in step S 17 , the transmission and reception unit 21 transmits an HDR exit command. Consequently, the communication process of reading out data from the slave 13 (DDR Read) in DDR mode by the master 12 is ended.
  • FIG. 5 is a circuit diagram illustrating an example configuration of the master 12 .
  • the master 12 is provided with an SCL driving control unit 51 , an amplification unit 52 , an H level maintaining unit 53 , an amplification unit 54 , a serial conversion unit 55 , a conflict error detector 56 , a parity error detector 57 , a CRC5 error detection unit 58 , a parallel conversion unit 59 , a token error detector 60 , an ACK/NACK detector 61 , a preamble error detector 62 , and a finite state machine (FSM) 63 .
  • SCL driving control unit 51 the master 12 is provided with an SCL driving control unit 51 , an amplification unit 52 , an H level maintaining unit 53 , an amplification unit 54 , a serial conversion unit 55 , a conflict error detector 56 , a parity error detector 57 , a CRC5 error detection unit 58 , a parallel conversion unit 59 , a token error detector 60 , an ACK/NACK detector 61 , a preamble error detector 62
  • the SCL driving control unit 51 following a signal at a frequency that acts as a reference output from the state machine 63 , generates a serial clock to provide to the slave 13 via the clock signal line 14 - 2 , and controls the driving of the clock signal line 14 - 2 .
  • the amplification unit 52 amplifies the clock signal generated by the SCL driving control unit 51 up to a certain level necessary for transmission via the clock signal line 14 - 2 , and outputs to the clock signal line 14 - 2 .
  • the amplification unit 54 amplifies and outputs serial data transmitted via the data signal line 14 - 1 up to a certain level, and amplifies serial data transmitted via the data signal line 14 - 1 to a level necessary for processing internally inside the master 12 .
  • the serial conversion unit 55 converts and outputs parallel data output from the state machine 63 as serial data.
  • the conflict error detector 56 compares serial data output from the serial conversion unit 55 to serial data transmitted via the data signal line 14 - 1 , and thereby detects a conflict error on the data signal line 14 - 1 .
  • the parity error detector 57 uses parity bits added to detect a bit error on the basis of oddness or evenness, detects an error in serial data transmitted via the data signal line 14 - 1 , and reports the error detection result to the state machine 63 .
  • the CRC5 error detection unit 58 corresponds to the error detection unit 22 in FIG. 1 , and by using 5-bit data added to detect a bit error on the basis of a CRC, detects an error in serial data transmitted via the data signal line 14 - 1 , and reports the error detection result to the state machine 63 .
  • the parallel conversion unit 59 converts and outputs serial data transmitted via the data signal line 14 - 1 as parallel data.
  • the ACK/NACK detector 61 corresponds to the confirmation signal detection unit 23 in FIG. 1 , detects from the parallel data converted by the parallel conversion unit 59 an ACK or a NACK transmitted from the slave 13 , and reports the detection result (ACK/NACK) to the state machine 63 .
  • the preamble error detector 62 detects whether or not an error has occurred in the preamble included in parallel data converted by the parallel conversion unit 59 , and reports the error detection result to the state machine 63 .
  • word alignment is conducted by adopting as the format of the CRC word a format in which 9 reserved bits have been inserted between the token (Token(0xC)) and the CRC5.
  • the number of reserved bits corresponds to the different between the number of bits in the token and the CRC5 (9 bits), and the number of bits in the read data (18 bits).
  • the master 12 detects any of a token error, a CRC error, and reception of a CRC word of a certain length or less after receiving a preamble with a bit sequence of 0 and 1, in order to stop the slave 13 safely, the master 12 is subsequently able to end communication similarly to a normal master abort.
  • communication may be ended early safely by having the driving of the data signal line 14 - 1 be switched from the slave 13 to the master 12 in accordance with the bit immediately after reception of the CRC word.
  • the configuration is not limited to the transmission of the HDR exit command, insofar as the conflict may be avoided and communication may be recovered.
  • the master 12 may transmit an HDR restart command (HDR Restart) giving an instruction to restart communication in HDR mode.
  • HDR restart command HDR Restart
  • the conflict avoidance unit 24 may also infer that an error has occurred if the transmission and reception unit 21 receives a CRC word rather than receiving read data of a certain length, and instruct the transmission and reception unit 21 to transmit an abort signal after transmitting an additional clock as described earlier.
  • the present technology is not limited to a bus IF 11 conforming to the I3C standard, and may also be applied to a bus IF 11 conforming to another standard.
  • a bus IF 11 illustrated in FIG. 1 an example configuration is illustrated in which slaves 13 - 1 to 13 - 3 are connected, but there may also be one or two slaves 13 , or three or more slaves 13 , for example.
  • system represents the totality of an apparatus composed of a plurality of apparatus.
  • the foregoing series of operations may be executed in hardware, and may also be executed in software.
  • a program constituting such software may be installed from a program recording medium storing the program onto a computer built into special-purpose hardware, or alternatively, onto a computer capable of executing various functions by installing various programs thereon, such as a general-purpose personal computer, for example.
  • FIG. 8 is a block diagram illustrating an exemplary hardware configuration of a computer that executes the foregoing series of processes in accordance with a program.
  • a central processing unit (CPU) 101 read-only memory (ROM) 102 , random access memory (RAM) 103 , and electrically erasable and programmable read-only memory (EEPROM) 104 are connected to each other by a bus 105 . Also connected to the bus 105 is an input/output interface 106 , and the input/output interface 106 is connected to external equipment (for example, the data signal line 14 - 1 and the clock signal line 14 - 2 in FIG. 1 ).
  • CPU central processing unit
  • ROM read-only memory
  • RAM random access memory
  • EEPROM electrically erasable and programmable read-only memory
  • the foregoing series of processes is conducted as a result of the CPU 101 loading a program stored in the ROM 102 or the EEPROM 104 into the RAM 103 via the bus 105 , and executing the program, for example.
  • the program executed by the computer CPU 101
  • the program executed by the computer may also be installed and updated in the EEPROM 104 from an external source via the input/output interface 106 .
  • present technology may also be configured as below.
  • a communication device including:
  • a transmission and reception unit that transmits and receives a signal with an other communication device
  • an error detection unit that detects an occurrence of an error by having the transmission and reception unit receive a preamble specifying a type of data to be transmitted next, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble;
  • a conflict avoidance unit that, if the occurrence of an error is detected by the error detection unit, instructs the transmission and reception unit to transmit a clock corresponding to a certain number of bits following the preamble, and then transmit an abort signal giving an instruction to terminate communication partway through.
  • a preamble received by the transmission and reception unit specifies transmission of a cyclic redundancy check (CRC) word including a token and a CRC5, but a token error or a CRC error is detected by the error detection unit on the basis of a bit sequence in a signal received following the preamble,
  • CRC cyclic redundancy check
  • the conflict avoidance unit causes the abort signal to be transmitted after transmitting, following the preamble, a clock according to a number of bits in the CRC word, and an additional clock corresponding to a difference between the number of bits in the CRC word and a number of bits in read data read out from the other communication device.
  • the conflict avoidance unit ignores a signal received by the transmission and reception unit during transmission of the additional clock.
  • a preamble received by the transmission and reception unit specifies transmission of a cyclic redundancy check (CRC) word including a token and a CRC5, but a token error or a CRC error is detected by the error detection unit on the basis of a bit sequence in a signal received following the preamble,
  • CRC cyclic redundancy check
  • the conflict avoidance unit causes the abort signal to be transmitted after transmitting a clock with a number of bits corresponding to the CRC word in which is used a format made up of the token, the CRC5, and a number of reserved bits corresponding to a difference between the token and the CRC5 and a number of bits when data is read out from the other communication device.
  • the transmission and reception unit transmits, following the abort signal, a command giving an instruction to exit a specific communication mode.
  • the transmission and reception unit transmits, following the abort signal, a command giving an instruction to restart communication in a specific communication mode.
  • the communication device according to any one of (1) to (7), further including:
  • an acknowledgement signal detection unit that detects either an acknowledgement signal or a negative acknowledgement signal transmitted from the other communication device that has received a signal transmitted from the transmission and reception unit
  • the transmission and reception unit receives read data read out from the other communication device, and continually drives a second bit of a preamble transmitted and received after the read data.
  • the transmission and reception unit drives a data signal line from a bit immediately after reception of a cyclic redundancy check (CRC) word transmitted by the other communication device driving the data signal line.
  • CRC cyclic redundancy check
  • the error detection unit treat one as even parity and the other as odd parity, and detects an occurrence of an error by conducting a parity check on data received by the transmission and reception unit.
  • the transmission and reception unit is able to transmit and receive a signal in a standard data rate (SDR) mode in which data communication is conducted at a standard transfer rate, and a high data rate (HDR) mode in which data communication is conducted at a higher transfer rate than the SDR mode.
  • SDR standard data rate
  • HDR high data rate
  • the transmission and reception unit conducts communication in conformity with the improved Inter-Integrated Circuit (I3C) standard.
  • I3C Inter-Integrated Circuit
  • a communication method including:
  • a program for causing a computer to execute a communication process including:
  • a system including:
  • a transmission and reception unit that transmits and receives a signal with the second communication device
  • an error detection unit that detects an occurrence of an error by having the transmission and reception unit receive a preamble specifying a type of data to be transmitted next, and comparing a bit sequence of a signal received following the preamble to a bit sequence that should be transmitted for the type specified for transmission by the preamble, and
  • a conflict avoidance unit that, if the occurrence of an error is detected by the error detection unit, instructs the transmission and reception unit to transmit a clock corresponding to a certain number of bits following the preamble, and then transmit an abort signal giving an instruction to terminate communication partway through.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
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  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Small-Scale Networks (AREA)
US16/092,240 2016-05-18 2017-05-02 Communication device, communication method, program, and communication system Active 2037-07-20 US11791934B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016099955A JP6786871B2 (ja) 2016-05-18 2016-05-18 通信装置、通信方法、プログラム、および、通信システム
JP2016-099955 2016-05-18
PCT/JP2017/017221 WO2017199761A1 (en) 2016-05-18 2017-05-02 Communication device, communication method, program, and communication system

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CN109075902A (zh) 2018-12-21
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RU2741484C2 (ru) 2021-01-26
JP2017208713A (ja) 2017-11-24
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SG11201808955PA (en) 2018-11-29
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