US11521528B2 - GOA circuit and display panel including same - Google Patents

GOA circuit and display panel including same Download PDF

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Publication number
US11521528B2
US11521528B2 US16/625,024 US201916625024A US11521528B2 US 11521528 B2 US11521528 B2 US 11521528B2 US 201916625024 A US201916625024 A US 201916625024A US 11521528 B2 US11521528 B2 US 11521528B2
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signal line
layer
goa
metal layer
away
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US20210366338A1 (en
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Suping XI
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of display panel manufacturing technologies, and more particularly to a gate driver on array (GOA) circuit and a display panel including the same.
  • GOA gate driver on array
  • Gate driver on array (GOA) designs usually use an array process to make a gate line scan driving signal circuit on an array substrate to realize a driving method of line-by-line scan of a gate.
  • GOA will inevitably use a pad to complete various test functions. A tip of an instrument used in the test will be stuck in the pad. At this time, electrostatic discharge is easy to occur, which will damage a panel. This makes the pad unable to perform corresponding functions and affects stability of the panel.
  • An object of the present application is to provide a gate driver on array (GOA) protection circuit to solve issues of electrostatic discharge of needles during testing in the prior art.
  • GOA gate driver on array
  • an embodiment of the present application provides a GOA circuit, comprising: a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.
  • VCOM voltage common
  • STV start vertical
  • VSS reference voltage
  • LC low-frequency clock
  • the GOA protection circuit comprises: a transparent substrate; a first metal layer disposed on a side surface of the transparent substrate; an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate; an active layer disposed on a side surface of the insulating layer away from the first metal layer; a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole; a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole; a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
  • the antistatic layer is electrically connected to the first metal layer through the deep hole.
  • the antistatic layer is electrically connected to the second metal layer through the shallow hole.
  • the antistatic layer is an indium tin oxide (ITO) layer.
  • the GOA protection circuit comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
  • the diode is an I-type.
  • the I-type design helps to reduce space and not take up extra space.
  • material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
  • an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
  • An embodiment of the present application further provides a display panel using the above GOA circuit, comprising: a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.
  • VCOM voltage common
  • STV start vertical
  • VSS reference voltage
  • LC low-frequency clock
  • the GOA protection circuit comprises: a transparent substrate; a first metal layer disposed on a side surface of the transparent substrate; an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate; an active layer disposed on a side surface of the insulating layer away from the first metal layer; a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole; a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole; a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
  • the antistatic layer is electrically connected to the first metal layer through the deep hole.
  • the antistatic layer is electrically connected to the second metal layer through the shallow hole.
  • the antistatic layer is an indium tin oxide (ITO) layer.
  • the GOA protection circuit comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
  • the diode is an I-type.
  • the I-type design helps to reduce space and not take up extra space.
  • material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
  • an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
  • a GOA circuit and a display panel including the same include an I-type diode GOA protection circuit in the GOA circuit.
  • This design helps to reduce space without taking up extra space.
  • the static electricity is discharged through the GOA protection circuit, which effectively avoids damage to the GOA circuit during electrostatic discharge. When testing the panel, it will not have a substantial impact on function of the pad.
  • FIG. 1 is a top view of a GOA circuit structure in an embodiment of the present application.
  • FIG. 2 is a cross-sectional view of the GOA protection circuit along A-A direction of FIG. 1 .
  • an embodiment of the present application provides a GOA circuit 1 , comprising: a GOA drive signal line 2 comprising a voltage common (VCOM) signal line 201 , a start vertical (STV) signal line 202 , a reference voltage (VSS) signal line 203 , and a low-frequency clock (LC) signal line 204 ; and a GOA protection circuit 3 , wherein an end of the GOA protection circuit 3 is connected to the VCOM signal line 201 , and another end thereof is electrically connected to the STV signal line 202 , the VSS signal line 203 , and the LC signal line 204 .
  • VCOM voltage common
  • STV start vertical
  • VSS reference voltage
  • LC low-frequency clock
  • the GOA protection circuit 3 comprises: a transparent substrate 10 ; a first metal layer 20 disposed on a side surface of the transparent substrate 10 ; an insulating layer 30 disposed on a side surface of the first metal layer 20 away from the transparent substrate 10 and the side surface of the transparent substrate 10 near the first metal layer 20 ; an active layer 40 disposed on a side surface of the insulating layer 30 away from the first metal layer 20 ; a doped layer 50 disposed on a side surface of the active layer 40 away from the insulating layer 30 and having a first via hole; a second metal layer 60 disposed on a side surface of the doped layer 50 away from the active layer 40 and having a second via hole; a passivation layer 70 disposed on a side surface of the second metal layer 60 away from the doped layer 50 and the side surface of the active layer 40 away from the insulating layer 30 , covering the doped layer 50 and the second metal layer 60 ; and an antistatic
  • the antistatic layer 80 is electrically connected to the first metal layer 20 through the deep hole.
  • the antistatic layer 80 is electrically connected to the second metal layer 60 through the shallow hole.
  • the antistatic layer 80 is an indium tin oxide (ITO) layer.
  • ITO indium tin oxide
  • the antistatic layer 80 may also be made of the same metal as the first metal layer 20 and/or the second metal layer 60 .
  • the GOA protection circuit 3 comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
  • the diode is an I-type.
  • the I-type design helps to reduce space and not take up extra space.
  • material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
  • PFA transparent perfluoroalkoxy
  • an end of the antistatic layer 80 is connected to the GOA protection circuit 3 , and another end thereof is overlapped with the STV signal line 202 , the VSS signal line 203 , and the LC signal line 204 .
  • static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
  • An embodiment of the present application further provides a display panel using the above GOA circuit 1 , comprising: a GOA drive signal line 2 comprising a voltage common (VCOM) signal line 201 , a start vertical (STV) signal line 202 , a reference voltage (VSS) signal line 203 , and a low-frequency clock (LC) signal line 204 ; and a GOA protection circuit 3 , wherein an end of the GOA protection circuit 3 is connected to the VCOM signal line 201 , and another end thereof is electrically connected to the STV signal line 202 , the VSS signal line 203 , and the LC signal line 204 .
  • VCOM voltage common
  • STV start vertical
  • VSS reference voltage
  • LC low-frequency clock
  • the GOA protection circuit 3 comprises: a transparent substrate 10 ; a first metal layer 20 disposed on a side surface of the transparent substrate 10 ; an insulating layer 30 disposed on a side surface of the first metal layer 20 away from the transparent substrate 10 and the side surface of the transparent substrate 10 near the first metal layer 20 ; an active layer 40 disposed on a side surface of the insulating layer 30 away from the first metal layer 20 ; a doped layer 50 disposed on a side surface of the active layer 40 away from the insulating layer 30 and having a first via hole; a second metal layer 60 disposed on a side surface of the doped layer 50 away from the active layer 40 and having a second via hole; a passivation layer 70 disposed on a side surface of the second metal layer 60 away from the doped layer 50 and the side surface of the active layer 40 away from the insulating layer 30 , covering the doped layer 50 and the second metal layer 60 ; and an antistatic layer 80 disposed on a side surface of the pass
  • the antistatic layer 80 is electrically connected to the first metal layer 20 through the deep hole.
  • the antistatic layer 80 is electrically connected to the second metal layer 60 through the shallow hole.
  • the antistatic layer 80 is an indium tin oxide (ITO) layer 301 .
  • ITO indium tin oxide
  • the antistatic layer 80 may also be made of the same metal as the first metal layer 20 and/or the second metal layer 60 .
  • the GOA protection circuit 3 comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
  • the diode is an I-type.
  • the I-type design helps to reduce space and not take up extra space.
  • material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
  • PFA transparent perfluoroalkoxy
  • an end of the antistatic layer 80 is connected to the GOA protection circuit 3 , and another end thereof is overlapped with the STV signal line 202 , the VSS signal line 203 , and the LC signal line 204 .
  • static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
  • I-type diode GOA protection circuit is disposed in the GOA circuit. This design helps to reduce space without taking up extra space. The static electricity is discharged through the GOA protection circuit, which effectively avoids damage to the GOA circuit during electrostatic discharge. When testing the panel, it will not have a substantial impact on function of the pad.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A gate driver on array (GOA) circuit and a display panel including the same are provided. The GOA circuit includes: a GOA drive signal line including a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.

Description

FIELD OF INVENTION
The present disclosure relates to the field of display panel manufacturing technologies, and more particularly to a gate driver on array (GOA) circuit and a display panel including the same.
BACKGROUND OF INVENTION
Gate driver on array (GOA) designs usually use an array process to make a gate line scan driving signal circuit on an array substrate to realize a driving method of line-by-line scan of a gate. GOA will inevitably use a pad to complete various test functions. A tip of an instrument used in the test will be stuck in the pad. At this time, electrostatic discharge is easy to occur, which will damage a panel. This makes the pad unable to perform corresponding functions and affects stability of the panel.
SUMMARY OF INVENTION
An object of the present application is to provide a gate driver on array (GOA) protection circuit to solve issues of electrostatic discharge of needles during testing in the prior art.
In order to solve the above issues, an embodiment of the present application provides a GOA circuit, comprising: a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line. In this design, static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
In the GOA circuit according to an embodiment of the present application, the GOA protection circuit comprises: a transparent substrate; a first metal layer disposed on a side surface of the transparent substrate; an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate; an active layer disposed on a side surface of the insulating layer away from the first metal layer; a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole; a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole; a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
In the GOA circuit according to an embodiment of the present application, the antistatic layer is electrically connected to the first metal layer through the deep hole.
In the GOA circuit according to an embodiment of the present application, the antistatic layer is electrically connected to the second metal layer through the shallow hole.
Advantages of this design are that static electricity is discharged through the antistatic layer, which effectively avoids damage to a GOA drive signal line during electrostatic discharge, and does not have a substantial impact on function of a pad when testing a panel.
In the GOA circuit according to an embodiment of the present application, the antistatic layer is an indium tin oxide (ITO) layer.
In the GOA circuit according to an embodiment of the present application, the GOA protection circuit comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
In the GOA circuit according to an embodiment of the present application, the diode is an I-type. The I-type design helps to reduce space and not take up extra space.
In the GOA circuit according to an embodiment of the present application, material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
In the GOA circuit according to an embodiment of the present application, an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
An embodiment of the present application further provides a display panel using the above GOA circuit, comprising: a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line. In this design, static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
In the display panel according to an embodiment of the present application, the GOA protection circuit comprises: a transparent substrate; a first metal layer disposed on a side surface of the transparent substrate; an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate; an active layer disposed on a side surface of the insulating layer away from the first metal layer; a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole; a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole; a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
In the display panel according to an embodiment of the present application, the antistatic layer is electrically connected to the first metal layer through the deep hole.
In the display panel according to an embodiment of the present application, the antistatic layer is electrically connected to the second metal layer through the shallow hole.
In the display panel according to an embodiment of the present application, the antistatic layer is an indium tin oxide (ITO) layer.
In the display panel according to an embodiment of the present application, the GOA protection circuit comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
In the display panel according to an embodiment of the present application, the diode is an I-type. The I-type design helps to reduce space and not take up extra space.
In the display panel according to an embodiment of the present application, material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
In the display panel according to an embodiment of the present application, an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
Beneficial effects of the present application are that, compared with the prior art, a GOA circuit and a display panel including the same provided in embodiments of the present application include an I-type diode GOA protection circuit in the GOA circuit. This design helps to reduce space without taking up extra space. The static electricity is discharged through the GOA protection circuit, which effectively avoids damage to the GOA circuit during electrostatic discharge. When testing the panel, it will not have a substantial impact on function of the pad.
DESCRIPTION OF DRAWINGS
FIG. 1 is a top view of a GOA circuit structure in an embodiment of the present application.
FIG. 2 is a cross-sectional view of the GOA protection circuit along A-A direction of FIG. 1 .
 DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The structure and function of the preferred embodiment of the present application will be described in detail below with reference to the accompanying drawings of the description. Obviously, the embodiment described below is only one of many aspects of the present application, and belongs to a part of the detailed technology of the present application.
The terms used in the specification of the present application are only used to describe specific embodiments, and are not intended to show the concepts of the present application. Unless the context clearly indicates a different meaning, expressions used in the singular encompass expressions in the plural. In this specification, it should be understood that terms such as “including”, “having”, and “containing” are intended to indicate the possibility of features, numbers, steps, actions, or combinations thereof disclosed in this specification. It is not intended to exclude the possibility that one or more other features, numbers, steps, actions, or a combination thereof may be present or may be added. The same reference numerals in the drawings refer to the same parts.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Referring to FIG. 1 , an embodiment of the present application provides a GOA circuit 1, comprising: a GOA drive signal line 2 comprising a voltage common (VCOM) signal line 201, a start vertical (STV) signal line 202, a reference voltage (VSS) signal line 203, and a low-frequency clock (LC) signal line 204; and a GOA protection circuit 3, wherein an end of the GOA protection circuit 3 is connected to the VCOM signal line 201, and another end thereof is electrically connected to the STV signal line 202, the VSS signal line 203, and the LC signal line 204. In this design, static electricity is released through an antistatic layer, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
Referring to FIG. 1 and FIG. 2 , in an embodiment of the present application, the GOA protection circuit 3 comprises: a transparent substrate 10; a first metal layer 20 disposed on a side surface of the transparent substrate 10; an insulating layer 30 disposed on a side surface of the first metal layer 20 away from the transparent substrate 10 and the side surface of the transparent substrate 10 near the first metal layer 20; an active layer 40 disposed on a side surface of the insulating layer 30 away from the first metal layer 20; a doped layer 50 disposed on a side surface of the active layer 40 away from the insulating layer 30 and having a first via hole; a second metal layer 60 disposed on a side surface of the doped layer 50 away from the active layer 40 and having a second via hole; a passivation layer 70 disposed on a side surface of the second metal layer 60 away from the doped layer 50 and the side surface of the active layer 40 away from the insulating layer 30, covering the doped layer 50 and the second metal layer 60; and an antistatic layer 80 disposed on a side surface of the passivation layer 70 away from the second metal layer 60 and having at least one deep hole and at least one shallow hole.
In an embodiment of the present application, the antistatic layer 80 is electrically connected to the first metal layer 20 through the deep hole.
In an embodiment of the present application, the antistatic layer 80 is electrically connected to the second metal layer 60 through the shallow hole.
Advantages of this design are that static electricity is discharged through the antistatic layer, which effectively avoids damage to a GOA drive signal line during electrostatic discharge, and does not have a substantial impact on function of a pad when testing a panel.
In an embodiment of the present application, the antistatic layer 80 is an indium tin oxide (ITO) layer. However, in other embodiments of the present application, the antistatic layer 80 may also be made of the same metal as the first metal layer 20 and/or the second metal layer 60.
In an embodiment of the present application, the GOA protection circuit 3 comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
In an embodiment of the present application, the diode is an I-type. The I-type design helps to reduce space and not take up extra space.
In an embodiment of the present application, material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
In an embodiment of the present application, an end of the antistatic layer 80 is connected to the GOA protection circuit 3, and another end thereof is overlapped with the STV signal line 202, the VSS signal line 203, and the LC signal line 204. In this design, static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
An embodiment of the present application further provides a display panel using the above GOA circuit 1, comprising: a GOA drive signal line 2 comprising a voltage common (VCOM) signal line 201, a start vertical (STV) signal line 202, a reference voltage (VSS) signal line 203, and a low-frequency clock (LC) signal line 204; and a GOA protection circuit 3, wherein an end of the GOA protection circuit 3 is connected to the VCOM signal line 201, and another end thereof is electrically connected to the STV signal line 202, the VSS signal line 203, and the LC signal line 204. In this design, static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
In an embodiment of the present application, the GOA protection circuit 3 comprises: a transparent substrate 10; a first metal layer 20 disposed on a side surface of the transparent substrate 10; an insulating layer 30 disposed on a side surface of the first metal layer 20 away from the transparent substrate 10 and the side surface of the transparent substrate 10 near the first metal layer 20; an active layer 40 disposed on a side surface of the insulating layer 30 away from the first metal layer 20; a doped layer 50 disposed on a side surface of the active layer 40 away from the insulating layer 30 and having a first via hole; a second metal layer 60 disposed on a side surface of the doped layer 50 away from the active layer 40 and having a second via hole; a passivation layer 70 disposed on a side surface of the second metal layer 60 away from the doped layer 50 and the side surface of the active layer 40 away from the insulating layer 30, covering the doped layer 50 and the second metal layer 60; and an antistatic layer 80 disposed on a side surface of the passivation layer 70 away from the second metal layer 60 and having at least one deep hole and at least one shallow hole.
In an embodiment of the present application, the antistatic layer 80 is electrically connected to the first metal layer 20 through the deep hole.
In an embodiment of the present application, the antistatic layer 80 is electrically connected to the second metal layer 60 through the shallow hole.
Advantages of this design are that static electricity is discharged through the antistatic layer, which effectively avoids damage to a GOA drive signal line during electrostatic discharge, and does not have a substantial impact on function of a pad when testing a panel.
In an embodiment of the present application, the antistatic layer 80 is an indium tin oxide (ITO) layer 301. However, in other embodiments of the present application, the antistatic layer 80 may also be made of the same metal as the first metal layer 20 and/or the second metal layer 60.
In an embodiment of the present application, the GOA protection circuit 3 comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
In an embodiment of the present application, the diode is an I-type. The I-type design helps to reduce space and not take up extra space.
In an embodiment of the present application, material of the passivation layer may be silicon oxide, and/or silicon oxynitride, and/or silicon nitride, or may be a transparent perfluoroalkoxy (PFA).
In an embodiment of the present application, an end of the antistatic layer 80 is connected to the GOA protection circuit 3, and another end thereof is overlapped with the STV signal line 202, the VSS signal line 203, and the LC signal line 204. In this design, static electricity is released through the GOA protection circuit, which can effectively prevent damage to a GOA drive signal line during electrostatic discharge, and will not have a substantial impact on function of a pad when testing a panel.
In summary, in embodiments of the present application, I-type diode GOA protection circuit is disposed in the GOA circuit. This design helps to reduce space without taking up extra space. The static electricity is discharged through the GOA protection circuit, which effectively avoids damage to the GOA circuit during electrostatic discharge. When testing the panel, it will not have a substantial impact on function of the pad.
The above are the preferred embodiments provided by the present application, but the protection scope of the present application is not limited by specific embodiments. Those skilled in the art can make structural element replacements and other changes within the scope of the present application. Such changes as replacements should also fall within the protection scope of the present application.

Claims (20)

What is claimed is:
1. A gate driver on array (GOA) circuit, comprising:
a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and
a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line;
wherein the GOA protection circuit comprises a first diode, a second diode, and a third diode, and the first diode, the second diode, and the third diode are connected in parallel.
2. The GOA circuit according to claim 1, wherein the GOA protection circuit comprises:
a transparent substrate;
a first metal layer disposed on a side surface of the transparent substrate;
an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate;
an active layer disposed on a side surface of the insulating layer away from the first metal layer;
a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole;
a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole;
a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and
an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
3. The GOA circuit according to claim 2, wherein the antistatic layer is electrically connected to the first metal layer through the deep hole.
4. The GOA circuit according to claim 2, wherein the antistatic layer is electrically connected to the second metal layer through the shallow hole.
5. The GOA circuit according to claim 2, wherein the antistatic layer is an indium tin oxide (ITO) layer.
6. The GOA circuit according to claim 1, wherein the diode is an I-type.
7. The GOA circuit according to claim 2, wherein material of the passivation layer comprises a transparent perfluoroalkoxy (PFA).
8. The GOA circuit according to claim 2, wherein an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
9. A display panel using the GOA circuit according to claim 1, comprising:
a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and
a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line.
10. The display panel according to claim 9, wherein the GOA protection circuit comprises:
a transparent substrate;
a first metal layer disposed on a side surface of the transparent substrate;
an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate;
an active layer disposed on a side surface of the insulating layer away from the first metal layer;
a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole;
a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole;
a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and
an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
11. The display panel according to claim 10, wherein the antistatic layer is electrically connected to the first metal layer through the deep hole.
12. The display panel according to claim 10, wherein the antistatic layer is electrically connected to the second metal layer through the shallow hole.
13. The display panel according to claim 10, wherein the antistatic layer is an indium tin oxide (ITO) layer.
14. The display panel according to claim 10, wherein material of the passivation layer comprises a transparent perfluoroalkoxy (PFA).
15. The display panel according to claim 10, wherein an end of the antistatic layer is connected to the GOA protection circuit, and another end thereof is overlapped with the STV signal line, the VSS signal line, and the LC signal line.
16. A gate driver on array (GOA) circuit, comprising:
a GOA drive signal line comprising a voltage common (VCOM) signal line, a start vertical (STV) signal line, a reference voltage (VSS) signal line, and a low-frequency clock (LC) signal line; and
a GOA protection circuit, wherein an end of the GOA protection circuit is connected to the VCOM signal line, and another end thereof is electrically connected to the STV signal line, the VSS signal line, and the LC signal line;
wherein the GOA protection circuit comprises:
a transparent substrate;
a first metal layer disposed on a side surface of the transparent substrate;
an insulating layer disposed on a side surface of the first metal layer away from the transparent substrate and the side surface of the transparent substrate;
an active layer disposed on a side surface of the insulating layer away from the first metal layer;
a doped layer disposed on a side surface of the active layer away from the insulating layer and having a first via hole;
a second metal layer disposed on a side surface of the doped layer away from the active layer and having a second via hole;
a passivation layer disposed on a side surface of the second metal layer away from the doped layer and the side surface of the active layer away from the insulating layer, covering the doped layer and the second metal layer; and
an antistatic layer disposed on a side surface of the passivation layer away from the second metal layer and having at least one deep hole and at least one shallow hole.
17. The GOA circuit according to claim 16, wherein the antistatic layer is electrically connected to the first metal layer through the deep hole.
18. The GOA circuit according to claim 16, wherein the antistatic layer is electrically connected to the second metal layer through the shallow hole.
19. The GOA circuit according to claim 16, wherein the antistatic layer is an indium tin oxide (ITO) layer.
20. The GOA circuit according to claim 16, wherein material of the passivation layer comprises a transparent perfluoroalkoxy (PFA).
US16/625,024 2019-11-25 2019-12-11 GOA circuit and display panel including same Active 2041-06-05 US11521528B2 (en)

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