JP4807365B2 - Semiconductor device, display device and electronic apparatus - Google Patents

Description

The present invention relates to a semiconductor device, a display device, and an electronic apparatus, and more particularly to a display device in which a drive circuit is built on an active matrix substrate.

In semiconductor devices, countermeasures against electrostatic breakdown (ESD), in which an unintended high voltage due to static electricity or various noise phenomena is applied inside the device and damage to the insulating film due to destruction, is an important issue. Various protection circuits have been devised to prevent this. For example, Patent Document 1 and Patent Document 2 propose a circuit that discharges abnormal voltage applied to wiring to GND or the like by appropriately combining diodes. However, since ordinary semiconductor devices are formed on a silicon wafer, which is a conductor, they are rarely charged in the semiconductor device and are mainly used when static electricity enters through the input terminals. In general, a protection circuit is formed between the semiconductor elements to be operated, that is, immediately after the input terminal, so that a high voltage entering from the input terminal is prevented from propagating to the element.

On the other hand, in a display device using an active element such as a thin film transistor (TFT), which has been rapidly spread in recent years, the device is formed on an insulating substrate. There is a problem that electric breakdown easily occurs. For this reason, countermeasures against static electricity are taken by, for example, forming an antistatic wiring called a guard ring or a short ring on the outer periphery of the active matrix circuit.

Recently, a display device with a built-in drive circuit that uses a polysilicon TFT with polysilicon as an active layer and incorporates a drive circuit for the display device to improve definition, reduce costs, and ensure reliability is practical. Is becoming popular. In such a device, since the countermeasures against static electricity in the drive circuit apply the technique that has been used in the past on semiconductors on silicon wafers, only a protection circuit for protecting static electricity from the input terminal is built in, For the electrostatic protection of the active matrix circuit, a conventional method of a display device without a built-in driving circuit is used. The details of the prior art relating to protection of the drive circuit will be described below with reference to FIG.

  FIG. 11 is a block diagram of an active matrix substrate for VGA-LCD using polysilicon TFTs according to the prior art. Reference numerals 201-1 to 480 denote scanning lines of the active matrix circuit, which are driven by a scanning line driving circuit indicated by 800. Reference numerals 202-1 to 1920 denote data lines, and pixel transistors (401) and pixel electrodes (402) made of n-type TFTs are formed at intersections between the scanning lines and the data lines to drive the liquid crystal elements. ing.

Reference numerals 801-1 to 480 denote 480-stage scanning line driving unit circuits constituting the scanning line driving circuit (800), which are constituted by CMOS circuits. For a specific circuit configuration example of the scanning line driving unit circuits (801-1 to n), see, for example, FIG.

Each scanning line drive unit circuit (801-1 to 480) is connected to the low potential power supply wiring (750) and the high potential power supply wiring (751), and power is supplied through these. The low-potential power supply wiring (750) is connected to the low-potential power supply terminal (650), and the high-potential power supply wiring (751) is connected to the high-potential power supply terminal (651), respectively. A power supply IC is connected to the terminal (651) through an FPC or the like, and reference potentials VS and VD are supplied to the terminals (651). Here, VS <VD.

Further, a signal (for example, a clock signal) necessary for the operation of each scanning line driving unit circuit (801-1 to 480) is supplied from an external IC through signal wiring (701, 702) and signal terminals (601, 602).

Here, static electricity and noise current invade through the low potential power supply terminal (650), the high potential power supply terminal (651), and the signal terminals (601, 602) to configure each scanning line driving unit circuit (801-1 to 480). In order to prevent the TFT from being destroyed, an electrostatic protection circuit (ESD1 to 4) is provided between each input terminal (601, 650, 651) and each scanning line drive unit circuit (801-1 to 480). Specific examples of the electrostatic protection circuits (ESD1 to ESD4) include Patent Document 1 and Patent Document 2.

Japanese Patent No. 2884946 Japanese Patent No. 3141511

However, the drive circuit on the insulating substrate is less likely to escape the charge than the circuit on the silicon wafer and is easily charged. In addition, when the drive circuit of the display device is built on a glass substrate, the circuit area is larger than an IC manufactured on a general silicon wafer. There is a problem that the protection against is not sufficient particularly in the process during production. This is because there is a possibility that static electricity will be charged at any position on the board in the manufacturing process, and the electrostatic protection circuit will operate when the distance from the charged position to the electrostatic protection circuit is long and the wiring resistance is high. This is because there is a case where a transistor in a circuit closer to the front may be electrostatically destroyed. Such a problem is a common problem even in the case of a semiconductor device using an SOI substrate.

In addition, in the case of an insulating substrate, a large current may flow on the wiring due to electrostatic induction when a strong electrostatic discharge occurs outside the substrate even in the finished product state after completion of the manufacturing process. There is a possibility of destroying the circuit of the place.

Furthermore, the present invention shows a countermeasure against the problem that the potential on the wiring instantaneously fluctuates when a large amount of current flows through the circuit.

A semiconductor device according to the present invention includes a wiring extending from a first end to which an electrical signal is supplied from the outside and a second end from which the electrical signal is not supplied from the outside, a semiconductor circuit connected to the wiring, and a semiconductor among the wirings A first protection circuit disposed between the circuit and the first end portion to protect the semiconductor circuit; and a second protection circuit disposed between the semiconductor circuit and the second end portion of the wiring to protect the semiconductor circuit. And a buffer circuit disposed between the first end of the wiring and the semiconductor circuit.

In addition to the first protection circuit installed in the vicinity of the first end where the electrical signal is supplied from the outside, the second protection circuit is installed at the second end where the electrical signal of the wiring is not supplied from the outside. This has the effect that sufficient protection can be obtained even at a location away from the first end where the electrical signal is supplied from the outside .

Furthermore, a configuration is proposed in which a plurality of semiconductor circuits are connected to the wiring, and a third protection circuit is provided that is disposed between adjacent semiconductor circuits in the wiring and protects the plurality of semiconductor circuits . Thus, static electricity and noise from the input terminal can be prevented, and a semiconductor circuit far from the input terminal can be protected. In addition, it is more preferable that a plurality of protection circuits be arranged at a substantially constant interval so that the semiconductor circuits connected on the wiring can be protected evenly.

A semiconductor device according to a preferred aspect of the present invention includes a first power supply line branched from a high potential power supply line and a second power supply line branched from a low potential power supply line, and the buffer circuit includes a first power supply line and A fourth protection circuit interposed between the second power supply wiring and disposed on the opposite side of the branch point from the high potential power supply wiring across the buffer circuit of the first power supply wiring to protect the buffer circuit; And a fifth protection circuit disposed on the opposite side of the branch point from the low-potential power supply wiring across the buffer circuit in the second power supply wiring to protect the buffer circuit.

In a further preferred aspect, the buffer circuit includes a first NOT circuit to which an electric signal is input and a second NOT circuit connected in series to the first NOT circuit, and a connection point between the first power supply wiring and the first NOT circuit. Between the connection point between the first protection circuit and the connection point between the second NOT circuit and the sixth protection circuit disposed between the connection point between the first NOT circuit and the second NOT circuit. And a seventh protection circuit for protecting the buffer circuit.

  In another aspect of the present invention, the buffer circuit includes a first NOT circuit to which an electrical signal is input and a second NOT circuit connected in series to the first NOT circuit, and each of the first NOT circuit and the second NOT circuit is complementary. The channel width of the transistor of the second NOT circuit is larger than the channel width of the transistor of the first NOT circuit.

In a preferred aspect of the present invention, the wiring is a low-potential power wiring or a high-potential power wiring that supplies a power supply potential to the semiconductor circuit, or a signal input wiring that transmits a signal to the semiconductor circuit.

A semiconductor device according to a preferred aspect of the present invention includes a substrate on which a semiconductor circuit is disposed, and the wiring is formed from the first corner to the second corner of the substrate along the periphery of the substrate. The one protection circuit is disposed at the first corner of the substrate, and the second protection circuit is disposed at the second corner of the substrate. Arranging the protection circuit at such a position is advantageous because a large protection circuit can be arranged without increasing the size (frame) of the peripheral portion of the substrate .

In addition, a display device using the semiconductor device of the present invention and an electronic device equipped with the display device are advantageous in terms of cost because electrostatic breakdown is less likely to occur during the process, and the display is less likely to cause a voltage drop of the power source. It has the effect of high quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an active matrix substrate with a built-in scanning line driving circuit in a first embodiment for realizing a liquid crystal display device using the scanning line driving circuit of the present invention. On the active matrix substrate (101), 480 scanning lines (201-1 to 480) and 1920 data lines (202-1 to 1920) are formed orthogonally, and 480 capacitance lines (203) -1 to 480) are arranged in parallel and alternately with the scanning lines (201-1 to 480). The data lines (202-1 to 1920) are connected to data line input terminals (302-1 to 1920). The capacitor lines (203-1 to 480) are short-circuited to each other and connected to the common potential input terminal (303). The opposing conduction portion (304) is also connected to the common potential input terminal (303).

A pixel switching element (401-nm) made of an N-channel field effect thin film transistor is formed at each intersection of the scanning line (201-n) and the data line (202-m), and its gate electrode scans. The source and drain electrodes are connected to the data line (202-m) and the pixel electrode (402-nm), respectively, to the line (201-n). The pixel electrode (402-n-m) forms a capacitance line (203-n) and an auxiliary capacitor, and when assembled as a liquid crystal display device, it is also a counter substrate electrode (COM) across the liquid crystal element. Form a capacitor.

The scanning lines (201-1 to 480) are connected to a scanning line driving circuit (800) formed by integrating polysilicon thin film transistors on an active matrix substrate and supplied with a driving signal. Here, the scanning line driving circuit is composed of 480 scanning line driving unit circuits (801-1 to 480) connected to each scanning line. In the present invention, the semiconductor circuit in the claims is a scanning line driving circuit (800). In addition, the wiring in the claims indicates a CLK signal wiring (701), an SP signal wiring (702), a high potential power wiring (751), a low potential power wiring (750), and the like.

A CLK signal wiring (701), an SP signal wiring (702), a high potential power wiring (751), and a low potential power wiring (750) are connected to the scanning line driving circuit (800), and a clock start pulse signal and each power source are connected. A potential is supplied. Here, the CLK signal wiring (701), the SP signal wiring (702), the high potential power wiring (751), and the low potential power wiring (750) are the CLK signal terminal (601), the high potential power terminal (651), and the low potential power supply. These terminals are connected to a terminal (650), and these terminals are connected to an external IC through an FPC or the like to supply a desired signal / power supply potential.

CLK signal terminal (601), SP signal terminal (602), high potential power supply terminal (651), low potential power supply signal terminal (650) and CLK signal wiring (701), SP signal wiring (702), high potential power supply wiring ( 751), the first to fourth protection circuits (ESD1 to ESD4) are connected to the connection wiring between the low-potential power supply wiring (750), and static electricity and noise current from each terminal (601, 602, 651, 650). Prevents the TFT in the scan line driver circuit 800 from being destroyed.

Further, as seen from the CLK signal terminal (601), the high potential power supply terminal (651), and the low potential power supply signal terminal (650) on the CLK signal wiring (701), the high potential power supply wiring (751), and the low potential power supply wiring (750). Fifth to seventh protection circuits (ESDs 11 to 13) are also arranged at the opposite ends across the scanning line driving circuit (800). Accordingly, it is possible to prevent a situation in which a unit (for example, n = 1) far from the terminal in the scanning line driving unit circuit (801-n) is destroyed by static electricity during the production of the active matrix substrate. Further, the fifth to seventh protection circuits (ESDs 11 to 13) can be arranged without increasing the substrate area if arranged at the corners of the active matrix substrate, particularly at the corners opposite to the input terminals.

FIG. 4 is a specific circuit configuration example of the protection circuits (ESD1 to ESD13). The source electrode and gate electrode of the p-type transistor (504) are connected to the high-potential power supply VH, and the drain electrode is connected to the wiring to be protected. The source electrode and gate electrode of the n-type transistor (502) are connected to the low-potential power supply VL. The electrode is connected to the protected wiring. Here, the signal level applied to the wiring to be protected must be VH or less and VL or more. When the potential of the protected power supply is outside the range of VH to VL due to static electricity or the like, the n-type transistor (502) or p-type transistor (504) is turned on, and the abnormal current is transferred to the reference potential VH wiring or the reference potential VL wiring. Miss. Further, the protective resistance (503) can prevent the potential of the wiring from rapidly rising and the n-type transistor (502) or the p-type transistor (504) from being destroyed. Here, VH and VL generally use the highest power supply and the lowest power supply in the circuit, but VH = VD and VL = VS may be used.

Although the protection circuits (ESD1 to ESD13) have the same configuration here, it goes without saying that each protection circuit may have a different circuit configuration depending on the necessity. In particular, with respect to the internal protection circuits (ESDs 11 to 13), the protection circuits (ESDs 1 to 4) of the input unit are required to have relatively high protection performance. For this reason, for example, the first protection circuit (ESD1) may have a circuit configuration having higher protection performance than the fifth protection circuit (ESD11). Specifically, the n-type transistor (502) and the p-type transistor (504) are used. The channel width of the first protection circuit (ESD1) may be made larger.

FIG. 5 shows a configuration example of the scanning line driving unit circuits (801-1 to 480), which is a combination of a static shift register using two clock inverters, a NAND circuit, and a NOT circuit. Note that the OUT terminal of the n-th stage (n <480) scanning line driving unit circuit (801-n) is connected to the IN terminal of the (n-1) th stage scanning line driving unit circuit (801-n-1), The IN terminal of the 480th scanning line driving unit circuit (801-480) is connected to the SP signal wiring (702).

FIG. 6 is a perspective configuration diagram (partially sectional view) of the transmissive liquid crystal display device showing the first embodiment. The active matrix substrate (101) shown in FIG. 1 and a counter substrate (901) on which a common electrode is formed by depositing ITO on a color filter are bonded together by a sealing material (920), and a nematic liquid crystal material is formed therein. (910) is enclosed. In addition, a conductive material is disposed on the opposing conductive portion (304) on the active matrix substrate (101) and is short-circuited with the common electrode of the counter substrate (901).

The data line input terminals (302-1 to 1920), the common potential input terminal (303), the CLK signal terminal (601), the SP signal terminal (602), the high potential power supply terminal (651), and the low potential power supply terminal (650) It is connected to one or a plurality of external ICs (940) through an FPC (930) mounted on a terminal and supplied with necessary electric signals and potentials.

Further, an upper deflecting plate (951) is disposed outside the active matrix substrate, and a lower deflecting plate (952) is disposed outside the opposing substrate, and they are disposed so that their polarization directions are orthogonal (crossed Nicols). Further, a backlight (960) is attached under the deflection plate to complete. The backlight (960) may be a cold cathode tube with a light guide plate or a scattering plate attached thereto, or may be a unit that emits light entirely from an EL element. Although not shown, if necessary, the periphery may be covered with an outer shell, or a protective glass or acrylic plate may be attached on the upper deflection plate.

Since this liquid crystal display device is less likely to cause electrostatic breakdown due to static electricity during the manufacturing process or after completion, compared with the conventional liquid crystal display device, the yield is high and the reliability is high.

FIG. 2 is a block diagram showing a driving circuit in a second embodiment for realizing a liquid crystal display device using the scanning line driving circuit of the present invention. This figure corresponds to the inside of the chain line A frame in FIG.

In this embodiment, the drive circuit (800) as viewed from the input protection circuits (ESD1 to 3) and the input terminals (601, 650, 651) from the terminals (601, 650, 651) to the scanning line drive circuit (800). As well as the internal protection circuits (ESDs 11 to 13) at the end of the drive circuit (800), the 240th unit drive circuit (801-240) and the 241st unit drive circuit (801-) 241) are also provided with eighth to tenth protection circuits (ESDs 21 to 23). Thereby, electrostatic breakdown can be prevented near the intermediate stage (n = 240) far from both the vicinity of the terminal and the terminal. In this embodiment, the protection circuit is added only to the intermediate stage, but the number of protection circuits in the middle may be increased according to the scale and size of the circuit. For example, in addition to the location of this embodiment, between the 120th stage (801-120) and the 121st stage (801-121) and between the 360th stage (801-360) and the 361st stage (801-361). If a protection circuit is included, it is more preferable. If there is no problem in circuit area, it is most desirable if all the protection circuits are inserted between all stages. However, in any case, the interval between the protection circuits should be almost constant, otherwise electrostatic breakdown is likely to occur only where the interval is wide.

The configuration of the active matrix substrate and the details of the protection circuit and the drive circuit other than those described above are the same as those of the first embodiment, and the active matrix including the circuit shown in FIG. Since the liquid crystal display device using the substrate may have the same configuration as that of the first embodiment, the description thereof will be omitted.

FIG. 3 is a configuration diagram of an active matrix substrate with a built-in scanning line driving circuit in the first embodiment for realizing a liquid crystal display device using the scanning line driving circuit of the present invention.

In this embodiment, unlike the first and second embodiments, the CLK signal and the SP signal supplied to the scanning line driving circuit (800) are directly input from the CLK signal terminal (601) and the SP signal terminal (602). Instead, the driving capability is temporarily amplified by the buffer circuits (810-1, 810-2) and then input to the scanning line driving circuit 800. With such a configuration, even if the signal driving capability of the external IC is not so high, signals can be driven without a large delay even in a large-area panel.

FIG. 7 shows a specific circuit configuration of the buffer circuits (810-1, 810-2) in the third embodiment. The first NOT circuit (821) and the second NOT circuit (822) are connected in series in two stages, and the second NOT circuit (822) is formed by a transistor constituting the first NOT circuit (821). ) Has a larger channel width (W), for example, W = 250 μm for the first NOT circuit (821) and W = 1000 μm for the second NOT circuit (822). The power wiring 850 is a branch wiring branched from the low potential power wiring 750 in FIG. 3, and the power wiring 851 is a branch wiring branched from the high potential power wiring 751 in FIG. However, eleventh and twelfth protection circuits (ESD41, ESD42) are provided on the opposite side (that is, the ends of the branch wirings 850, 851) across the buffer circuit (810-1, 810-2). Has been placed.

With such a configuration, the portion sandwiched between the first protection circuit (ESD11) and the eleventh protection circuit (ESD41) on the low potential power supply wiring (750) and the second potential on the high potential power supply wiring (751). The portion between the protection circuit (ESD12) and the twelfth protection circuit (ESD42) and the buffer circuit (810-1, 810-2) are connected, and the first protection circuit (ESD11) Compared with the case where there is only one, the protection performance when static electricity is charged in the buffer circuits (810-1, 810-2) is remarkably improved.

FIG. 8 shows another example of the specific circuit configuration of the buffer circuits (810-1, 810-2) in the third embodiment. Compared with the configuration of FIG. 7, the connection point of the first NOT circuit (821) and the connection point of the second NOT circuit (822) on the low potential power supply wiring (750) and the high potential power supply wiring (751) are connected. A thirteenth protection circuit (ESD51) and a fourteenth protection circuit (ESD51) are added on the line. Other configurations are the same as those in FIG. Thus, the protection performance is further improved by the presence of the internal protection circuit at the midpoint between the circuits.

In addition, the present embodiment has another effect of preventing voltage fluctuation of the power source. The resistance of the power supply wiring is finite. Therefore, when a large current is instantaneously consumed by the complementary circuit, the voltage of the power supply wiring varies partially and instantaneously. In this embodiment, the channel width of the second NOT circuit (822) is as large as W = 1000 μm, and when the input signal is inverted, a very large current flows instantaneously and the potential of the power supply fluctuates. (The time depends on the capacitance value of the wiring to which the output terminal of the second NOT circuit (822) is connected).

FIG. 10 shows the result of simulating potential fluctuations in the buffer circuit configured as shown in FIGS. 7 and 8, and will be described in detail using this. A graph 880 is a signal waveform output from the first NOT circuit (821) and input to the second NOT circuit (822), in which the potential changes from VS to VD. At this time, the n-type transistor constituting the second NOT circuit (822) is turned ON, and the potential of the output terminal is written to VS. At this time, a large current flows on the low-potential power supply wiring (850), a voltage gradient is generated, and the potential is slightly increased instantaneously. In order to prevent this, the wiring width of the low-potential power supply wiring (850) may be increased, but may be limited due to the circuit area. 881 is a graph showing the potential in the vicinity of the second NOT circuit (822) of the low-potential power line (850) when the low-potential power line (850) is fixed to a certain wiring width and no particular measures are taken. It can be seen that the voltage rises instantaneously.

When such a phenomenon occurs, not only the driving ability of the buffer circuit is lowered, but also another circuit connected to the low potential power wiring (850) may be adversely affected. That is, the voltage drop as shown in the graph 881 is transmitted to other circuits through the low-potential power supply wiring (850), causing the malfunction in the worst case and affecting the output accuracy in the case of the analog circuit. Such a problem becomes more conspicuous in a TFT circuit on an insulating substrate having a larger circuit area than a circuit on a silicon wafer, particularly in a driver circuit of a display device.

Next, a graph 882 shows a result when an appropriate capacitance element is added to the low potential power supply wiring. In this case, since the instantaneously flowing current is supplied from the capacitive element to some extent, the voltage drop can be reduced. That is, in order to reduce the voltage drop, a capacitor element may be added to the power supply wiring. The larger the capacitance of the capacitive element, the higher the effect of reducing the voltage drop. However, as a result of the study by the author, the maximum current flowing in the power supply wiring is I (A) and the allowable time for the voltage drop is t (seconds). At this time, if a capacitance element of I × t × 0.1 (F) or more is used, the voltage drop is effective, and if it is less than this, no significant effect is observed. Here, the allowable time t during which the voltage drop occurs is determined by the maximum operation speed of the logic circuit and the sampling time of the analog circuit. In general, a TFT using polysilicon does not have a high operation speed, and the upper limit is an operation at about several tens of MHz. That is, power supply voltage fluctuations of 10 ns or less have almost no problem. The maximum current flowing through the power supply is equal to the maximum instantaneous current consumption of the circuit.

Therefore, assuming that the maximum current consumed by the circuit is I (A) and the allowable time during which the voltage drop occurs is t (seconds), the voltage can be increased by adding a capacity of I × t × 0.1 (F) or more to the power supply. This is effective in reducing the descent, and at this time, t ≦ 10 ⁻⁸ (seconds) may be satisfied. Further, it is desirable that the other party to which the capacitor is connected is another power supply wiring whose potential does not fluctuate. However, when such a capacitor is arranged, the circuit area increases. Therefore, when a plurality of protection circuits are arranged on the power supply wiring as in the present embodiment, the space between the power supply wiring protected by the capacitance component on the protection circuit and the reference potential power supply wiring (VH, VL) in the protection circuit. Capacity. In this case, the circuit functions both as a protection circuit and as a countermeasure against power supply potential fluctuations, which is extremely advantageous in terms of circuit area.

When such a drop in power supply potential fluctuation is expected, it is necessary to provide a protection circuit in the vicinity of a circuit with a large current consumption, otherwise the voltage fluctuation is also caused by the power supply wiring resistance from the circuit with a large current consumption to the protection circuit. Will occur. Specifically, the distance (X) along the power supply wiring from the circuit with large current consumption to the protection circuit should be smaller than the distance (Y) along the power supply wiring from the circuit with high current consumption to the input terminal. It is.

The specific configurations of the first to second and eleventh to fourteenth protective circuits (ESD 1 to 2, 11 to 14) may be as shown in FIG. The description of the circuit configuration in FIG. 4 is omitted because it is the same as in the first embodiment, but in this configuration as well, between the wiring protected by the gate-drain capacitance component of the transistor and the high potential power source VH and the low potential power source VL To add capacity. In the configuration of FIG. 9, the first capacitor (505) and the second capacitor (506) are added compared to the configuration of FIG. 4, so that when a strong voltage is applied instantaneously, the protection resistor (503) The function of preventing damage to the n-type transistor (502) and the p-type transistor (504) by operating as a CR circuit in combination is improved, and the protected wiring, the high-potential power supply VH, and the low-potential power supply Since the capacity of the VL can be adjusted by the first capacity (505) and the second capacity (506), the configuration is more effective as a countermeasure against a power supply voltage drop.

In such a configuration, the capacitance of the protection circuit (ESD1, 2, 11, 12) connected to the low potential power supply wiring (750) and the high potential power supply wiring (751) is equal to the signal wiring (701, 702). ) Should be smaller than the capacity of the protection circuit (ESD3, 4, 13) connected to. This is because the potential of the signal wiring fluctuates, so that if the capacitance with the signal wiring is too large, crosstalk occurs between the reference power supply wiring connected to the signal line in the protection circuit. Specifically, if the configuration of the protection circuit is as shown in FIG. 9, the protection circuit (ESD1, 2, 11, 12) connected to the low potential power supply wiring (750) and the high potential power supply wiring (751). The first capacitance (505) and the second capacitance (ESD3, 4, 13) of the protection circuit (ESD3, 4, 13) in which the first capacitance (505) and the second capacitance (506) are connected to the signal wiring (701, 702). 506) may be set to be larger.

Similarly, when the complementary circuit other than the buffer circuit as described in this embodiment, for example, the data line driving circuit, the DAC circuit, the power supply circuit, the level shift circuit, the memory circuit, etc. are built in the active matrix substrate, the branch power supply is used. It is desirable to provide a protection circuit at the end and in the middle of the wiring, and it is more preferable that all the circuits are placed on the power supply wiring between the protection circuit and the protection circuit. In addition, it is preferable from the viewpoint of reducing power supply noise to install a protection circuit having a certain capacity in front and rear stages of the circuit that consumes a large amount of current. Assuming that (typically t ≦ 10 ⁻⁸ (seconds)), a capacity of I × t × 0.1 (F) or more may be used as a guide.

The configuration of the active matrix substrate other than those described above, the details of the protection circuit and the drive circuit, etc. are the same as those of the first embodiment, and the active matrix substrate as shown in FIG. 3 was used. Since the liquid crystal display device may have the same configuration as that of the first embodiment, the description thereof is omitted.

In the first embodiment, only the protection circuit of FIG. 4 has been described. However, the same effect as that of the third embodiment can be obtained by providing the protection circuit of FIG.

The present invention is not limited to the above-described embodiment, and a liquid crystal display device using an active matrix substrate incorporating a data line driving circuit, a DAC, a power supply circuit, and the like may be used. In this case, the contents of the present invention may be applied to each circuit, or only a part of the circuits may be applied if there is a problem such as layout. Even when applied to the scanning line driving circuit, not only the shift register type as in the embodiment but also various sequential selection circuits may be used.

In addition, the protection circuit is not limited to the configurations of the embodiments and the preceding examples, and any configuration among various protection circuits proposed so far can be used.

Further, an amorphous silicon thin film transistor may be used instead of polysilicon as the transistor. Further, instead of forming a thin film transistor on an insulating substrate, an active matrix substrate in which pixel switching elements and driving circuits are formed on a crystalline silicon wafer may be used.

Further, the liquid crystal display device may be a reflection type or a semi-transmission type instead of the transmission type as in the embodiment, or may be a projection light valve instead of the direct view type. Further, not only the normally white mode but also the normally black mode may be used as in the embodiment. Particularly in this case, the alignment mode of the liquid crystal may be a vertical alignment mode or a horizontal electric field switching mode.

1 is an active matrix substrate configuration diagram for explaining a first embodiment of the present invention. FIG. The scanning line drive circuit diagram for demonstrating the 2nd Example of this invention. The active matrix substrate block diagram for demonstrating the 3rd Example of this invention. The protection circuit diagram for demonstrating the Example of this invention. FIG. 5 is a circuit diagram of a scanning line driving unit for explaining an embodiment of the present invention. 1 is a perspective view (partially sectional view) of a liquid crystal display device for explaining a first embodiment of the present invention. The buffer circuit diagram for demonstrating the 3rd Example of this invention. The buffer circuit diagram for demonstrating another embodiment of the 3rd Example of this invention. The protection circuit diagram for demonstrating the 3rd Example of this invention. The graph of the result of having simulated the reference potential fluctuation for explaining the 3rd example of the present invention. The active matrix substrate block diagram for demonstrating a prior art example.

Explanation of symbols

101: Active matrix substrates 201-1 to 480: Scan lines 1 to 480
202-1 to 1920: Data lines 1 to 1920
ESD1 to 4: First to fourth protection circuits ESD11 to 13: Fifth to seventh protection circuits ESD21 to 23: Eighth to tenth protection circuits 800: Scan line drive circuits 801-1 to 480: Scan lines Drive unit circuit

Claims (10)

Wiring extending from a first end to which an electric signal is supplied from the outside and a second end from which the electric signal is not supplied from the outside;
A semiconductor circuit connected to the wiring;
A first protection circuit disposed between the semiconductor circuit and the first end of the wiring to protect the semiconductor circuit;
A second protection circuit disposed between the semiconductor circuit and the second end portion of the wiring to protect the semiconductor circuit;
A buffer circuit disposed between the first end of the wiring and the semiconductor circuit;
A semiconductor device comprising: A plurality of semiconductor circuits are connected to the wiring,
A third protection circuit disposed between the semiconductor circuits adjacent to each other in the wiring and protecting the plurality of semiconductor circuits
The semiconductor device according to claim 1 comprising: A first power supply line branched from the high potential power supply line;
A second power supply line branched from the low potential power supply line,
The buffer circuit is interposed between the first power supply wiring and the second power supply wiring,
A fourth protection circuit that is disposed on the opposite side of the branch point from the high-potential power supply wiring across the buffer circuit in the first power supply wiring and protects the buffer circuit;
A fifth protection circuit which is disposed on the opposite side of the branch point from the low-potential power line across the buffer circuit in the second power line and protects the buffer circuit;
The semiconductor device according to claim 1, further comprising: The buffer circuit includes a first NOT circuit to which the electrical signal is input, and a second NOT circuit connected in series to the first NOT circuit,
A sixth protection circuit disposed between a connection point of the first power supply wiring and the first NOT circuit and a connection point of the second NOT circuit and protecting the buffer circuit;
A seventh protection circuit disposed between a connection point of the second power supply wiring and the first NOT circuit and a connection point of the second NOT circuit and protecting the buffer circuit;
A semiconductor device according to claim 3 comprising: The buffer circuit includes a first NOT circuit to which the electrical signal is input, and a second NOT circuit connected in series to the first NOT circuit,
Each of the first NOT circuit and the second NOT circuit is composed of complementary transistors,
The channel width of the transistor of the second NOT circuit is larger than the channel width of the transistor of the first NOT circuit.
3. The semiconductor device according to claim 1 or 2. The wiring is a low potential power wiring or a high potential power wiring for supplying a power potential to the semiconductor circuit.
The semiconductor device according to claim 1. The wiring is a signal input wiring that transmits a signal to the semiconductor circuit.
The semiconductor device according to claim 1. Comprising a substrate on which the semiconductor circuit is disposed;
The wiring is formed from the first corner to the second corner of the substrate along the periphery of the substrate,
The first protection circuit is disposed at the first corner of the substrate;
The second protection circuit is disposed at the second corner of the substrate.
The semiconductor device according to claim 1. A display device comprising the semiconductor device according to claim 1. An electronic apparatus comprising the display device according to claim 9.

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