KR100987709B1 - Liquid crystal display apparatus - Google Patents

Abstract

In the LCD, the lower substrate includes a driver for outputting a driving signal and a display unit for displaying an image in response to the driving signal. The upper substrate has a common electrode and faces the lower substrate. The liquid crystal is interposed between the lower substrate and the upper substrate, and the insulating film partially covers the driving portion, and is formed on the lower substrate at an uneven height. Therefore, the liquid crystal display device can prevent the malfunction of the gate driving circuit.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY APPARATUS}

1 is a cross-sectional view showing a general liquid crystal display device.

FIG. 2 is an output waveform diagram of the gate driver shown in FIG. 1.

3 illustrates a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view of the liquid crystal display shown in FIG. 3.

FIG. 5 is a diagram illustrating the gate driving circuit shown in FIG. 3 in detail.

FIG. 6 is a layout view of each stage shown in FIG. 5.

7 is a layout view illustrating an arrangement structure of an organic insulating layer according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 121: conductive film

140: organic insulating film 150: gate driving circuit

200: upper substrate 300: liquid crystal

400: liquid crystal display GDA: gate driving region

LA: Wiring part CA: Circuit part

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing a malfunction of the gate driving circuit.

1 is a cross-sectional view illustrating a general liquid crystal display, and FIG. 2 is an output waveform diagram of the gate driver shown in FIG. 1. However, in the graph shown in FIG. 2, the x axis represents time and the y axis represents voltage.

Referring to FIG. 1, the liquid crystal display device 40 may include an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 interposed between the color filter substrate 20 and the array substrate 10. Is done. The liquid crystal display 40 displays an image while changing an arrangement angle of the liquid crystal layer 30 by an electric field formed between the color filter substrate 20 and the array substrate 10 by a signal from the outside.

The array substrate 10 includes a display area DA and a peripheral area PA adjacent to the display area DA. In the display area DA, a plurality of pixels are provided in a matrix form. Each of the plurality of pixels includes a gate line, a data line, a thin film transistor (hereinafter, referred to as a TFT) 11 connected to the gate line and the data line, and a pixel electrode 12 coupled to the TFT 11.

In the peripheral area PA, a gate driving circuit 16 for applying a driving voltage to the gate line is integrated by a TFT process. As such, by integrating the gate driving circuit 16 on the array substrate 10, the number, volume, and size of the assembling process of the liquid crystal display device 40 can be reduced.                         

On the other hand, the color filter substrate 20 is provided with a common electrode 24 facing the pixel electrode 20 with the liquid crystal layer 30 therebetween. The cell gap holding member 25 is provided on the common electrode 24 to maintain the cell gap of the liquid crystal display 40 corresponding to the display area DA.

Since the common electrode 24 also faces the gate driving circuit 16 with the liquid crystal layer 30 interposed therebetween, the parasitic capacitance C is generated between the gate driving circuit 16 and the common electrode 24. .

In FIG. 2, the solid line represents the normal waveform G1 and the dotted line represents the waveform G2 distorted by the parasitic capacitance C. In FIG. As shown in FIG. 2, the highest voltage in the distorted waveform G2 was about 5 V or lower than the highest voltage in the normal waveform G1.

As a result, the parasitic capacitance C distorts or delays the signal output from the gate driving circuit 16, thereby degrading the display characteristics of the liquid crystal display device 40. FIG.

In addition, when an external force is applied to the peripheral area PA of the liquid crystal display 40, the common electrode 24 and the gate driving circuit 16 are shorted to cause a malfunction of the gate driving circuit 16.

Accordingly, the present invention provides a liquid crystal display device for preventing the malfunction of the gate driving circuit.

A liquid crystal display according to an aspect of the present invention includes a lower substrate, an upper substrate, a liquid crystal, and an insulating film.

The lower substrate includes a driver for outputting a driving signal and a display unit for displaying an image in response to the driving signal. The upper substrate has a common electrode and faces the lower substrate.

The liquid crystal is interposed between the lower substrate and the upper substrate, and the insulating film partially covers the driving unit, and is formed on the lower substrate at an uneven height.

According to the liquid crystal display device, the insulating film covers the circuit area of the driving part and exposes the contact area. In this case, the insulating layer is formed to have a first height in a portion adjacent to the contact region, and has a second height that is higher than the first height as it moves away from the contact region. Accordingly, the insulating layer may electrically insulate the driving unit from the common electrode, thereby preventing malfunction of the gate driving circuit.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

3 is a view showing a liquid crystal display device according to an embodiment of the present invention, Figure 4 is a cross-sectional view of the liquid crystal display device shown in FIG.

3 and 4, the liquid crystal display device 400 according to an exemplary embodiment of the present invention may include a lower substrate 100, an upper substrate 200 facing the lower substrate 100, and the lower substrate 100. ) And the upper substrate 200 are interposed between the liquid crystal layer 300.

The lower substrate 100 provides a display area DA for displaying an image and a gate and data driving areas GDA and DDA for driving the display area DA by providing a driving signal to the display area DA. Include.

A plurality of pixels is provided in a matrix form on the first substrate 101 corresponding to the display area DA. Each of the plurality of pixels is coupled to the pixel TFT 110 and the pixel TFT 110 connected to the data lines D1 to Dm, the gate lines G1 to Gn orthogonal to the data lines D1 to Dm, and are transparent. The pixel electrode 120 is formed of a conductive material.

In detail, the pixel TFT 110 has a gate electrode 111 connected to the corresponding gate lines G1 to Gn, a source electrode 112 is connected to the data lines D1 to Dm, and a drain electrode. 113 has a configuration connected to the pixel electrode 120. The pixel electrode 120 is made of indium tin oxide (ITO) or indium zinc oxide (IZO).

A passivation layer 130 and an organic insulating layer 140 are interposed between the pixel TFT 110 and the pixel electrode 120. The passivation layer 130 is made of an inorganic insulating layer such as silicon nitride layer (SiNx) or silicon oxide layer (SiOx) and is formed on the pixel TFT 110 to protect the pixel TFT 110. Thereafter, the organic insulating layer 140 made of a photosensitive acrylic resin is formed on the passivation layer 130.

In order to connect the pixel electrode 120 only with the drain electrode 113 of the pixel TFT 110, the passivation layer 130 and the organic insulating layer 140 expose a pixel contact hole exposing the drain electrode 113. 141 is formed. Therefore, the pixel electrode 120 is electrically connected to the drain electrode 113 through the pixel contact hole 141.

In the gate driving area GDA, a gate driving circuit 150 including a plurality of driving TFTs 151 is formed under the same process conditions and time as the pixel TFT 110 provided in the display area DA. Accordingly, the gate driving circuit 150 is connected to one end of the gate lines G1 to Gn to output a gate driving signal to the gate lines G1 to Gn. The plurality of driving TFTs 151 are electrically coupled to each other by the conductive film 121. The conductive layer 121 is formed under the same process conditions and time as the pixel electrode 120 provided in the display area DA.

The gate driving circuit 150 formed in the gate driving region GDA will be described in detail later with reference to FIGS. 4 and 5.

Meanwhile, the data driving circuit 160 provided in the form of a chip is attached to the data driving region DDA by a bonding process. Therefore, when gate driving signals are sequentially output to the gate lines G1 to Gn, the data driving circuit 160 outputs an image signal to the data lines D1 to Dm.

The passivation layer 130 extends from the display area DA to the gate driving area GDA to protect the driving TFT 151. In addition, the organic insulating layer 140 includes the gate driving region GDA as well as the display region DA.

The gate driving region GDA may include a first region A1 in which the driving TFT 151 is formed and a second region A2 in which the conductive film 121 is formed. The organic insulating layer 140 is formed only in the first region A1 while exposing the second region A2 to cover the driving TFT 151. Sidewalls of the organic insulating layer 140 adjacent to the second region A2 have a step shape. That is, the organic insulating layer 140 is stacked to the first height h1 from the first substrate 101 adjacent to the second region A2, and the organic insulating layer 140 is separated from the second region A2. The second height h2 is higher than the first height h1.

As such, the stacking height of the organic insulating layer 140 is adjusted according to the distance from the second region A2, so that the conductive layer is formed on the sidewall of the organic insulating layer 140 adjacent to the second region A2. This prevents the swelling of 121. Therefore, it is possible to prevent the conductive film 121 and the adjacent conductive film from being electrically connected to each other.

The upper substrate 200 is a substrate including a color filter 220, a light shielding film 210, a planarization film 230, and a common electrode 240 on the second substrate 201. In the display area DA, the common electrode 24 faces the pixel electrode 120 with the liquid crystal layer 300 interposed therebetween. In addition, in the gate driving region GDA, the common electrode 240 faces the gate driving circuit 150.

The organic insulating layer 140 is interposed between the first region of the gate driving region GDA and the common electrode 240. Here, the organic insulating layer 140 has a lower dielectric constant than that of the liquid crystal layer 300. In general, since the capacitance is proportional to the dielectric constant, parasitic capacitance generated between the gate driving circuit 150 and the common electrode 240 may be reduced.

FIG. 5 is a view illustrating in detail the gate driving circuit illustrated in FIG. 3, and FIG. 6 is a layout view of each stage illustrated in FIG. 5. In FIG. 6, the region divided by the dotted line is the first region A1 in which the organic insulating layer is formed.

Referring to FIG. 5, the gate driving area GDA includes a circuit part CA and a wiring part LA. The circuit part CA includes a gate driving circuit 150 including one shift register including a plurality of stages SRC1 to SRCn + 1 corresponding to a plurality of gate lines. The output terminals of the respective stages are not only connected to corresponding gate lines, but also connected to the previous stage and the next stage, respectively, so that the plurality of stages are cascaded.

Meanwhile, as shown in FIG. 6, each stage includes a plurality of driving TFTs including a gate electrode, a gate insulating film, an active layer, an ohmic contact layer, a source electrode, and a drain electrode. Thereafter, the driving TFTs are entirely covered by a protective film formed in the display area. The driving TFTs are organically coupled to each other, and when combined, gate electrodes and source electrodes in different layers may be coupled, or gate and drain electrodes may be coupled.

In this case, a contact region for exposing the gate electrode and the source electrode or the gate electrode and the drain electrode is formed in the passivation layer. Thereafter, a conductive film is formed on the passivation layer corresponding to the contact region. Therefore, the gate electrode and the source electrode or the gate electrode and the drain electrode are electrically connected by the conductive film.

5 and 6, the gate driving circuit 150 is electrically connected to the wiring part LA including a plurality of signal wires. The signal wires receive various signals from the outside and provide the signals to the gate driving circuit. The signal lines may include a start signal line ST, a first clock line CK, a second clock line CKB, a ground voltage line VSS, and a driving voltage line VDD.

The signal lines extend from the first stage SRC1 to the last stage SRCn + 1 of the gate driving circuit 150 in a direction parallel to the data line. The wiring part LA further includes a plurality of connection wires CL1, CL2, and CL3 to electrically connect the signal wires to the stages. The connection lines CL1 to CL2 apply various signals to each stage by electrically connecting the corresponding signal lines with each stage.

The signal wires and the connection wires are formed on different layers so as to connect the signal wires only with corresponding connection wires. When the signal wirings are formed on the same layer as the gate electrode, a gate insulating film is formed on the signal wirings, and the connection wirings are formed on the same layer as the source and drain electrodes on the gate insulating film. Thereafter, the passivation layer made of an inorganic insulating layer is formed on the connection wires.

In this case, a contact hole for exposing the connection lines or the signal lines is formed in the passivation layer and the gate insulating layer. Thereafter, a conductive film made of ITO or IZO is formed on the protective film. The conductive layer is connected to the connection line and the corresponding signal line through the contact hole, thereby electrically connecting the connection line and the corresponding signal line.

Therefore, various signals provided to the signal wires may be provided to each stage through the connection wires.

As shown in FIG. 6, the organic insulating layer 140 (shown in FIG. 4) is formed on the first area A1 in which the plurality of driving TFTs are formed, and the second area A2 in which contact holes are formed. (Shown in 4) is exposed. Therefore, even after the conductive film is formed corresponding to the second region A2, the conductive film and the lower metal may be electrically connected through the contact hole.

The stacking height of the organic insulating layer 140 is lower as the second region A2 approaches. In particular, as shown in FIG. 4, sidewalls of the organic insulating layer 140 adjacent to the second region A2 have a step shape. Therefore, the phenomenon in which the conductive films formed in the second region A2 adjacent to the sidewall of the organic insulating layer 140 may be electrically connected may be prevented.

Meanwhile, the organic insulating layer 140 covers only the circuit portion CA in which the gate driving circuit 150 is formed in the gate driving region GDA and exposes the wiring portion LA including the signal wirings. The signal wires are connected to the connection wires so as to be connected to each stage of the gate driving circuit 150.

As described above, since most of the signal wires have contact areas connected to the connection wires and the distance between the contact areas is narrow, the organic insulating layer 140 is completely removed from the portion corresponding to the wiring part LA. do. Therefore, the phenomenon in which the conductive films provided in the contact regions formed in the wiring part LA are electrically connected can be prevented.

7 is a layout view illustrating an arrangement structure of an organic insulating layer according to another exemplary embodiment of the present invention.

Referring to Fig. 7, each stage consists of a plurality of driving TFTs. In particular, each stage includes first and second driving TFTs T1 and T2 that are relatively larger than the remaining driving TFTs of the plurality of driving TFTs.

Since the first and second driving TFTs T1 and T2 are implemented as amorphous-silicon thin film transistors, they have very small electron mobility. When the liquid crystal display becomes large, a high voltage amplitude must be applied to the gate line to drive it. Therefore, the size of the first and second driving TFTs T1 and T2 is inevitably increased.

In this case, the organic insulating layer 140 is formed in the gate driving region GDA to cover the wiring part LA and the circuit part CA. In particular, in the circuit part CA, the organic insulating layer 140 is laminated to a first thickness in the third region A3 in which the first and second driving TFTs T1 and T2 are formed, and the third region A3. ) And the second region except for the second region A2, which is a contact region, are stacked to have a second thickness thinner than the first thickness.

The total area of the third area A3 is not only larger than the total area of the fourth area A4, but the second area A2 does not exist in the third area A3. Therefore, the thickness of the organic insulating layer 140 formed in the third region A3 may be sufficiently increased. As a result, parasitic capacitance generated between the gate driving circuit 150 and the common electrode 240 provided on the upper substrate 200 (refer to FIG. 4) may be reduced.

According to such a liquid crystal display device, the insulating layer is formed on the lower substrate to cover the driving unit, and has a different thickness for each region in the driving unit to electrically insulate the driving unit and the common electrode.

Accordingly, malfunction of the gate driving circuit can be prevented by reducing the parasitic capacitance generated between the driver and the common electrode.

In addition, the insulating layer may have a first thickness adjacent to the contact region where the conductive layer is formed, and have a second thickness that is larger than the first thickness as the contact layer is farther away from the contact region, thereby preventing short-circuiting of the conductive layers. have. As a result, malfunction of the gate driving circuit can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (6)

A lower substrate comprising a driving unit for outputting a driving signal and a display unit for displaying an image in response to the driving signal; An upper substrate having a common electrode and facing the lower substrate; A liquid crystal interposed between the lower substrate and the upper substrate; And An insulating film partially covering the driving part and formed at an uneven height on the lower substrate, The driving unit includes a contact region in which a conductive film is formed and a circuit region adjacent to the contact region. And the insulating film covers the circuit area and exposes the contact area. delete 2. The liquid crystal display of claim 1, wherein the insulating layer has a first height from the lower substrate at a portion adjacent to the contact region, and has a second height higher than the first height as it moves away from the contact region. Device. 4. The liquid crystal display device according to claim 3, wherein the sidewalls of the insulating film adjacent to the contact region have a step shape. The shift driver of claim 1, wherein the driving unit comprises a shift register in which a plurality of stages are cascaded. Each stage, A pull-up unit configured to output the driving signal to an output terminal; A pull-down part for discharging a driving signal applied to the output terminal; A pull-up driving unit turning on the pull-up unit in response to an output signal of a previous stage; And And a pull-down driving unit which turns on the pull-down unit in response to the leading end of the output signal of the next stage. The method of claim 5, wherein the insulating film, A first insulating film covering the pull-up part and the pull-down part and having a first height from the lower substrate; And And a second insulating film covering the pull-up driving part and the pull-down driving part and having a second height lower than the first height.

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