US10748834B2 - Stack type power module and method of manufacturing the same - Google Patents
Stack type power module and method of manufacturing the same Download PDFInfo
- Publication number
- US10748834B2 US10748834B2 US16/179,264 US201816179264A US10748834B2 US 10748834 B2 US10748834 B2 US 10748834B2 US 201816179264 A US201816179264 A US 201816179264A US 10748834 B2 US10748834 B2 US 10748834B2
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- United States
- Prior art keywords
- power semiconductor
- substrate layer
- gate
- stack type
- power module
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- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 239000004065 semiconductor Substances 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229920005989 resin Polymers 0.000 claims description 24
- 239000011347 resin Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000945 filler Substances 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229920006336 epoxy molding compound Polymers 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 34
- 230000008569 process Effects 0.000 description 25
- 125000006850 spacer group Chemical group 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 238000005245 sintering Methods 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000009413 insulation Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 101001045744 Sus scrofa Hepatocyte nuclear factor 1-beta Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 235000015096 spirit Nutrition 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L21/4814—Conductive parts
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/293—Organic, e.g. plastic
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- H01L23/293—Organic, e.g. plastic
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- H01L23/367—Cooling facilitated by shape of device
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- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present disclosure relates to a stack type power module and a method of manufacturing the same, and more particularly, to a stack type power module and a method of manufacturing the same for securing A structure capable of having high-density and high-integration, and cost competitiveness of thin and light chips.
- the automotive motor requires an alternating current (AC) current and the battery is a direct current (DC) power source
- an inverter that can convert the DC current of the battery into the AC current is required.
- the inverter includes a power module for generating the polarity of the current.
- FIG. 1 is a diagram illustrating a general stack type power module.
- the wire bonding 50 is mainly used as an inexpensive and simple connection method, but it is necessary to secure additional space inside the module due to the loop height of the wire.
- the stack type power module 1 should have a spacer 60 for securing additional space therein, which is not only difficult to reduce the thickness of the power module 1 but also has the limit raising the cost.
- the stack type power module 1 it is necessary for the stack type power module 1 to secure a structure capable of having high density and high integration of thin and light chips, and cost competitiveness as well as securing heat resistance and heat dissipation property.
- An object of the present disclosure is to provide a stack type power module and a method of manufacturing the same for securing the structure capable of having high-density and high-integration of thin and light chips, and cost competitiveness by removing a spacer because a power semiconductor and a lead frame are connected directly through a substrate without interconnecting them via wire bonding.
- a stack type power module in accordance with an embodiment of the present disclosure includes: a power semiconductor having a gate and an emitter, each of which having a pad shape, adjacent to each other on one surface of the power semiconductor, and a collector having a pad shape on another surface of the power semiconductor; an upper substrate layer stacked on an upper portion of the power semiconductor, and electrically connected to a metal layer that has a lower surface with which the collector, and a lower substrate layer stacked on a lower portion of the power semiconductor, and electrically connected to the metal layer that has an upper surface with which each of the gate and the emitter is in contact.
- Each of the upper substrate layer and the lower substrate layer can be formed with the stacked structure of an upper metal layer, a ceramic layer, and a lower metal layer as the path discharging the heat generated in the power semiconductor to the outside.
- At least any one of the lower metal layer of the upper substrate layer and the upper metal layer of the lower substrate layer can be electrically connected with the power semiconductor.
- the power semiconductor can be rotated 180° through a flip chip process to be stacked conversely.
- the power semiconductor can perform an ON/OFF switching control through the gate, and converts a DC current inputted from the collector into an AC current to output it to the emitter.
- An insulating resin can be filled through an underfill process.
- the insulating resin can be filled into the space between a plurality of terminal pads of the gate and the space between terminal pads between the gate and the emitter.
- the insulating resin can be a thermosetting epoxy resin containing silica or silicon dioxide (SiO 2 ) filler.
- the shape of the filler can be spherical, and the maximum diameter of the filler can be adjusted to be equal to or less than half of the narrowest width of the space to be filled.
- the content of the filler can be adjusted to 50 weight % or more, based on the total weight of the insulating resin, and the thermal expansion coefficient can be adjusted to 20 (ppm/° C.) or less.
- the stack type power module can further include a first lead frame and a second lead frame connected to the metal layer formed on the upper surface of the lower substrate layer, respectively; and the first lead frame can receive a control signal delivered to the gate from the outside, and the second lead frame can receive an AC current delivered to the outside from the emitter.
- the stack type power module can further include a molding portion forming an Epoxy Molding Compound (EMC) molding for the power semiconductor, the upper substrate layer, the lower substrate layer, the first lead frame, and the second lead frame.
- EMC Epoxy Molding Compound
- a method of manufacturing a stack type power module in accordance with another embodiment of the present disclosure includes: printing a circuit pattern for bonding a power semiconductor to an upper surface of a lower substrate layer; bonding a gate and an emitter, each of which has a pad shape, spaced apart from each other on one surface of the power semiconductor through a flip chip process for the power semiconductor to a metal layer attached to the upper surface of the lower substrate layer; filling an insulating resin in a peripheral space of the gate and the emitter through an underfill process; connecting a first lead frame and a second lead frame to the metal layer attached to the upper surface of the lower substrate layer; and bonding a collector having a pad shape on another surface of the power semiconductor to a metal layer attached to a lower surface of an upper substrate layer.
- the method of manufacturing the stack type power module can further include performing an EMC molding after the bonding of the power semiconductor and the upper substrate layer.
- the filling of the insulating resin can be filled in a space between a plurality of terminal pads of the gate, and a space between terminal pads between the gate and the emitter.
- the filling of the insulating resin can include filling the insulating resin in a dispensing method using a syringe and then hardening it in a high temperature chamber.
- the present disclosure can secure the structure capable of having high-density and high-integration of thin and light chips, and cost competitiveness by removing the spacer because the power semiconductor and the lead frame are connected directly through the substrate without interconnecting them via the wire bonding.
- the present disclosure can eliminate the spacer to reduce the number of processes and parts in the entire manufacturing process, thus enhancing the cost competitiveness.
- the present disclosure can eliminate the spacer to reduce a Z-axis height to reduce the overall size, thus achieving high density.
- the present disclosure can enhance the heat radiation performance through the direct contact between the power semiconductor, the upper substrate layer, and the lower substrate layer.
- FIG. 1 is a diagram illustrating a general stack type power module.
- FIG. 2 is a diagram illustrating a stack type power module in accordance with an embodiment of the present disclosure.
- FIG. 3 is a diagram illustrating a pad of a power semiconductor.
- FIG. 4 is a diagram illustrating a method of manufacturing the stack type power module in accordance with the embodiment of the present disclosure.
- FIG. 5 is a diagram explaining a flip chip process in FIG. 4 .
- FIG. 6 is a diagram explaining an underfill process in FIG. 4 .
- ⁇ unit means a software or hardware component, such as FPGA or ASIC, which performs certain tasks. However, “ ⁇ unit” does not mean to be limited to software or hardware.
- the term “ ⁇ unit” can advantageously be configured to reside on the addressable storage medium and configured to execute on one or more processors.
- “ ⁇ unit” can include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.
- components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.
- the functionality provided for in the components and “ ⁇ units” can be combined into fewer components and “ ⁇ units” or further separated into additional components and “
- FIG. 2 is a diagram illustrating a stack type power module in accordance with an embodiment of the present disclosure
- FIG. 3 is a diagram illustrating a pad of a power semiconductor.
- a stack type power module 100 in accordance with an embodiment of the present disclosure can secure the structure capable of having high-density and high-integration of thin and light chips, and cost competitiveness by removing a spacer because a power semiconductor and a lead frame are connected directly through a substrate without interconnecting them via wire bonding.
- the stack type power module 100 directly connects the power semiconductor to the substrate conversely through a flip chip process, thus connecting terminal pads of the power semiconductor and a lead frame through the substrate without the wire bonding.
- the stack type power module 100 needs to secure the insulation property of the terminal pad of the power semiconductor by directly bonding the terminal pad of the power semiconductor to the substrate.
- the stack type power module 100 is filled with an insulating resin through an underfill process in order to secure the insulation property against the terminal pad of the power semiconductor.
- the stack type power module 100 is implemented as a Double Side Cooling (DSC) structure is described, but it is not limited thereto and also applicable to the case implemented as an One Side Cooling structure.
- DSC Double Side Cooling
- the stack type power module 100 includes an upper substrate layer 110 , a lower substrate layer 120 , a power semiconductor 130 , an insulating resin 140 , first and second lead frames 150 a and 150 b , and a molding portion 160 .
- the upper substrate layer 110 and the lower substrate layer 120 are the substrate on which a metal layer is printed on both surfaces of a ceramic layer and have high heat dissipation and high insulation characteristics.
- the upper substrate layer 110 is stacked with a first upper metal layer 111 , a first ceramic layer 112 , and a first lower metal layer 113
- the lower substrate layer 120 is stacked with a second upper metal layer 121 , a second ceramic layer 122 , and a second lower metal layer 123 .
- each of the upper substrate layer 110 and the lower substrate layer 120 has a metal layer formed on both surfaces thereof to form a double-sided cooling structure. That is, the power semiconductor 130 is interposed between the upper substrate layer 110 and the lower substrate layer 120 .
- This can improve heat dissipation performance as the power semiconductor 130 directly contacts with the upper substrate layer 110 and the lower substrate layer 120 by eliminating the existing spacer. Accordingly, the heat generated in the power semiconductor 130 is discharged to the outside through the path connected to the first lower metal layer 113 , first ceramic layer 112 , and first upper metal layer 111 of the upper substrate layer 110 , and can be discharged to the outside through the path connected to the second upper metal layer 121 , second ceramic layer 122 , and second lower metal layer 123 of the lower substrate layer 120 .
- a circuit pattern for electrical connection with the power semiconductor 130 is printed on at least any one of the first lower metal layer 113 of the upper substrate layer 110 and the second upper metal layer 121 of the lower substrate layer 120 , which can be used as an intermediate substrate for bonding the power semiconductor 130 through the flip chip process of the power semiconductor 130 .
- the first and second ceramic layers 112 and 122 are insulating materials such as aluminum oxide (Al 2 O 3 ) and silicon nitride (Si 3 N 4 ), and the first upper metal layer 111 , the first lower metal layer 113 , the second upper metal layer 121 , and the second lower metal layer 123 can be made of copper (Cu), aluminum (Al), or the like.
- the upper substrate layer 110 and the lower substrate layer 120 can be formed of various materials and structures such as Thick Film Copper (TFC), PCB, FPCB (Flexible PCB), Insulated Metal Substrate (IMS), Pre-molded Subs, Direct Bonded Copper (DBC), and ceramic.
- TFC Thick Film Copper
- PCB PCB
- FPCB Flexible PCB
- IMS Insulated Metal Substrate
- Pre-molded Subs Pre-molded Subs
- DBC Direct Bonded Copper
- the power semiconductor 130 can be a large-power and high-speed switching device for converting a DC current into an AC current, for example, an Insulated Gate Bipolar mode Transistor (IGBT) or the like.
- IGBT Insulated Gate Bipolar mode Transistor
- the power semiconductor 130 is rotated by 180° through the flip chip process to be bonded conversely unlike FIG. 1 .
- FIG. 1 if one surface of the power semiconductor 130 is bonded to the upper substrate layer 110 , the same surface of the power semiconductor 130 is bonded to the lower substrate layer 120 in FIG. 2 .
- the electrical connection relationship through wire bonding in FIG. 1 is formed in the electrical connection relationship through the lower substrate layer 120 in FIG. 2 .
- the power semiconductor 130 as a terminal for functioning as a switching element, includes a gate 131 , an emitter 132 , and a collector 133 and these terminals are formed on both surfaces thereof in the pad shape exposed to the outside for the electrical bonding of the upper substrate layer 110 and the lower substrate layer 120 .
- the power semiconductor 130 has the plurality of pad shape gates 131 and the single pad shape emitter 132 located on the same plane as the gate 131 formed one surface thereof, and has the single pad shape collector 133 formed on the other surface thereof.
- the gate 131 and the emitter 132 are bonded to and electrically connected to the metal layer formed on the upper surface of the lower substrate layer 120
- the collector 133 is bonded to and electrically connected to the metal layer formed on the lower surface of the upper substrate layer.
- the power semiconductor 130 performs ON/OFF switching control through the gate 131 , and converts a DC current inputted from the collector 133 into an AC current to supply it to the emitter 132 .
- the gate 131 is formed with a plurality of adjacent pads, and the emitter 132 is formed with a pad adjacent to the same plane as the gate 131 .
- the gate 131 and the emitter 132 are formed adjacent to each other on the same plane of the power semiconductor 130 and are electrically connected to the metal layer formed on the upper surface of the lower substrate layer 120 , an underfill process for ensuring insulation is performed. That is, the space between the terminal pads of the gate 131 and the emitter 132 is filled with the insulating resin 140 for ensuring electrical insulation through the underfill process.
- the insulating resin 140 is filled in ‘the space between the plurality of terminal pads in the gate 131 ’ and ‘the space between terminal pads between the gate 131 and the emitter 132 ’.
- the insulating resin 140 is a thermosetting epoxy resin containing silica or silicon dioxide (SiO 2 ) filler. In this time, the insulating resin 140 is filled by a dispensing method using a syringe instead of an injection method, and then cured in a high temperature chamber.
- the shape and size of the filler included in the insulating resin 140 can be adjusted to fill a fine space (gap).
- the shape of the filler can be a plate-like shape or a spherical shape, but a spherical shape may be used for facilitating fine space penetration.
- a maximum diameter thereof is adjusted to be less than half of the narrowest width of the space to be filled when spherical filler is used.
- the content of the filler is adjusted to 50 weight % or more, based on the total weight of the insulating resin, and thereby the thermal expansion coefficient is 20 (ppm/° C.) or less.
- the first and second lead frames 150 a and 150 b are bonded to the upper metal layer of the lower substrate layer 120 .
- the first and second lead frames 150 a and 150 b connect the power semiconductor 130 to an external circuit to transmit an electric signal. That is, the first lead frame 150 a is connected to the metal layer formed on the upper surface of the lower substrate layer 120 to receive a control signal delivered to the gate 131 of the power transistor 130 from the outside. Likewise, the second lead frame 150 b is connected to the metal layer formed on the upper surface of the lower substrate layer 120 to receive the AC current delivered to the outside from the emitter 132 of the power semiconductor 130 .
- the molding portion 160 is formed through an Epoxy Molding Compound (EMC) molding after the power semiconductor 130 is completely packaged as described above.
- EMC Epoxy Molding Compound
- the molding portion 160 seals the packaging structure of the power semiconductor 130 in order to protect the packaging structure of the power semiconductor 130 from external moisture or shock.
- the power semiconductor 130 and the first and second lead frames 150 a and 150 b are stacked with the upper substrate layer 110 or the lower substrate layer 120 through a bonding process.
- the bonding process can be, for example, solder/soldering, sinter paste/sintering, Transient Liquid Phase (TLP), or the like.
- solder/soldering a tin (Sn) based chemical composition is used, and an intermetallic compound is formed on the bonded surface and is bonded.
- silver (Ag) based sinter paste/sintering and copper (Cu) based sintering can be used.
- silver-based sinter paste/sintering bonds by making silver powder particles into paste form and sintering them at high temperature.
- the pressure can be atmospheric pressure or high pressure.
- Copper-based sinter paste/sintering bonds by making copper powder particles into paste form and sintering at high temperature/high pressure.
- the filler can be copper (Cu), copper oxide (CuO 2 ), copper-tin (Cu—Sn), or the like.
- TLP is a liquid-phase transition diffusion bonding process in which copper (Cu) and tin (Sn) are formed of an intermetallic compound of 100%. TLP is similar to the soldering, but the process time is longer than 1 hour.
- FIG. 4 is a diagram illustrating a method for manufacturing a stack type power module in accordance with the embodiment of the present disclosure
- FIG. 5 is a diagram explaining a flip chip process in FIG. 4
- FIG. 6 is a diagram explaining an underfill process in FIG. 4 .
- the lower substrate layer 120 is formed.
- a circuit pattern for bonding with the power semiconductor 130 is printed on the upper surface of the lower substrate layer 120 .
- the power semiconductor 130 is deposited on the lower substrate layer 120 through the solder printing.
- the power semiconductor 130 is rotated by 180° through the flip chip process to be bonded to the lower substrate layer 120 conversely.
- the gate 131 and emitter 132 of the power semiconductor 130 are bonded to the lower substrate layer 120 .
- the collector 133 of the power semiconductor 130 is bonded on the lower substrate layer 120 .
- the flip chip process can be carried out while being in an inverted state when receiving the power semiconductor 130 , it is possible to mount the chip with the mount equipment without special equipment. If it is necessary to rotate the power semiconductor 130 by 180°, the chip mounting is performed using two heads (head A and head B) as illustrated in FIG. 5 . That is, the power semiconductor 130 located on the ring frame is rotated by 180° by the head A (HA), and the power semiconductor 130 rotated by 180° moves from the head A (HA) to the head B (HB), and then mounted on the lower substrate layer 120 .
- heads head A and head B
- the underfill process is performed. That is, the space formed between the terminal pads of the gate 131 and the emitter 132 is filled with the insulating resin 140 .
- the insulating resin 140 is discharged using the syringe SG as illustrated in FIG. 6 to be filled in the space formed in the terminal pad.
- the first and second lead frames 150 a and 150 b are stacked on the lower substrate layer 120 through the solder printing.
- the first lead frame 150 a is connected with the gate 131 of the power semiconductor 130 through the circuit pattern printed on the upper surface of the lower substrate layer 120 instead of being connected with the gate 131 of the power semiconductor 130 through the wire bonding. If the first lead frame 150 a is connected with the gate 131 of the power semiconductor 130 through the wire bonding, a spacer is required, but herein, since the spacer is eliminated, the height in the Z-axis direction can be reduced.
- the upper substrate layer 110 is stacked on the collector 133 of the power semiconductor 130 through the solder printing.
- the bonding the spacer to the upper substrate layer 110 is further required. That is, as the spacer is eliminated, the upper substrate layer 110 does not require performing the upper package to bond the spacer.
- the method of manufacturing the stack type power module in accordance with the embodiment of the present invention excludes the inserting the spacer because the power semiconductor 130 and the first lead frame 150 a are not connected by the wire bonding, such that some of the overall manufacturing processes can be excluded.
- This can reduce the manufacturing processes and the number of parts, thereby contributing to improve the cost competitiveness, and additionally, reduce the height in the Z-axis direction by eliminating the spacer, thus expecting high density due to the size reduction.
- the method in accordance with some embodiments can be implemented in the form of program instructions that can be executed through various computer means to be recorded on a computer readable medium.
- the computer-readable medium can include program instruction, data file, data structure, and the like, alone or in combination thereof.
- the program instruction recorded on the medium can be those specially designed and constructed for the present disclosure, or can be available to those skilled in the art of computer software.
- Examples of a computer-readable media include magnetic media such as a hard disk, a floppy disk, and a magnetic tape, optical media such as CDROM and DVD, magneto-optical media such as a floptical disk, magneto-optical media such a floptical disk, and a hardware device specifically configured to store and execute program instructions such as ROM, RAM, and flash memory.
- Examples of the program instruction include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like.
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Abstract
Description
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US20210043466A1 (en) | 2019-08-06 | 2021-02-11 | Texas Instruments Incorporated | Universal semiconductor package molds |
KR102296270B1 (en) * | 2019-12-10 | 2021-09-01 | 현대모비스 주식회사 | Dual side cooling power module and manufacturing method of the same |
US11610861B2 (en) * | 2020-09-14 | 2023-03-21 | Infineon Technologies Austria Ag | Diffusion soldering with contaminant protection |
KR102459361B1 (en) * | 2020-12-14 | 2022-10-28 | 파워마스터반도체 주식회사 | Power module package |
US11646249B2 (en) * | 2020-12-29 | 2023-05-09 | Semiconductor Components Industries, Llc | Dual-side cooling semiconductor packages and related methods |
KR102442951B1 (en) | 2022-02-04 | 2022-09-15 | (주)아이에이파워트론 | Electrical connection and integrated fixtures in terminals in power modules |
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KR20150039155A (en) * | 2015-02-24 | 2015-04-09 | 페어차일드코리아반도체 주식회사 | Three-phase inverter package |
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2018
- 2018-04-23 KR KR1020180046840A patent/KR102552077B1/en active IP Right Grant
- 2018-11-02 US US16/179,264 patent/US10748834B2/en active Active
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US20080054425A1 (en) * | 2006-08-29 | 2008-03-06 | Denso Corporation | Power electronic package having two substrates with multiple electronic components |
KR101489325B1 (en) | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | Power module with stacked flip-chip and method of fabricating the same power module |
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KR101321282B1 (en) | 2011-06-17 | 2013-10-28 | 삼성전기주식회사 | Power module package and system module having the same |
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CN110391205A (en) | 2019-10-29 |
US20190326195A1 (en) | 2019-10-24 |
KR20190123099A (en) | 2019-10-31 |
KR102552077B1 (en) | 2023-07-06 |
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