US10199406B2 - Array substrate and manufacturing method thereof, display panel and display device - Google Patents

Array substrate and manufacturing method thereof, display panel and display device Download PDF

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Publication number
US10199406B2
US10199406B2 US15/175,700 US201615175700A US10199406B2 US 10199406 B2 US10199406 B2 US 10199406B2 US 201615175700 A US201615175700 A US 201615175700A US 10199406 B2 US10199406 B2 US 10199406B2
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Prior art keywords
opening region
active layer
photoresist
array substrate
gate insulating
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US20170025449A1 (en
Inventor
Wei Huang
Jiaqing Zhao
Linrun FENG
Wei Tang
Xiaojun Guo
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BOE Technology Group Co Ltd
Shanghai Jiaotong University
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BOE Technology Group Co Ltd
Shanghai Jiaotong University
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Assigned to SHANGHAI JIAO TONG UNIVERSITY, BOE TECHNOLOGY GROUP CO., LTD. reassignment SHANGHAI JIAO TONG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Guo, Xiaojun
Assigned to SHANGHAI JIAO TONG UNIVERSITY, BOE TECHNOLOGY GROUP CO., LTD. reassignment SHANGHAI JIAO TONG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, WEI
Assigned to SHANGHAI JIAO TONG UNIVERSITY, BOE TECHNOLOGY GROUP CO., LTD. reassignment SHANGHAI JIAO TONG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TANG, WEI
Assigned to SHANGHAI JIAO TONG UNIVERSITY, BOE TECHNOLOGY GROUP CO., LTD. reassignment SHANGHAI JIAO TONG UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FENG, Linrun
Assigned to BOE TECHNOLOGY GROUP CO., LTD., SHANGHAI JIAO TONG UNIVERSITY reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHAO, JIAQING
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • an active layer is formed in such a manner: firstly, forming a semiconductor layer, and then, etching the semiconductor layer, so as to reserve the semiconductor layer in a channel region as the active layer.
  • the reserved semiconductor layer i.e., the active layer
  • the reserved semiconductor layer can be damaged by a process for etching the semiconductor layer, and even if an etch stop layer is formed on the semiconductor layer and damage brought to the reserved semiconductor layer by etching cannot be completely avoided.
  • Embodiments of the present disclosure relate to an array substrate and a manufacturing method thereof, a display panel and a display device, which can avoid damage to the active layer in a process for forming a thin film transistor.
  • an embodiment of the present disclosure provides an array substrate manufacturing method, comprising: forming a source electrode and a drain electrode on a gate insulating layer; forming photoresist above the gate insulating layer and the source electrode and the drain electrode; etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode; and forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode.
  • an embodiment of the present disclosure provides an array substrate, comprising: a gate insulating layer; a source electrode and a drain electrode, arranged on the gate insulating layer; an active layer, formed on the gate insulating layer on which the source electrode and the drain electrode are formed and covering a part of the source electrode, a part of the drain electrode and the gate insulating layer between the source electrode and the drain electrode.
  • an embodiment of the present disclosure provides a display panel, comprising the array substrate as mentioned above.
  • an embodiment of the present disclosure provides display device, comprising the display panel as mentioned above.
  • FIG. 1 shows a schematic flow diagram of an array substrate manufacturing method according to an embodiment of the present disclosure
  • FIGS. 2-6 show sectional views of an array substrate obtained by steps of an array substrate manufacturing method according to an embodiment of the present disclosure.
  • FIG. 7 shows a structural schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • an array substrate manufacturing method comprises:
  • the opening region is formed by the photoresist 5 , thus a region in which the active layer 4 is formed may be defined, and then, the active layer 4 may be directly formed in the opening region; with respect to a process of firstly forming a semiconductor layer, and then etching the semiconductor layer to form the active layer, it is not necessary to etch a semiconductor material for forming the active layer, thereby avoiding damage to the active layer 4 and guaranteeing the good contact between the active layer 4 and the source and drain electrodes 2 and 3 , so that the source electrode 2 and the drain electrode 3 can be conducted very well when turned on, and the good performance of a thin film transistor is ensured.
  • the active layer 4 is formed on the source electrode 2 and the drain electrode 3 , even if treatment needs to be performed on the active layer 4 by a following process, only an upper surface of the active layer 4 can be influenced, a side of the active layer 4 in contact with the source electrode 2 and the drain electrode 3 is not influenced, which still can guarantee that the active layer 4 is in good contact with the source electrode 2 and the drain electrode 3 .
  • the forming the active layer 4 in the opening region includes: filling the semiconductor material in the opening region so as to form the active layer, for example, applying the semiconductor material in the opening region so as to form the active layer 4 .
  • a difference between a surface energy of the photoresist 5 and a surface energy of the gate insulating layer 1 is greater than a preset value.
  • the difference between the surface energy (i.e., surface tension) of the photoresist 5 and the surface energy of the gate insulating layer 1 may be relatively greater, for example, a the difference is up to 0.01 N/m, wherein the surface energy of the photoresist 5 is higher, and the surface energy of the gate insulating layer 1 is lower, while wettability of a semiconductor material solution with respect to a material with the lower surface energy is higher, and wettability of the semiconductor material solution with respect to a material with the higher surface energy is lower, and therefore when applied to the opening region, the semiconductor material solution is not easy to attach to the photoresist 5 , but easy to attach to the gate insulating layer 1 , so that the active layer 4 formed by the semiconductor material solution is defined in the opening region better.
  • the forming the active layer 4 in the opening region includes:
  • a length-width ratio of the opening region is 10:1 to 50:1.
  • the formed active layer 4 with the corresponding length-width ratio in the opening region with the length-width ratio of 10:1 to 50:1 may be well conducted under drive of the gate electrode 9 , and then, the source electrode 2 and the drain electrode 3 are conducted.
  • the semiconductor material solution is applied to the opening region by the solution processing method of ink-jet printing so as to form the active layer 4 , and a width of the opening region is 5 ⁇ m to 50 ⁇ m.
  • the semiconductor material solution may be applied into a narrower opening region by the ink-jet printing method, so that the width of the opening region may be set to be smaller to decrease a region occupied by the thin film transistor and increase an aperture ratio.
  • the semiconductor material solution is applied to the opening region by the solution processing method of silk-screen printing, blade coating or spin coating and the like so as to form the active layer, and the width of the opening region is 30 ⁇ m to 100 ⁇ m.
  • the opening region needs to be set to be wider.
  • the array substrate manufacturing method after applying the semiconductor material solution to the opening region by the solution processing method of blade coating and/or spin coating so as to form the active layer 4 , the array substrate manufacturing method according to an embodiment of the present disclosure further includes:
  • the active layer 4 may be directly formed in the opening region by the method of ink-jet printing and silk-screen printing, while a semiconductor layer is formed in the opening region and above the photoresist by the method of blade coating and spin coating, so that the semiconductor material outside the opening region needs to be removed, for example, the semiconductor material outside the opening region is removed by dry etching, wet etching or laser.
  • the active layer 4 formed by any above-mentioned method as the semiconductor material applied in the opening region covers the source electrode 2 and the drain electrode 3 , even if the semiconductor material is removed subsequently, only the upper surface of the active layer 4 may be influenced, a side of the active layer 4 in contact with the source electrode 2 and the drain electrode 3 may not be influenced, thereby ensuring that the active layer 4 is in good contact with the source electrode 2 and the drain electrode 3 .
  • the etching the photoresist 5 to form the channel region includes:etching the photoresist 5 by dry etching or wet etching.
  • Etching is performed by dry etching or wet etching so that etching depth may be accurately controlled, which avoids the phenomenon that the photoresist remains due to incomplete etching, or the gate insulating layer 1 is damaged by over etching.
  • the photoresist 5 is fluorinated photoresist.
  • the fluorinated photoresist has higher surface energy, which may ensure that surface energy difference between the fluorinated photoresist and the gate insulating layer 1 is relatively higher. Moreover, the fluorinated photoresist on the gate insulating layer 1 , the fluorinated photoresist on the source electrode 2 and the fluorinated photoresist on the drain electrode 3 are similar in film forming situation, so the active layer 4 with an even surface is easily formed.
  • the fluorinated photoresist is easily stripped completely so that a following process for removing the photoresist is facilitated, and the surface of the material after the photoresist is removed has no photoresist residues, for example, the photoresist of OSCoR 4001 or OSCoR 5001 may be selected.
  • the length-width ratio of the opening region is 10:1 to 50:1.
  • the formed active layer 4 with the corresponding length-width ratio in the opening region with the length-width ratio of 10:1 to 50:1 may be well conducted under drive of the gate electrode 9 , and then, the source electrode 2 and the drain electrode 3 are conducted.
  • the forming the active layer 4 in the opening region further includes:
  • Setting a structure parameter of the active layer 4 by controlling annealing time and annealing temperature of the active layer 4 .
  • the active layer 4 consistent with a target structure parameter may be formed.
  • the array substrate manufacturing method according to embodiment of the present disclosure further comprises:
  • the semiconductor material outside the opening region may be removed, and therefore a step of separately removing the semiconductor material outside the opening region may be omitted, which is not defined by the embodiment of the present disclosure.
  • a forming process adopted by the above-mentioned flows may include: a film forming process, such as, deposition and sputtering, and a patterning process, such as, etching.
  • an embodiment of the present disclosure further provides an array substrate, comprising:
  • a gate insulating layer 1 A gate insulating layer 1 ;
  • An active layer 4 formed on the gate insulating layer on which the source electrode and the drain electrode are formed, and covering a part of the source electrode 2 and a part of the drain electrode 3 and the gate insulating layer 1 between the source electrode 2 and the drain electrode 3 .
  • the length-width ratio of the active layer is 10:1 to 50:1.
  • the width of the active layer is 5 ⁇ m to 50 ⁇ m, or 30 ⁇ m to 100 ⁇ m.
  • the array substrate provided by the embodiment of the present disclosure further comprises:
  • a passivation layer 6 which is arranged on the active layer 4 , wherein a through hole is formed in the passivation layer 6 ;
  • a pixel electrode 7 which is arranged on the passivation layer 6 , and is electrically connected with the drain electrode 3 by the through hole.
  • the active layer 4 is in direct contact with a part of the source electrode 2 and a part of the drain electrode 3 and the gate insulating layer 1 between the source electrode 2 and the drain electrode 3 .
  • An embodiment of the present disclosure further provides a display panel, comprising any array substrate described above.
  • An embodiment of the present disclosure further provides a display device, comprising the display panel.
  • the display device may be any product or component with a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame and a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame and a navigator.
  • the source electrode and the drain electrode may be formed firstly, then, the opening region is formed in the photoresist, and then, the active layer is directly formed in the opening region; without etching the semiconductor material for forming the active layer, damage to the active layer is avoided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
US15/175,700 2015-07-22 2016-06-07 Array substrate and manufacturing method thereof, display panel and display device Active US10199406B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201510435044.1 2015-07-22
CN201510435044.1A CN105118835A (zh) 2015-07-22 2015-07-22 阵列基板及其制作方法、显示面板和显示装置
CN201510435044 2015-07-22

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US10199406B2 true US10199406B2 (en) 2019-02-05

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Publication number Priority date Publication date Assignee Title
CN106876277B (zh) * 2017-02-20 2020-03-17 武汉华星光电技术有限公司 薄膜晶体管的制备方法、显示面板的制备方法
CN108091700A (zh) * 2017-12-28 2018-05-29 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制造方法
CN109950415B (zh) * 2019-02-21 2021-07-27 纳晶科技股份有限公司 一种顶发射发光器件及其制备方法
CN110780492A (zh) * 2019-10-28 2020-02-11 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN112420740A (zh) * 2020-11-05 2021-02-26 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

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