US10008921B2 - Driving power generating circuit and a method for generating a driving power - Google Patents

Driving power generating circuit and a method for generating a driving power Download PDF

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US10008921B2
US10008921B2 US14/944,243 US201514944243A US10008921B2 US 10008921 B2 US10008921 B2 US 10008921B2 US 201514944243 A US201514944243 A US 201514944243A US 10008921 B2 US10008921 B2 US 10008921B2
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circuit
signal
sampling
control signal
driving power
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US20170070133A1 (en
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Chih-Ping Cheng
Pei-Ling Tseng
Szu-Chieh Liu
Sue-Chen Liao
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H05B33/0818—
    • H05B33/089—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/327—Means for protecting converters other than automatic disconnection against abnormal temperatures
    • H02M2001/327—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/18—Modifications for indicating state of switch
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/375—Switched mode power supply [SMPS] using buck topology
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/38—Switched mode power supply [SMPS] using boost topology
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/385—Switched mode power supply [SMPS] using flyback topology
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H05B45/56—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits involving measures to prevent abnormal temperature of the LEDs

Definitions

  • the disclosure relates to a driving power generating circuit and a method for generating a driving power.
  • an electronic apparatus often includes a driving power generating circuit for generating a driving power to drive a load of the electronic apparatus, and thereby the load is able to execute corresponding operative functions.
  • the driving power generating circuit may not function normally due to abnormal electrical conditions of the load. For instance, since light-emitting devices in an exemplary light-emitting apparatus may be an open circuit or a short circuit, the operating temperature of the driving power generating circuit may be excessively high, or the driving power generated by the driving power generating circuit is not configured to drive the load. Hence, as long as the load is on the abnormal electrical conditions, the overly high operating temperature may burn down the driving power generating circuit.
  • an additional voltage may be supplied to the driving power generating circuit, and the electrical conditions of the load may be detected by comparing variations in the voltage.
  • Said technique may, however, expand the chip area of the driving power generating circuit and increase the power consumption of the driving power generating circuit.
  • the disclosure provides a driving power generating circuit and a method for generating a driving power, whereby an electrical condition of a load may be detected to determine whether to generate the driving power or not.
  • the driving power generating circuit includes a signal generating circuit, a power converter circuit, and a sampling control circuit.
  • the signal generating circuit is configured to output a control signal according to a feedback signal and a lock signal.
  • the power converter circuit is electrically connected to the signal generating circuit.
  • the power converter circuit is configured to generate the driving power according to the control signal, so as to drive the load.
  • the sampling control circuit is electrically connected to the signal generating circuit.
  • the sampling control circuit is configured to sample the control signal and output the lock signal according to a sampling result.
  • One of the exemplary embodiments is directed to a method for generating a driving power to drive a load.
  • the method includes: outputting a control signal according to a feedback signal and a lock signal, sampling the control signal and outputting the lock signal according to a sampling result, and generating the driving power according to the control signal to drive the load.
  • the sampling control circuit is configured to sample the control signal and output the lock signal to the signal generating circuit or the processor circuit according to the sampling result.
  • FIG. 1 is schematic view of an electronic apparatus according to an exemplary embodiment.
  • FIG. 2 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 3 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 normally functions.
  • FIG. 4 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 is a short circuit.
  • FIG. 5 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 is an open circuit.
  • FIG. 6 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 7 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 normally functions.
  • FIG. 8 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 is a short circuit.
  • FIG. 9 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 is an open circuit.
  • FIG. 10 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 11 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 12 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 13 is schematic view of a sampling control circuit according to an exemplary embodiment.
  • FIG. 14 schematically illustrates waveforms of signals of a sampling control circuit while the sampling control circuit performs a sampling function according to an exemplary embodiment.
  • FIG. 15 is schematic view of a sampling control circuit according to another exemplary embodiment.
  • FIG. 16 is schematic view of a sampling control circuit according to another exemplary embodiment.
  • FIG. 17 is a flowchart of a method for generating a driving power according to an exemplary embodiment.
  • FIG. 18 is a flowchart of a method for generating a driving power according to an exemplary embodiment.
  • Couple in the description and claims may refer to any direct or indirect connection.
  • first apparatus if a first apparatus is coupled to a second apparatus, it means that the first apparatus may be directly connected to the second apparatus or may be indirectly connected to the second apparatus through another apparatus or by another connection means.
  • signal may stand for at least one current, voltage, electric charge, temperature, data, or any other signal or signals.
  • FIG. 1 is schematic view of an electronic apparatus according to an exemplary embodiment.
  • the electronic apparatus 100 includes a driving power generating circuit 110 and a load 120 .
  • the load 120 is electrically connected to the driving power generating circuit 110 .
  • the driving power generating circuit 110 is configured to generate a driving power S 1 , so as to drive the load 120 to perform corresponding operative functions.
  • the driving power generating circuit 110 may selectively decide whether to generate the driving power S 1 to drive the load 120 according to the electrical condition of the load 120 , e.g., whether the load 120 is an open circuit or a short circuit or functions normally.
  • a short circuit is an electrical circuit that allows a current to travel along an unintended path, often where essentially no (or a very low) electrical impedance is encountered.
  • the electrical opposite of a short circuit is an “open circuit”, which is an infinite resistance between two nodes.
  • the driving power generating circuit 110 includes a signal generating circuit 114 , a power converter circuit 116 , and a sampling control circuit 112 in the present exemplary embodiment.
  • the signal generating circuit 114 is configured to output a control signal S 3 to the power converter circuit 116 according to a feedback signal FB and a lock signal S 2 .
  • the feedback signal FB is a sensing signal generated by a current sensor which is located in the power converter circuit 116 and senses electric currents or an electrical signal provided by the load 120 , for instance, and the feedback signal GB is fed back to the signal generating circuit 114 .
  • the disclosure is not limited thereto.
  • the signal generating circuit 114 is, for instance, a pulse width modulating (PWM) circuit or another similar apparatus capable of generating a PWM signal as the control signal S 3 and outputting the control signal S 3 to the power converter circuit 116 , so as to control the conduction states of the switch in the power converter circuit 116 .
  • PWM pulse width modulating
  • the power converter circuit 116 described herein is electrically connected to the signal generating circuit 114 .
  • the power converter circuit 116 is configured to provide the feedback signal FB and generate the driving power S 1 according to the control signal S 3 , so as to drive the load 120 .
  • the power converter circuit 116 includes a buck converter, a boost converter, a flyback converter, or a combination thereof, for instance, which should however not be construed as a limitation to the disclosure.
  • the driving power S 1 may be a driving signal in form of electric current or voltage in response to the manner of designing the power converter circuit 116 or the load 120 , and the disclosure is not limited thereto.
  • the sampling control circuit 112 is electrically connected to the signal generating circuit 114 .
  • the sampling control circuit 112 is configured to sample the control signal S 3 , so as to determine the electrical condition of the load 120 , i.e., whether the load 120 is an open circuit or a short circuit or functions normally.
  • the sampling control circuit 112 then outputs the lock signal S 2 to the signal generating circuit 114 according to a sampling result S 4 , so as to control the signal generating circuit 114 to determine whether to output the control signal S 3 to the power converter circuit 116 .
  • the signal generating circuit 114 controls the power converter circuit 116 to stop operation according to the control signal S 3 , and thereby the power converter circuit 116 does not generate the driving power S 1 .
  • the lock signal S 2 acts as a warning signal, for instance, and the sampling control circuit 112 outputs the lock signal S 2 to a processor circuit to indicate whether the load 120 is an open circuit or a short circuit.
  • the driving power generating circuit 110 described herein may selectively decide whether to generate the driving power S 1 to drive the load 120 according to the electrical condition of the load 120 , e.g., whether the load 120 is an open circuit or a short circuit or functions normally. Thereby, the driving power generating circuit 110 which continuously functions when the load 120 is an open circuit or a short circuit can be prevented from being overheated or burned down.
  • the load 120 includes a display apparatus or a light-emitting apparatus, e.g., a light-emitting diode or an organic light-emitting diode, for instance; however, the disclosure is not limited thereto.
  • the load 120 exemplarily includes a display apparatus or a light-emitting apparatus, e.g., a light-emitting diode or an organic light-emitting diode; however, the type of the load 120 is not limited herein.
  • FIG. 2 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 3 to FIG. 5 schematically illustrate waveforms of signals of the driving power generating circuit while the load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 normally functions.
  • the electronic apparatus 200 includes a driving power generating circuit 210 and a load 220 .
  • the driving power generating circuit 210 includes a signal generating circuit 214 , a power converter circuit 216 , and a sampling control circuit 212 .
  • the load 220 is a string of light-emitting diodes for instance, and this should by no means restrict the scope of protection provided in the disclosure.
  • FIG. 3 schematically illustrates waveforms of signals of the driving power generating circuit while the load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 normally functions.
  • the power converter circuit 216 is configured to perform power conversion on the power voltage VP, so as to generate the driving power S 1 to drive the load 220 .
  • an inductor L, a diode D, and the load 220 constitute an electrical loop coupled between the power voltage VP and a switch SW.
  • a resistor R is coupled between the switch SW and the ground voltage GND.
  • the power voltage VP is converted into the driving power S 1 when the switch SW is switched on, so as to drive the load 220 ; besides, a portion of energy is stored in the inductor L.
  • the inductor L provides the driving power S 1 to the load 220 through the diode D.
  • the resistor R is coupled between the switch SW and the ground voltage GND.
  • the resistor R is, for instance, an electric current sensor for sensing the amount of the electric current of the driving power S 1 as the feedback signal FB, and the feedback signal FB is output to the signal generating circuit 214 .
  • the waveform of the feedback signal FB is shown in FIG. 3 .
  • the signal generating circuit 214 is configured to output the control signal S 3 according to the feedback signal FB and the lock signal S 2 , so as to determine whether the switch SW is switched on or off.
  • a comparator 710 is configured to receive the feedback signal FB and a reference signal VR and compares the levels of the two signals, so as to output the comparison result to determine whether to reset an SR flip-flop 720 or not.
  • a setting terminal S of the SR flip-flop 720 receives a clock signal CLK provided by a clock generator 730 , and the waveform of the clock signal CLK is shown in FIG. 3 .
  • the SR flip-flop 720 When the clock signal CLK is at the high level, the SR flip-flop 720 outputs the control signal at the high level through the output terminal Q. If the level of the feedback signal FB is higher than the level of the reference signal VR, the comparator 710 resets the SR flip-flop 720 , and the level of the control signal S 3 is reset from high to low. After that, when the clock signal CLK is again at the high level, the comparator 710 and the SR flip-flop 720 repeat said operations.
  • the control signal S 3 is output to the power converter circuit 216 through a logic circuit 740 and a buffer circuit 750 , so as to determine whether the switch SW is switched on or off.
  • control signal S 3 at the high level is configured to switch on the switch SW
  • control signal S 3 at the low level is configured to switch off the switch SW.
  • the correlation between the level of the control signal S 3 and the conduction state of the switch SW is determined by the type of the switch SW, for instance.
  • control signal S 3 at the low level may be configured to switch on the switch SW
  • control signal S 3 at the high level may be configured to switch off the switch SW, which should not be construed as limitations to the disclosure.
  • the sampling control circuit 212 is configured to sample the control signal S 3 at the output terminal Q of the SR flip-flop 720 , so as to determine the electrical condition of the load 220 , i.e., whether the load 220 is an open circuit or a short circuit or functions normally.
  • the sampling control circuit 212 provided herein includes a sampling circuit 810 and a control circuit 820 , for instance.
  • the sampling circuit 810 is electrically connected to the signal generating circuit 214 .
  • the control circuit 820 is electrically connected to the sampling detection circuit 810 .
  • the sampling circuit 810 is configured to sample the control signal S 3 according to the clock signal CLK and output the sampling result S 4 to the control circuit 820 .
  • the sampling result S 4 output by the sampling circuit 810 includes a pulse width of the control signal S 3 , for instance.
  • the sampling circuit 810 samples the control signal S 3 in the time sequence before and after the clock signal CLK at the high level.
  • the reference symbols VL and VH respectively represent the sampling result S 4 of the low-level control signal S 3 earlier obtained by the sampling circuit 810 and the high-level control signal S 3 later obtained by the sampling circuit 810 , for instance.
  • the sampling result S 4 indicates that the pulse width of the control signal S 3 is substantially equal to the predetermined width range, and the load 220 functions normally at this time.
  • the predetermined width range is determined according to actual circuit design demands or according to the clock signal CLK, for instance.
  • the predetermined width range provided in an exemplary embodiment may be equal to or slightly greater than the pulse width of the clock signal CLK by 2 nanoseconds (ns), which should not be construed as a limitation to the disclosure.
  • the control circuit 820 outputs the high-level or low-level lock signal S 2 .
  • the pulse width of the control signal S 3 is substantially equal to the predetermined width range according to the sampling result S 4 ; at this time, the load 220 functions normally, and the control circuit 820 outputs the high-level lock signal S 2 to the logic circuit 740 , for instance, such that the control signal S 3 passes through the logic circuit 740 and the buffer circuit 750 and is then output to the power converter circuit 216 to determine whether the switch SW is switched on or off.
  • the pulse width of the control signal S 3 may be greater than or less than the predetermined width range according to the sampling result S 4 . If the pulse width of the control signal S 3 is greater than the predetermined width range, it indicates that the load 220 is an open circuit. On the contrary, if the pulse width of the control signal S 3 is less than a predetermined width range, it indicates that the load 220 is a short circuit. That is, the sampling result S 4 of the sampling circuit 810 includes the information of whether the pulse width of the control signal S 3 is greater than, equal to, or less than the predetermined width range.
  • FIG. 4 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 is a short circuit.
  • the load 220 is a short circuit, for instance.
  • the high-level control signal S 3 switches on the switch SW
  • the waveform of the feedback signal FB is rapidly raised and goes beyond the level of the reference signal VR because the load 220 is a short circuit.
  • the SR flip-flop 720 is reset, and thereby the level of the control signal S 3 is dropped from high to low. Therefore, as shown in FIG.
  • the sampling circuit 810 samples the control signal S 3 in the time sequence before and after the clock signal CLK at the high level
  • the sampling result S 4 lies in that the earlier-obtained control signal S 3 and the later-obtained high-level control signal S 3 are both at the low level.
  • the pulse width of the control signal S 3 is less than the predetermined width range, which indicates that the load 220 is a short circuit.
  • the control circuit 820 then outputs the low-level lock signal S 2 to the logic circuit 740 , for instance, such that the logic circuit 740 masks and does not output the control signal S 3 , and that the switch SW is switched off.
  • the driving power generating circuit 210 that is continuously operated when the load 220 is a short circuit can be prevented from being overheated or burned down.
  • FIG. 5 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 2 is an open circuit.
  • the load 220 is an open circuit, for instance.
  • the sampling circuit 810 samples the control signal S 3 in the time sequence before and after the clock signal CLK at the high level
  • the sampling result S 4 lies in that the earlier-obtained control signal S 3 and the later-obtained high-level control signal S 3 are both at the high level.
  • the pulse width of the control signal S 3 is greater than the predetermined width range, which indicates that the load 220 is an open circuit.
  • the control circuit 820 then outputs the low-level lock signal S 2 to the logic circuit 740 , for instance, such that the logic circuit 740 masks and does not output the control signal S 3 , and that the switch SW is switched off.
  • the driving power generating circuit 210 that is continuously operated when the load 220 is an open circuit can be prevented from being overheated or burned down.
  • the control circuit 820 controls the logic circuit 740 to mask the control signal S 3 ; however, the disclosure is not limited thereto.
  • the control circuit 820 may also control the logic circuit 740 to mask the control signal S 3 if the number of times of the pulse width of the control signal being greater than or less than the predetermined width range is greater than or equal to a predetermined value according to the detection result of the sampling circuit 810 .
  • control circuit 820 may control the logic circuit 740 to mask the control signal S 3 .
  • FIG. 6 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • FIG. 7 to FIG. 9 schematically illustrate waveforms of signals of the driving power generating circuit while the load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 normally functions.
  • the electronic apparatus 300 described in the present embodiment is similar to the electronic apparatus 200 illustrated in FIG. 2 , while the main difference therebetween lies in the manner of designing the circuit structure inside the power converter circuit, for instance.
  • the inductor L, the light-emitting diode D, and the load 320 constitute an electrical loop coupled between the ground voltage GND and the switch SW.
  • the resistor R is coupled between the switch SW and the power voltage VP.
  • FIG. 7 schematically illustrates waveforms of signals of the driving power generating circuit while the load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 normally functions.
  • the comparator 710 is configured to compare the level of the feedback signal FB and the level of the reference signal VR. If the level of the feedback signal FB is lower than the level of the reference signal VR, the comparator 710 resets the SR flip-flop 720 , as shown in FIG. 7 .
  • FIG. 8 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 is a short circuit.
  • the load 320 is a short circuit, for instance.
  • the sampling circuit 810 when the sampling circuit 810 samples the control signal S 3 in the time sequence before and after the clock signal CLK at the high level, the sampling result S 4 lies in that the earlier-obtained control signal S 3 and the later-obtained high-level control signal S 3 are both at the low level.
  • the pulse width of the control signal S 3 is less than the predetermined width range, which indicates that the load 320 is a short circuit.
  • the control circuit 820 then outputs the low-level lock signal S 2 to the logic circuit 740 , for instance, such that the logic circuit 740 masks and does not output the control signal S 3 , and that the switch SW is switched off.
  • the driving power generating circuit 310 that is continuously operated when the load 320 is a short circuit can be prevented from being overheated or burned down.
  • FIG. 9 schematically illustrates waveforms of signals of a driving power generating circuit while a load of the driving power generating circuit provided in the exemplary embodiment as shown in FIG. 6 is an open circuit.
  • the load 320 is an open circuit, for instance.
  • the sampling circuit 810 samples the control signal S 3 in the time sequence before and after the clock signal CLK at the high level
  • the sampling result S 4 lies in that the earlier-obtained control signal S 3 and the later-obtained high-level control signal S 3 are both at the high level.
  • the pulse width of the control signal S 3 is greater than the predetermined width range, which indicates that the load 320 is an open circuit.
  • the control circuit 820 then outputs the low-level lock signal S 2 to the logic circuit 740 , for instance, such that the logic circuit 740 masks and does not output the control signal S 3 , and that the switch SW is switched off.
  • the driving power generating circuit 310 that is continuously operated when the load 320 is an open circuit can be prevented from being overheated or burned down.
  • FIG. 10 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • the electronic apparatus 400 described in the present embodiment is similar to the electronic apparatus 300 illustrated in FIG. 6 , while the main difference therebetween lies in the manner of designing the circuit structure inside the power converter circuit, for instance.
  • the inductor L, the light-emitting diode D, the capacitor C, and the load 420 constitute an electrical loop coupled between the ground voltage GND and the switch SW.
  • the voltage at a terminal of the load 420 acts as the feedback signal FB and is transmitted to the comparator 710 of the signal generating circuit 410 , so as to compare the levels of the signals.
  • the pulse width of the control signal S 3 if the pulse width of the control signal S 3 is less than the predetermined width range, it indicates that the load 420 is an open circuit. On the contrary, if the pulse width of the control signal S 3 is greater than the predetermined width range, it indicates that the load 420 is a short circuit. That is, as provided herein, the overly large or small pulse width of the control signal S 3 in comparison with to the predetermined width range represents different circuit abnormalities according to different manner of designing the circuit structure inside the power converter circuit 416 .
  • FIG. 11 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • the electronic apparatus 500 described in the present embodiment is similar to the electronic apparatus 100 illustrated in FIG. 1 , while the main difference therebetween lies in that the driving power generating circuit 510 outputs the lock signal S 2 as a warning signal to the processor circuit 530 , so as to indicate whether the load 520 is an open circuit or a short circuit, for instance.
  • the sampling control circuit 512 is configured to sample the control signal S 3 , so as to determine the electrical condition of the load 520 , i.e., whether the load 520 is an open circuit or a short circuit or functions normally.
  • the sampling control circuit 512 then outputs the lock signal S 2 to the processor circuit 530 according to the sampling result S 4 , and the lock signal S 2 acts as a warning signal to indicate whether the load 520 is an open circuit or a short circuit.
  • the processor circuit 530 may determine whether the load 520 is an open circuit/a short circuit or not, so as to process the driving power generating circuit 510 through stopping its operation and preventing the driving power generating circuit 510 from being overheated or burned down, for instance.
  • the processor circuit 530 may be an external processor outside the electronic apparatus 500 or an internal processor installed in the electronic apparatus 500 .
  • the processor circuit 530 provided herein includes, for instance, a central processing unit (CPU), any other general or specific programmable microprocessor, any other digital signal processor (DSP), any other programmable controller, any other application specific integrated circuit (ASIC), any other programmable logic device (PLD), any other similar device, or a combination thereof, which should not be construed as limitations to the disclosure.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • PLD programmable logic device
  • FIG. 12 is schematic view of an electronic apparatus according to another exemplary embodiment.
  • the electronic apparatus 600 described in the present embodiment is similar to the electronic apparatus 200 illustrated in FIG. 12 , while the main difference therebetween lies in that the driving power generating circuit 610 outputs the lock signal S 2 as a warning signal to the processor circuit 630 , so as to indicate whether the load 620 is an open circuit or a short circuit, for instance.
  • the sampling circuit 810 is configured to sample the control signal S 3 output by the buffer circuit 750 , so as to determine the electrical condition of the load 620 , i.e., whether the load 620 is an open circuit or a short circuit or functions normally.
  • the control circuit 820 then outputs the lock signal S 2 to the processor circuit 630 according to the sampling result S 4 , and the lock signal S 2 acts as a warning signal to indicate whether the load 620 is an open circuit or a short circuit.
  • the processor circuit 630 may determine whether the load 620 is an open circuit/a short circuit or not, so as to process the driving power generating circuit 610 through stopping its operation and preventing the driving power generating circuit 610 from being overheated or burned down, for instance.
  • the sampling circuit 810 samples the control signal S 3 output by the buffer circuit 750 , for instance, which should however not be construed as a limitation to the disclosure.
  • the sampling circuit 810 may also sample the control signal S 3 output by the SR flip-flop 720 .
  • FIG. 13 is schematic view of a sampling control circuit according to an exemplary embodiment.
  • FIG. 14 schematically illustrates waveforms of signals of a sampling control circuit while the sampling control circuit performs a sampling function according to an exemplary embodiment.
  • the sampling control circuit 212 A provided herein includes a sampling circuit 810 and a control circuit 820 , for instance.
  • the sampling circuit 810 is configured to sample the control signal S 3 and determine whether the pulse width of the control signal S 3 is less than the predetermined width range according to the sampling result S 4 , for instance. If the pulse width of the control signal S 3 is less than the predetermined width range, it indicates that the load 20 is a short circuit.
  • the control circuit 820 then counts the number of times of the pulse width of the control signal S 3 being less than the predetermined width range and determines whether the number of times is greater than or equal to a predetermined value. If the number of times is greater than or equal to the predetermined value, the control circuit 820 outputs the lock signal S 2 to the signal generating circuit 216 to control the power converter circuit 216 to stop its operation or outputs the lock signal S 2 to the processor circuit to indicate that the load 220 is a short circuit.
  • the sampling circuit 810 includes a first sampling channel 812 A, a second sampling channel 812 B, and a first logic circuit 814 .
  • the first sampling channel 812 A and the second sampling channel 812 B are electrically connected to the signal generating circuit 214 .
  • the first logic circuit 814 is electrically connected to the first sampling channel 812 A and the second sampling channel 812 B.
  • the first sampling channel 812 A is configured to sample the control signal S 3 according to a first sampling reference signal A and a second sampling reference signal B, so as to output a first sampling signal SA to the first logic circuit 814 .
  • the second sampling channel 812 B is configured to sample the control signal S 3 according to the second sampling reference signal B, so as to output a second sampling signal SB to the first logic circuit 814 .
  • the first logic circuit 814 is configured to output the sampling result S 4 to the control circuit 820 according to the first sampling signal SA and the second sampling signal SB.
  • the first logic circuit 814 includes an NOR gate for performing logic computation on the first sampling signal SA and the second sampling signal SB, for instance, which should however not be construed as a limitation to the disclosure.
  • the first sampling reference signal A and the second sampling reference signal B are determined according to the clock signal CLK, for instance.
  • a rising edge of the first sampling reference signal A is slightly ahead of a rising edge of the clock signal CLK in terms of timing sequence, for instance.
  • the second sampling reference signal B may be obtained after inverting the clock signal CLK, and the rising edge of the clock signal CLK slightly falls behind the falling edge of the clock signal CLK in terms of timing sequence, for instance.
  • the first sampling channel 812 A and the second sampling channel 812 B respectively sample the control signal S 3 at the rising edge of the first sampling reference signal A and the rising edge of the second sampling reference signal B, as shown in FIG.
  • the reference symbols VL and VH respectively represent the sampling result S 4 of the low-level control signal S 3 earlier-obtained by the sampling circuit 810 and the high-level control signal S 3 later obtained by the sampling circuit 810 , for instance.
  • the pulse width of the control signal S 3 is substantially equal to the predetermined width range.
  • the load 220 functions normally, and the first logic circuit 814 outputs the sampling result S 4 with the first logic value (e.g., 1) to the control circuit 820 , for instance.
  • the sampling result S 4 of the first and second sampling channels 812 A and 812 B is as shown in FIG. 4 or FIG.
  • the first logic circuit 814 outputs the sampling result S 4 with the second logic value (e.g., 0) to the control circuit 820 , for instance.
  • the control circuit 820 includes a counter circuit 822 , a second logic circuit 824 , and a third logic circuit 826 .
  • the counter circuit 822 is electrically connected to the sampling circuit 810 .
  • the second logic circuit 824 and the third logic circuit 826 are electrically connected to the counter circuit 822 , respectively.
  • the third logic circuit 826 is configured to provide a counter reference signal CLK_C.
  • the counter circuit 822 counts the number of times of the pulse width of the control signal S 3 being less than the predetermined width range according to the counter reference signal CLK_C.
  • the second logic circuit 824 determines whether the number of times of the pulse width of the control signal S 3 being less than the predetermined width range is greater than or equal to a predetermined value. If the number of times of the pulse width of the control signal S 3 being less than the predetermined width range is greater than or equal to the predetermined value, the second logic circuit 824 outputs the lock signal S 2 to the signal generating circuit 216 or the processor circuit 530 .
  • the counter circuit 822 includes three counters composed of three shift registers, while the number and the type of the counters do not serve to limit the scope of protection provided in the disclosure.
  • the second logic circuit 824 outputs the lock signal S 2 to the signal generating circuit 216 or the processor circuit 530 .
  • the predetermined value provided herein is determined by the number of the counters (i.e., the shift registers).
  • the third logic circuit 824 provides the count reference signal CLK_C according to the clock signal CLK and the lock signal S 2 , such that the counter circuit 822 can count the number of times of the pulse width of the control signal S 3 being less than the predetermined width range.
  • the disclosure is not limited thereto.
  • the third logic circuit 826 may determine whether to provide the count reference signal CLK_C to the counter circuit 822 according to an over temperature protection (OTP) signal CLK or a PWM signal.
  • OTP over temperature protection
  • the electronic apparatus 200 depicted in FIG. 2 is taken for example, but the disclosure is not limited thereto.
  • the operation of the sampling circuit 810 and the operation of the control circuit 820 are applicable to other electronic apparatuses according to other exemplary embodiments.
  • the circuit structures of the sampling circuit 810 and the control circuit 820 provided herein are exemplary and should not be construed as limitations to the disclosure.
  • FIG. 15 is schematic view of a sampling control circuit according to another exemplary embodiment.
  • the sampling control circuit 212 B provided in the present exemplary embodiment is similar to the sampling control circuit 212 A depicted in FIG. 13 , whereas the main difference therebetween lies in the fact that the sampling control circuit 212 B determines whether the pulse width of the control signal S 3 is greater than the predetermined width range according to the sampling result S 4 , for instance. If the pulse width of the control signal S 3 is greater than the predetermined width range, it indicates that the load 20 is an open circuit.
  • the sampling control circuit 212 B includes a sampling circuit 910 and a control circuit 820 , for instance.
  • the sampling circuit 910 is configured to sample the control signal S 3 and determine whether the pulse width of the control signal S 3 is greater than the predetermined width range according to the sampling result S 4 , for instance. If the pulse width of the control signal S 3 is greater than the predetermined width range, it indicates that the load 20 is an open circuit.
  • the control circuit 820 then counts the number of times of the pulse width of the control signal S 3 being greater than the predetermined width range and determines whether the number of times is greater than or equal to a predetermined value.
  • control circuit 820 If the number of times is greater than or equal to the predetermined value, the control circuit 820 outputs the lock signal S 2 to the signal generating circuit 216 to control the power converter circuit 216 to stop its operation or outputs the lock signal S 2 to the processor circuit to indicate that the load 220 is an open circuit.
  • the first logic circuit 914 outputs the sampling result S 4 to the control circuit 820 according to the first sampling signal SA and the second sampling signal SB.
  • the first logic circuit 914 includes an NAND gate for performing logic computation on the first sampling signal SA and the second sampling signal SB, for instance, which should however not be construed as a limitation to the disclosure.
  • the first logic circuit 914 outputs the sampling result S 4 with the first logic value (e.g., 1) to the control circuit 820 , for instance.
  • the first logic value e.g., 1
  • the sampling result S 4 of the first and second sampling channels 812 A and 812 B is as shown in FIG. 5 or FIG.
  • the first logic circuit 914 outputs the sampling result S 4 with the second logic value (e.g., 0) to the control circuit 820 , for instance.
  • the counter circuit 822 counts the number of times of the pulse width of the control signal S 3 being greater than the predetermined width range according to the counter reference signal CLK_C.
  • the second logic circuit 824 determines whether the number of times of the pulse width of the control signal S 3 being greater than the predetermined width range is greater than or equal to a predetermined value. If the number of times of the pulse width of the control signal S 3 being greater than the predetermined width range is greater than or equal to the predetermined value, the second logic circuit 824 outputs the lock signal S 2 to the signal generating circuit 216 or the processor circuit 530 .
  • the electronic apparatus 200 depicted in FIG. 2 is taken for example, but the disclosure is not limited thereto.
  • the operation of the sampling circuit 910 and the operation of the control circuit 820 are also applicable to other electronic apparatuses according to other exemplary embodiments.
  • the circuit structures of the sampling circuit 910 and the control circuit 820 provided herein are exemplary and should not be construed as limitations to the disclosure.
  • FIG. 16 is schematic view of a sampling control circuit according to another exemplary embodiment.
  • the sampling control circuit 212 C provided in the present exemplary embodiment is similar to the sampling control circuit 212 A depicted in FIG. 13 , whereas the main difference therebetween lies in the fact that the sampling control circuit 212 C determines whether the pulse width of the control signal S 3 is greater than or less than the predetermined width range according to the sampling result S 4 , for instance. If the pulse width of the control signal S 3 is greater than or less than the predetermined width range, it indicates that the load 20 is an open circuit or a short circuit.
  • the sampling control circuit 212 C includes a sampling circuit 1010 and a control circuit 820 , for instance.
  • the sampling circuit 1010 is configured to sample the control signal S 3 and determine whether the pulse width of the control signal S 3 is greater than or less than the predetermined width range according to the sampling result S 4 , for instance. If the pulse width of the control signal S 3 is greater than or less than the predetermined width range, it indicates that the load 20 is an open circuit or a short circuit.
  • the control circuit 820 then counts the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range and determines whether the number of times is greater than or equal to a predetermined value.
  • control circuit 820 If the number of times is greater than or equal to the predetermined value, the control circuit 820 outputs the lock signal S 2 to the signal generating circuit 216 to control the power converter circuit 216 to stop its operation or outputs the lock signal S 2 to the processor circuit to indicate that the load 220 is a short circuit or an open circuit.
  • the first logic circuit 1014 outputs the sampling result S 4 to the control circuit 820 according to the first sampling signal SA and the second sampling signal SB.
  • the first logic circuit 1014 includes an inverter and an AND gate for performing logic computation on the first sampling signal SA and the second sampling signal SB, for instance, which should however not be construed as a limitation to the disclosure.
  • the first logic circuit 1014 outputs the sampling result S 4 with the first logic value (e.g., 1) to the control circuit 820 , for instance.
  • the first logic value e.g. 1, 1
  • the first logic circuit 814 outputs the sampling result S 4 with the second logic value (e.g., 0) to the control circuit 820 , for instance.
  • the counter circuit 822 counts the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range according to the counter reference signal CLK_C.
  • the second logic circuit 824 determines whether the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range is greater than or equal to a predetermined value. If the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range is greater than or equal to the predetermined value, the second logic circuit 824 outputs the lock signal S 2 to the signal generating circuit 216 or the processor circuit 530 .
  • the electronic apparatus 200 depicted in FIG. 2 is taken for example, but the disclosure is not restricted here.
  • the operation of the sampling circuit 1010 and the operation of the control circuit 820 are also applicable to other electronic apparatuses according to other exemplary embodiments.
  • the circuit structures of the sampling circuit 1010 and the control circuit 820 provided herein are exemplary and should not be construed as limitations to the disclosure.
  • FIG. 17 is a flowchart of a method for generating a driving power according to an exemplary embodiment.
  • the method for generating a driving power as provided herein is at least applicable to the driving power generating circuit 100 depicted in FIG. 1 or the driving power generating circuit 500 depicted in FIG. 11 , for instance.
  • the driving power generating circuit 100 depicted in FIG. 1 is taken for instance; in step S 100 , the driving power generating circuit 100 outputs the control signal S 3 to the power converter circuit 116 according to the feedback signal FB and the lock signal S 2 .
  • step S 110 the sampling control circuit 112 of the driving power generating circuit 100 is configured to sample the control signal S 3 and output the lock signal S 2 to the signal generating circuit 114 according to the sampling result S 4 .
  • step S 120 the power converter circuit 116 of the driving power generating circuit 100 is configured to generate the driving power S 1 according to the control signal S 3 to drive the load 120 .
  • the driving power generating circuit 100 again outputs the control signal S 3 to the power converter circuit 116 according to the feedback signal FB and the lock signal S 2 , so as to continuously perform the method of generating the driving power as provided in the present exemplary embodiment.
  • FIG. 18 is a flowchart of a method for generating a driving power according to an exemplary embodiment.
  • the method for generating a driving power as provided herein is at least applicable to the driving power generating circuit 100 depicted in FIG. 1 , for instance.
  • the driving power generating circuit 100 depicted in FIG. 1 is taken for example; in step S 200 , the driving power generating circuit 100 outputs the control signal S 3 to the power converter circuit 116 according to the feedback signal FB and the lock signal S 2 .
  • the sampling control circuit 112 of the driving power generating circuit 100 is configured to sample the control signal S 3 .
  • the sampling control circuit 112 of the driving power generating circuit 100 is configured to determine whether the pulse width of the control signal S 3 is greater than or less than the predetermined width range according to the sampling result S 4 .
  • the power converter circuit 116 of the driving power generating circuit 100 is configured to generate the driving power S 1 according to the control signal S 3 in step S 230 to drive the load 120 .
  • the driving power generating circuit 100 again outputs the control signal S 3 to the power converter circuit 116 according to the feedback signal FB and the lock signal S 2 , so as to continuously perform the method of generating the driving power as provided in the present exemplary embodiment.
  • the sampling control circuit 112 of the driving power generating circuit 100 is configured to determine whether the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range is greater than or equal to a predetermined value in step S 240 .
  • the power converter circuit 116 of the driving power generating circuit 100 is configured to generate the driving power S 1 according to the control signal S 3 in step S 230 to drive the load 120 .
  • the driving power generating circuit 100 again outputs the control signal S 3 to the power converter circuit 116 according to the feedback signal FB and the lock signal S 2 , so as to continuously perform the method of generating the driving power as provided in the present exemplary embodiment.
  • the sampling control circuit 112 of the driving power generating circuit 100 is configured to output the lock signal S 2 to the signal generating circuit 114 and thereby control the signal generating circuit 114 to stop outputting the control signal S 3 to the power converter circuit 116 in step S 250 .
  • the driving power generating circuit 110 that is continuously operated when the load 120 is an open circuit or a short circuit can be prevented from being overheated or burned down.
  • the sampling control circuit 112 determines whether the pulse width of the control signal S 3 is greater than or less than the predetermined width range; in step S 240 , the sampling control circuit 112 determines whether the number of times of the pulse width of the control signal S 3 being greater than or less than the predetermined width range is greater than or equal to the predetermined value.
  • the sampling control circuit 112 may determine whether the pulse width of the control signal S 3 is less than the predetermined width range and determine whether the number of times of the pulse width of the control signal S 3 being less than the predetermined width range is greater than or equal to the predetermined value.
  • the sampling control circuit 112 may determine whether the pulse width of the control signal S 3 is greater than the predetermined width range and determine whether the number of times of the pulse width of the control signal S 3 being greater than the predetermined width range is greater than or equal to the predetermined value.
  • step S 250 the sampling control circuit 112 outputs the lock signal S 2 to the signal generating circuit 114 , so as to control the signal generating circuit 114 to stop outputting the control signal S 3 to the power converter circuit 116 ; however, the disclosure is not limited thereto.
  • the lock signal S 2 may act as a warning signal, for instance, and the sampling control circuit 112 outputs the lock signal S 2 to a processor circuit to indicate whether the load is an open circuit or a short circuit.
  • the sampling control circuit is configured to sample the control signal, and the sampling result includes the information of the pulse width of the control signal.
  • the sampling control circuit determines whether the load functions normally, is an open circuit, or is a short circuit according to the sampling result, so as to output the lock signal to the signal generating circuit or the processor circuit.
  • the driving power generating circuit that is continuously operated when the load is an open circuit or a short circuit can be prevented from being overheated or burned down.

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CN106505838A (zh) 2017-03-15
US20170070133A1 (en) 2017-03-09

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