UA71411U - Opto-immitance logic element or - Google Patents

Opto-immitance logic element or

Info

Publication number
UA71411U
UA71411U UAU201200212U UAU201200212U UA71411U UA 71411 U UA71411 U UA 71411U UA U201200212 U UAU201200212 U UA U201200212U UA U201200212 U UAU201200212 U UA U201200212U UA 71411 U UA71411 U UA 71411U
Authority
UA
Ukraine
Prior art keywords
output
bipolar transistor
immitance
opto
global bus
Prior art date
Application number
UAU201200212U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Людмила Брониславовна Лищинская
Светлана Евгеньевна Фурса
Александр Александрович Лазарев
Николай Антонович Филинюк
Original Assignee
Винницкий Национальный Технический Университет
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Винницкий Национальный Технический Университет filed Critical Винницкий Национальный Технический Университет
Priority to UAU201200212U priority Critical patent/UA71411U/en
Publication of UA71411U publication Critical patent/UA71411U/en

Links

Landscapes

  • Direct Current Feeding And Distribution (AREA)
  • Logic Circuits (AREA)

Abstract

An opto-immitance logic element “OR” comprises a limiting resistor, a global bus, a power distribution bus, an output terminal, a bipolar transistor, three photoresistors, a balancing capacitor. The bipolar transistor collector is connected to the global bus; an emitter is connected to the first terminal of limiting resistor, the second output of which is connected to the power distribution bus. Between the collector of bipolar transistor and first output of limiting resistor the first output of balancing capacitor is connected, which second output is connected to the output terminal. Three photoresistors are in parallel connected to the bipolar transistor base. The second output of the first photoresistor is connected to the global bus. The second output of second photoresistor is also connected to the global bus. The second output of the third photoresistor is connected to the global bus.
UAU201200212U 2012-01-06 2012-01-06 Opto-immitance logic element or UA71411U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201200212U UA71411U (en) 2012-01-06 2012-01-06 Opto-immitance logic element or

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201200212U UA71411U (en) 2012-01-06 2012-01-06 Opto-immitance logic element or

Publications (1)

Publication Number Publication Date
UA71411U true UA71411U (en) 2012-07-10

Family

ID=50848443

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201200212U UA71411U (en) 2012-01-06 2012-01-06 Opto-immitance logic element or

Country Status (1)

Country Link
UA (1) UA71411U (en)

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