UA90280U - Current reflector - Google Patents

Current reflector

Info

Publication number
UA90280U
UA90280U UAU201309914U UAU201309914U UA90280U UA 90280 U UA90280 U UA 90280U UA U201309914 U UAU201309914 U UA U201309914U UA U201309914 U UAU201309914 U UA U201309914U UA 90280 U UA90280 U UA 90280U
Authority
UA
Ukraine
Prior art keywords
transistor
collector
emitter
base
terminal
Prior art date
Application number
UAU201309914U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Олексій Дмитрович Азаров
Сергій Володимирович Павлов
Сергій Віталійович Богомолов
Сергій Ігорович Павлович
Original Assignee
Вінницький Національний Технічний Університет
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Вінницький Національний Технічний Університет filed Critical Вінницький Національний Технічний Університет
Priority to UAU201309914U priority Critical patent/UA90280U/en
Publication of UA90280U publication Critical patent/UA90280U/en

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Abstract

A current reflector comprises four transistors, a zero bus, input and output buses, with input bus being connected to a collector and base of first transistor, also to the base of second transistor; the emitter of first transistor is connected to the collector and base of third transistor, and to the base of fourth transistor, the emitter of second transistor is connected to the collector of fourth transistor. The emitter of third and fourth transistors are connected to the zero bus, the second transistor collector is connected to the output bus. Three transistors and four current sources are introduced, the emitter of fifth transistor is united with the collector of second transistor and connected to the united collector of sixth transistor and first terminal of third current source, the base of fifth transistor and emitter of sixth transistor are connected to the second terminal of second current source, the bases of sixth and seventh transistors are united and connected to the collector of seventh transistor and to second terminal of fourth current source, the emitter of seventh transistor is connected to the collector and base of eighth transistor, the collector of fifth transistor is connected to the output bus, the first terminal of first current source, first terminal of second and fourth current source are connected to the zero bus.
UAU201309914U 2013-08-09 2013-08-09 Current reflector UA90280U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201309914U UA90280U (en) 2013-08-09 2013-08-09 Current reflector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201309914U UA90280U (en) 2013-08-09 2013-08-09 Current reflector

Publications (1)

Publication Number Publication Date
UA90280U true UA90280U (en) 2014-05-26

Family

ID=56268039

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201309914U UA90280U (en) 2013-08-09 2013-08-09 Current reflector

Country Status (1)

Country Link
UA (1) UA90280U (en)

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