UA117741U - PROGRAMMER OF IMPULSE PULSE SEQUENCE WITH PROGRAMMED DURATION - Google Patents
PROGRAMMER OF IMPULSE PULSE SEQUENCE WITH PROGRAMMED DURATIONInfo
- Publication number
- UA117741U UA117741U UAU201613584U UAU201613584U UA117741U UA 117741 U UA117741 U UA 117741U UA U201613584 U UAU201613584 U UA U201613584U UA U201613584 U UAU201613584 U UA U201613584U UA 117741 U UA117741 U UA 117741U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- output
- counter
- zero
- asynchronous
- Prior art date
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Формувач послідовності імпульсів типу меандр з програмованою тривалістю містить два двійкових лічильники, вхід дозволу паралельного завантаження і входи подачі даних при завантаженні, вхід дозволу режиму лічби, вхід асинхронної установки у нульовий стан, вихід переповнювання; два елементи АБО; ланцюжок, що складається з послідовно з'єднаних резистора і конденсатора, підключеного до джерела живлення; стартостопний пристрій, який містить синхронний D-тригер зі входом асинхронної установки у нульовий стан, перший і другий двовходові елементи І. Другий лічильник виконаний однорозрядним (JK-тригер зі входом асинхронної установки у нульовий стан). Виходи другого, третього і четвертого розрядів першого лічильника з'єднано зі входами другого елемента АБО, вихід якого з'єднано зі входом дозволу переходу другого лічильника (входами J і K JK-тригера) і входом дозволу синхронного паралельного завантаження першого лічильника. Вихід JK-тригера, який утворює вихід формувача, з'єднано з другим входом першого елемента АБО. Тактовий вхід JK-тригера з’єднано зі входом формувача. Вхід асинхронної установки JK-тригера у нульовий стан з'єднано з виходом другого елемента І.A programmable pulse waveform generator with programmable duration comprises two binary counters, a parallel boot resolution input and a data input at boot, a digital mode resolution input, an asynchronous zero input, an overflow output; two elements OR; a circuit consisting of a series-connected resistor and a capacitor connected to a power source; a starter device comprising a synchronous D-flip-flop with zero input asynchronous setting, first and second two-input elements I. The second counter is made single-digit (JK flip-flop with asynchronous zero input input). The outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second element OR, the output of which is connected to the input of the transition of the second counter (inputs J and K JK trigger) and the input of the synchronous parallel load of the first counter. The output of the JK trigger, which forms the output of the shaper, is connected to the second input of the first element OR. The clock input of the JK trigger is connected to the input of the shaper. The input of the asynchronous setting of the JK flip-flop to zero is connected to the output of the second element I.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201613584U UA117741U (en) | 2017-02-16 | 2017-02-16 | PROGRAMMER OF IMPULSE PULSE SEQUENCE WITH PROGRAMMED DURATION |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201613584U UA117741U (en) | 2017-02-16 | 2017-02-16 | PROGRAMMER OF IMPULSE PULSE SEQUENCE WITH PROGRAMMED DURATION |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UA117741U true UA117741U (en) | 2017-07-10 |
Family
ID=59266277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| UAU201613584U UA117741U (en) | 2017-02-16 | 2017-02-16 | PROGRAMMER OF IMPULSE PULSE SEQUENCE WITH PROGRAMMED DURATION |
Country Status (1)
| Country | Link |
|---|---|
| UA (1) | UA117741U (en) |
-
2017
- 2017-02-16 UA UAU201613584U patent/UA117741U/en unknown
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