UA117703U - PULSE SEQUENCE SHAPTER WITH PROGRAMMED PARAMETERS - Google Patents
PULSE SEQUENCE SHAPTER WITH PROGRAMMED PARAMETERSInfo
- Publication number
- UA117703U UA117703U UAU201612600U UAU201612600U UA117703U UA 117703 U UA117703 U UA 117703U UA U201612600 U UAU201612600 U UA U201612600U UA U201612600 U UAU201612600 U UA U201612600U UA 117703 U UA117703 U UA 117703U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- pulse sequence
- shapter
- digits
- outputs
- Prior art date
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Формувач послідовності імпульсів з програмованими параметрами містить: синхронний D-тригер зі входом асинхронної установки у нульовий стан; два чотирирозрядні двійкові лічильники, перший із яких реверсивний, налагоджений на режим віднімання, що має вхід подачі тактових імпульсів, вхід дозволу режиму лічби, вхід асинхронної установки у нульовий стан, виходи першого, другого, третього і четвертого розрядів, вихід переповнювання, вхід дозволу режиму синхронного паралельного завантаження і входи завантаження; інвертор; перший, другий і третій елементи АБО; перший, другий і третій двох входові елементи І; ланцюжок, що складається з послідовно з'єднаних резистора і конденсатора. При цьому, введено: третій тривходовий елемент АБО; перший і другий цифрові компаратори, другий лічильник виконаний підсумовуючим, що має тактовий вхід, вхід дозволу режиму лічби, вхід асинхронної установки у нульовий стан, виходи першого, другого, третього і четвертого розрядів.The programmable pulse sequence shaper includes: a synchronous D-trigger with an asynchronous zero input; two four-digit binary counters, the first of which is reversible, tuned to the subtraction mode, which has an input of clock pulses, the input of the digital mode resolution, the input of the asynchronous zero setting, the outputs of the first, second, third and fourth digits, the output of overflow synchronous parallel download and download inputs; inverter; the first, second and third elements OR; the first, second and third two input elements I; a circuit consisting of a series-connected resistor and a capacitor. In this case, the following is introduced: the third three-way element OR; the first and second digital comparators, the second counter is made by the summator having clock input, digital mode resolution input, asynchronous zero input input, outputs of first, second, third and fourth digits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201612600U UA117703U (en) | 2016-12-09 | 2016-12-09 | PULSE SEQUENCE SHAPTER WITH PROGRAMMED PARAMETERS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201612600U UA117703U (en) | 2016-12-09 | 2016-12-09 | PULSE SEQUENCE SHAPTER WITH PROGRAMMED PARAMETERS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UA117703U true UA117703U (en) | 2017-07-10 |
Family
ID=59266195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| UAU201612600U UA117703U (en) | 2016-12-09 | 2016-12-09 | PULSE SEQUENCE SHAPTER WITH PROGRAMMED PARAMETERS |
Country Status (1)
| Country | Link |
|---|---|
| UA (1) | UA117703U (en) |
-
2016
- 2016-12-09 UA UAU201612600U patent/UA117703U/en unknown
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