UA114373U - FORMER OF THE PERIODIC IMPULSION SEQUENCE WITH PROGRAMMABLE DURATION, SHARPING, AND DELAY OF STARTING FORMATION AFTER STARTING - Google Patents
FORMER OF THE PERIODIC IMPULSION SEQUENCE WITH PROGRAMMABLE DURATION, SHARPING, AND DELAY OF STARTING FORMATION AFTER STARTINGInfo
- Publication number
- UA114373U UA114373U UAU201608600U UAU201608600U UA114373U UA 114373 U UA114373 U UA 114373U UA U201608600 U UAU201608600 U UA U201608600U UA U201608600 U UAU201608600 U UA U201608600U UA 114373 U UA114373 U UA 114373U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- starting
- elements
- asynchronous
- periodic
- Prior art date
Links
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- Dc-Dc Converters (AREA)
Abstract
Формувач періодичної послідовності імпульсів з програмованою тривалістю, шпаруватістю і затримкою початку формування відносно стартового імпульсу містить: синхронний D-тригер зі входом асинхронної установки у нульовий стан; перший і другий реверсивні двійкові лічильники, налагоджені на режим віднімання, що мають вхід подачі тактових імпульсів, вхід дозволу режиму лічби, вхід асинхронної установки у нульовий стан, вихід переповнювання, вхід дозволу режиму синхронного паралельного завантаження і входи завантаження; інвертор; перший і другий елемента АБО; перший і другий двовходові елементи І; ланцюжок, що складається з послідовно з'єднаних резистора і конденсатора. Додатково в нього введено: підсумувальний лічильник зі входом дозволу режиму лічби, входом асинхронної установки у нульовий стан, тактовим входом; компаратор зі входом дозволу сигналу на виході; третій, четвертий і п'ятий елементи АБО; елемент АБО-НІ.The periodic pulse shaper with programmable duration, duty cycle and delayed start of the formation relative to the starting pulse contains: a synchronous D-trigger with the input of the asynchronous installation in the zero state; the first and second reversible binary counters configured for subtraction having a clock pulse input, digital mode resolution input, asynchronous zero input, overflow output, synchronous parallel boot mode input and load inputs; inverter; the first and second elements OR; the first and second two-port elements I; a circuit consisting of a series-connected resistor and a capacitor. In addition, it includes: a summation counter with the input of the digital mode resolution, the input of the asynchronous setting to the zero state, the clock input; comparator with input signal resolution output; the third, fourth and fifth elements OR; element OR NOT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201608600U UA114373U (en) | 2016-08-05 | 2016-08-05 | FORMER OF THE PERIODIC IMPULSION SEQUENCE WITH PROGRAMMABLE DURATION, SHARPING, AND DELAY OF STARTING FORMATION AFTER STARTING |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| UAU201608600U UA114373U (en) | 2016-08-05 | 2016-08-05 | FORMER OF THE PERIODIC IMPULSION SEQUENCE WITH PROGRAMMABLE DURATION, SHARPING, AND DELAY OF STARTING FORMATION AFTER STARTING |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UA114373U true UA114373U (en) | 2017-03-10 |
Family
ID=58504248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| UAU201608600U UA114373U (en) | 2016-08-05 | 2016-08-05 | FORMER OF THE PERIODIC IMPULSION SEQUENCE WITH PROGRAMMABLE DURATION, SHARPING, AND DELAY OF STARTING FORMATION AFTER STARTING |
Country Status (1)
| Country | Link |
|---|---|
| UA (1) | UA114373U (en) |
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2016
- 2016-08-05 UA UAU201608600U patent/UA114373U/en unknown
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