UA116393C2 - THREE-CODE SEQUENCES SERVER WITH PROGRAMMED TIME PARAMETERS AND NUMBER OF PULSES IN A SERIES - Google Patents

Abstract

The sequence generator of the three code series pulses with programmable time parameters and the number of pulses in the series refers to automation, pulse, computing and measurement technology. The shaper contains four reversible binary counters, a synchronous D-flip-flop and two JK-flip-flops with zero input asynchronous inputs, three OR elements, three AND elements, three inverters, two I-NO elements, a series consisting of a series connected resistor and capacitor. The technical result is the expansion of the functionality of the shaper.

Description

The invention belongs to pulse technology and is intended for forming a sequence of three code series of pulses with programmable time parameters and the number of pulses in the series.

There are well-known generators that contain a quartz setting generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Clock generator. Copyright certificate of the USSR Mo 307502. - Bulletin of inventions. Mo 20, 1971; Clock generator. AS USSR Mo 354544. - Bulletin of inventions. Mo 30, 1972).

The disadvantage of the known devices is the limited functionality due to setting the pulse parameters to a fixed mode.

The closest in terms of technical essence and the result that is achieved is a sequence generator of three coded series of pulses with programmable time parameters and the number of pulses in the series (utility model patent of Ukraine Mo 53542 dated 11.10.2010), which contains: two reversible binary counters, each of which has a synchronization pulse supply input, a summation/subtraction debug input, a synchronous parallel download enable input and data feed inputs, a count mode enable input, an asynchronous set-to-zero input, an overflow output; first and second elements

OR; inverter; a chain consisting of a resistor and a capacitor connected in series; synchronous SW-trigger with the input of the asynchronous installation in the zero state, the first and second two-input elements I, while the common point of the series-connected resistor and capacitor is connected to the information input of the SW-trigger, with the inputs of the first and second two-input elements of the II, the output of the U-trigger from connected to the input of the first OR element, the output of which is connected to the second input of the second AND element; the output of the first two-input element is connected to the input of the asynchronous unit of the SW-trigger in the zero state; output of the second element

OR connected to the synchronous parallel loading enable input of the first counter; the overflow output of the first counter, which forms the output of the shaper, is connected to the input of the inverter, the output of which is connected to the enable input of the counting mode of the first counter; the values of the signals at the inputs of parallel data loading of the first counter are determined

Z duration of pulses at the output of the shaper; the inputs of the parallel loading of the second counter form the programming inputs of the shaper for a given pause between pulses; the output of the second element I is connected to the input of the asynchronous unit in the zero state of the first counter; the clock inputs of the first and second counters are connected to each other, creating the input of the shaper - the input of supplying a continuous periodic sequence of pulses from the output of the external generator; the clock input of the SW flip-flop creates the start pulse supply input (stage).

The disadvantage of the known device is limited functionality.

The basis of the invention is the task of improving the sequence generator from three code series of pulses with programmable time parameters and the number of pulses in the series by introducing a new composition of elements and a new organization of mutual connections between them.

The task is solved by the sequence generator of three coded series of pulses with programmable time parameters and the number of pulses in the series, which contains: two reversible binary counters, each of which has an input for supplying synchronization pulses, an input for debugging the summation/subtraction mode, an input enable synchronous parallel loading and data input, enable input of counting mode, input of asynchronous installation in the zero state, overflow output; the first and second OR elements; inverter; a chain consisting of a resistor and a capacitor connected in series; synchronous SW flip-flop with the input of the asynchronous unit in the zero state, the first and second two-input elements I, while the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, with the inputs of the first and second two-input elements I; the output of the Y-trigger is connected to the input of the first OR element, the output of which is connected to the second input of the second AND element; the output of the first two-input element | connected to the input of the asynchronous unit of the U-trigger in the zero state; the output of the second OR element is connected to the input of enabling synchronous parallel loading of the first counter; the overflow output of the first counter, which forms the output of the shaper, is connected to the input of the inverter, the output of which is connected to the enable input of the counting mode of the first counter; the values of the signals at the inputs of the parallel data loading of the first counter determine the duration of the pulses at the output of the shaper; the inputs of the parallel loading of the second counter form the programming inputs of the shaper for a given pause between pulses; output of the second element | connected to the input of the asynchronous installation in the zero state of the first 60 counter; the clock inputs of the first and second counters are connected to each other, creating the input of the shaper - the input of supplying a continuous periodic sequence of pulses from the output of the external generator; the clock input of the U-flip-flop creates a start pulse supply input (5iap), according to the invention, the following are introduced: the third and fourth reversible binary counters configured for subtraction mode, each of which has a synchronization pulse supply input, a debug input for summation/subtraction mode, an enable input synchronous parallel loading and data feed inputs, counting mode enable input, asynchronous installation input to the zero state, overflow output; second and third inverters; the first and second AND-NO elements; the third element

OR; the third element I; cyclic device, with a sequence of transitions 00-11-10-00 (0-3-2-0), which contains the first and second UC flip-flops with the input of the asynchronous unit in the zero state, while the inverse output of the first OK flip-flop is connected with the K input of the second UC flip-flop, the input of which is connected to the logic unit level, the inverse output of the second UC flip-flop is connected to the U input of the first UC flip-flop, the K input of which is also connected to the logic unit level, direct output the second

The CC-trigger is connected to the input of the first OR element; the overflow output of the first counter is connected to the first input of the second OR element, the output of which is connected to the enable input of the counting mode of the second counter; the overflow output of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the second OR element, to the second input of the first OR element, to the first input of the third OR element, to the first inputs of the first and second AND-NO elements; the overflow output of the third counter is connected to the second input of the third OR element, the second input of the first AND-NO element and the input of the third inverter, the output of which is connected to the second input of the second element AND1-NO; output of the first element

AND-NO is connected to the enable input of the counting mode of the third counter, the enable inputs of the loading mode of the second and first counters; the output of the third OR element is connected to the input of the third element AND, the second input of which is connected to the output of the second element AND, the output - to the input of the asynchronous installation in the zero state of the second counter; the overflow output of the fourth counter is connected to the second input of the first OR element, the loading mode enable inputs of the third and fourth counters, the clock inputs of the first and second UkK-triggers; the inputs of the parallel loading of the third counter form the programming inputs of the shaper for the specified number of pulses in series the inputs of the parallel loading of the fourth counter form the programming inputs of the shaper for the specified

From the pause between series of pulses; the inputs of the asynchronous installation in the zero state of the first and second K-triggers, the first, third and fourth counters are connected to the output of the second element I; the clock inputs of the third and fourth counters are connected to the input of the shaper.

The claimed former has a new composition of elements and a new organization of relationships between them, that is, it contains a new set of features that provide new technical properties. Technical result, as a result of these properties, expansion of the area of use and functional capabilities of the former.

In Fig. 1 shows the scheme of the former.

The shaper contains: the first (1), second (2), third (3) and fourth (4) reversible binary counters configured for the subtraction mode (0-0), which have an input for supplying clock pulses C, an input for enabling synchronous parallel loading I and data input inputs Оо-ХОз, input Ро of enabling/disabling the counting mode, input of the asynchronous device in the zero state B, overflow output Ра; the first (10), second (13) and third (17) OR elements; the first (11), second (12) and third (14) inverters; the first (15) and second (16) AND-NO elements; the first (8), second (9) and third (18) elements of II; a chain of series-connected resistor (5) and capacitor (b), connected to the power supply of the JHE; O-trigger (7), the first (19) and the second (20) UC-triggers with the input of the asynchronous installation in the zero state,

The common point of the series-connected resistor 5 and capacitor b is connected to the information input of the SW-trigger 7, with one input of the elements 8, 9. The output of the element 8 is connected to the input of the asynchronous installation of the O-trigger 7 in the zero state. The second input of element 9 is connected to the output of element 10. The output of element 9 is connected to the inputs A of the asynchronous installation in the zero state of counters 1, З, 4 and the input of element 18, the output of which is connected to the input of the asynchronous installation in the zero state of the counter 2.

The overflow output of the counter 1, which forms the output E of the shaper, is connected to the inputs of the element 13 and the input of the inverter Z, the output of which is connected to the input Po of the counter 1. The output of the overflow of the counter 2 is connected to the input of the inverter 12, the output of which is connected to the inputs of elements 8, 13 15, 16. 17. The overflow output of the counter C is connected to the inputs of elements 10, 15, 17 and the input of the inverter 14, the output of which is connected to the input of element 16. The output of element 15 is connected to by the enable input of the counting mode of the counter 3, the enable inputs of the loading mode of the counters 2, 1. The overflow output of the counter 4 is connected to the clock inputs of the triggers 19, 20, 60 with the second input of the OR element 10, the enabling inputs of the loading mode of the counters 3, 4.

The inverse output of the trigger 19 is connected to the input K of the trigger 20, the input / of which is connected to the level of a logical unit. The inverse output of the flip-flop 20 is connected to the input / of the flip-flop 19, whose input K is connected to the level of a logic unit. The direct output of the trigger 20 is connected to the third input of the element 10.

The values of the B-Ozb2riro signals at the inputs of the parallel data loading of counter 1 determine the duration of the pulses at the output of the generator. data loading bob102Oz counter C determine the number of pulses in series. The values of P-rzrgriro signals at the inputs of parallel data loading bob102Oz counter 2 determine the duration of the pause between series. The number of states of the cyclic device, which is equal to three, determines the number of series.

The inputs of the asynchronous unit to the zero state of the UC-triggers 19, 20 and counters 1, 3, 4 are connected to the output of element 9. The clock inputs of the counters are connected to each other, creating an input

With the shaper - the input of the supply of a continuous periodic sequence of pulses from the output of the external generator. The clock input of the U-trigger 7 creates the input of the supply of start pulses (stage).

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 5 and a capacitor 6 connected to the bus of the supply voltage ZHE, when the power source is turned on for a certain period of time, forms a logical zero level at the input AB of the asynchronous unit in the zero state of the trigger 7 and the inputs of elements 8 and 9, ensuring the formation of the logical zero level at the inputs B of the asynchronous installation in the zero state, respectively, of the CC-triggers 19, 20 and counters.

After the end of the transient process associated with turning on the power supply, triggers and counters go to the zero state, forming a logic zero level at the output of the trigger, at the counter overflow outputs, at the counter loading mode enable inputs 3, 4, at the output of element 10, with connected to the input of element I 9, which ensures confirmation (blocking) of level 0 at its output and after the end of the transient process associated with the charge of capacitor b, which ensures level 0 at the inputs of the asynchronous unit in the zero state of triggers 19, 20 and counters . Since the mode of asynchronous setting to the zero state has priority in relation to all the latest modes, then as long as on

From the output of element 9, the level of logical zero will be preserved, when clock pulses enter, the zero state of the counters will remain unchanged.

During the arrival of the readiness pulse (eiap) to the clock input C of the flip-flop 7 along its edge, the flip-flop 7 goes into a single state, forming the level of a logical unit at its output and the level of a logical unit at the output of element 10, and therefore at the input and output of element I 9 , which provides a logic unit level at the A inputs of the flip-flops and counters, removing the zero-state lock, enables boot mode. And then during the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C, the transition of counters 3, 4 to the state determined by the value of the signals set at their inputs of parallel data loading ЮБоб1О02Оз occurs, forming a single value on overflow outputs. As a result of these changes, counters 1, 2 go into loading mode, and counter Z - into counting mode, triggers 19, 20 go into a single state.

During the arrival of the second pulse, the transition of counters 1, 2 to the state determined by the value of the signals set at their inputs of parallel data loading 0о0102Оз3 occurs, forming a single value at the overflow outputs (at the output of the shaper). The content of counter Z is reduced by one, the content of counter 4 will remain unchanged. As a result of these changes, counters 2, 3, 4 go into saving mode, and counter 1 goes into counting mode. Trigger 7 goes to the zero state.

During the arrival of the next and subsequent clock pulses, the content of counter 1 decreases, and the state of counters 2, 3, 4 will remain unchanged until the content of counter 1 becomes equal to 0, which ensures a level of logic 0 at its overflow output (at the output of the shaper) , at the output of element 13 and a single value at the output of inverter 11, as a result of which counter 1 goes into the saving mode, and counter 2 - into the counting mode, the saving mode of counters 3, 4 will remain unchanged. This completes the formation of the first impulse in the series.

During the arrival of the next and subsequent clock pulses, the content of counter 2 is decremented, and the state of counters 1, 3, 4 will remain unchanged until the content of counter 2 becomes equal to 0, which ensures a logic 0 level on its overflow output, a single value on the outputs inverter 12, forming the level of a logical unit at the output of element 13 and a zero value at the output of element 15, as a result of which the counter Z goes into the counting mode, and the counters 1, 2 - into the download mode. This completes the formation of the first pause between pulses in the series.

During the introduction of subsequent clock pulses, the processes are similar (Fig. 3), until a pause is formed between the penultimate and last pulses in the series. And then, during the arrival of the next clock pulse, counters 1, 2 transition to a state determined by the value of the signals set at their inputs of parallel data loading 0о0б1О2Оз, forming a single value at the overflow outputs, the third counter goes to the zero state. As a result of these changes, a zero value is formed at the inputs and outputs of element 17 and at the output of element 18, which leads to the return of the second counter to the zero state.

During the introduction of subsequent clock pulses, the last pulse in the series is formed, the counter 4 goes into the counting mode. During the entry of the next and subsequent clock pulses, the content of counter 4 decreases, and the zero state of counters 1, 2, C will remain unchanged until the content of counter 4 becomes equal to 0, which ensures a level of logic 0 at its overflow output.

During the arrival of the next clock pulse, the transition of counters 3, 4 to the state determined by the value of the signals set at their inputs of parallel data loading 00010203 occurs, forming a single value at the overflow outputs. Trigger 19 goes to the zero state. The single state of flip-flop 20 will remain unchanged.

During the entry of the next and subsequent clock pulses, counters 3, 4 again transition to a state determined by the value of the signals that are set at their inputs of parallel data loading ЮОо0102Оз3, forming a single value at the overflow outputs. Trigger 20 goes to the zero state. The formation of the third series begins.

As soon as the next clock pulse arrives, the content of counter 4 will become equal to 0, which provides a level of logic 0 at its overflow output, at the output of the element OR 10, at the input and output of the element | 9, ensuring the formation of a logical zero level at the inputs B of the asynchronous unit in the zero state, respectively, of triggers 19, 20 and counters, that is, the generator returns to the initial state. With the arrival of the next start pulse, all processes are repeated.

Thus, after the end of the transition process associated with the inclusion of the source

A sequence of three code series, each of which contains (M--1) pulses, is generated from the power supply after the start pulse (stage) is applied to input C of the generator of a periodic sequence of clock pulses with a period T at the output of the generator (overflow output of counter 1). the duration of which is equal to VT. The duration of the pause between pulses in a series is equal to (0-11) T, the duration of the pause between series is equal to (P.2)T.

In Fig. 2 shows the transition graph of the shaper consisting of five rings (the first ring is the transition graph of counter 1, the second is the transition graph of counter 2, the third is the transition graph of counter 3, the fourth is the transition graph of counter 4, the fifth is the transition graph of cyclic device made on two UV triggers) with a common peak corresponding to the zero state of the trigger and counters, and in fig. C - time diagrams illustrating the work for the programming option B-3, 0-2, M-2, P-4.

Unlike the known device, the formation of a sequence of three coded series of pulses with programmable time parameters and the number of pulses in the series expands the functionality and scope of use of the shaper.

Claims (1)

DISCLOSURE OF THE INVENTION A sequence generator of three coded pulse series with programmable time parameters and the number of pulses in the series, containing: two reversible binary counters, each of which has a synchronization pulse supply input, a debug input for summation/subtraction mode, a synchronous parallel loading enable input, and inputs data input, counting mode enable input, asynchronous zero input, overflow output, first and second OR elements, inverter, circuit consisting of a resistor and capacitor connected in series, synchronous SW flip-flop with asynchronous zero input , the first and second two-input elements AND, while the common point of the series-connected resistor and capacitor is connected to the information input of the O-trigger, to the inputs of the first and second two-input elements AND, and the output of the SO-trigger is connected to the input of the first element OR, the output of which is connected to the second input of the second element AND, and the output of the first is double-ended second element AND is connected to the input of the asynchronous installation of the O-trigger in the zero state, the output of the second OR element is connected to the enable input of the synchronous 60 parallel loading of the first counter, where the overflow output of the first counter, which forms the output of the shaper, is connected to the input of the inverter, the output of which is connected to the enable input of the count mode of the first counter, and the values of the signals at the inputs of the parallel loading of the data of the first counter determine the duration of the pulses at the output of the shaper, also the inputs of the parallel loading of the second counter form the programming inputs of the shaper for a given pause between pulses, the output of the second element | connected to the input of the asynchronous unit in the zero state of the first counter, the clock inputs of the first and second counters are connected to each other, creating the input of the shaper - the input of the supply of a continuous periodic sequence of pulses from the output of the external generator, the clock input of the U-flip-flop creates the input of the supply of start pulses (2iap), which differs in that it is additionally introduced: the third and fourth reversible binary counters configured for the subtraction mode, each of which has an input for supplying synchronization pulses, an input for debugging for the summation/subtraction mode, an input for enabling synchronous parallel loading, and inputs for data supply, count mode enable input, asynchronous zero input, overflow output, second and third inverters, first and second AND-NOT elements, third OR element, third AND element, cyclic device with transition sequence 00-11-10-00/0 -3-2-0, which contains the first and second UV-triggers with the input of the asynchronous installation in the zero state, while the inverse output of the first OK flip-flop is connected to the K input of the second CC flip-flop, the input of which is connected to the level of a logic unit, the inverse output of the second CC flip-flop is connected to the input of the first CC flip-flop, the input of which is also is connected to the level of a logical unit, the direct output of the second CC flip-flop is connected to the input of the first OR element, the overflow output of the first counter is connected to the first input of the second OR element, the output of which is connected to the enable input of the counting mode of the second counter, and the overflow output of the second counter is connected to the input of the second inverter, the output of which is connected to the second input of the second OR element, to the second input of the first OR element, to the first input of the third OR element, to the first inputs of the first and second AND-NO elements, also to the overflow output of the third counter is connected to the second input of the third OR element, the second input of the first AND-NOR element and the input of the third inverter, the output of which is connected to the second input of the second AND-NOR element, and the output of the first AND-NOR element with connected to the enable input of the counting mode of the third counter, the enable inputs of the loading mode of the second and first counters, the output of the third element OR is connected to the input of the third element AND, the second input of which is connected to the output of the second element AND, the output - to the input of the asynchronous installation in the zero state of the second counter, the overflow output of the fourth counter is connected to the second input of the first OR element, the loading mode enable inputs of the third and fourth counters, the clock inputs of the first and second UC flip-flops, and the parallel loading inputs of the third counter form the programming inputs of the generator for a given amount pulses in series, the inputs of the parallel loading of the fourth counter form the programming inputs of the shaper for a given pause between the series of pulses, where the inputs of the asynchronous installation in the zero state of the first and second UV-triggers, the first, third and fourth counters are connected to the output of the second element I, and clock inputs of the third and fourth l and counters are connected to the input of the shaper. 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