UA129642U - DUAL-PHASE PULSE CONVERTER WITH ADJUSTED TIME PARAMETERS - Google Patents

Abstract

The two-phase pulse generator with reconfigured time parameters contains two binary counters, the first of which is reversible, tuned to the subtraction mode, which has a pulse input pulse output, overflow output, synchronous parallel load resolution input and digital input inputs the input of the asynchronous installation to the zero state (thus the active signal at the input of the synchronous parallel load resolution has priority over the active signal n and the input of the digital mode resolution, and the active signal at the input of the asynchronous zero setting takes precedence over the active signal at the synchronous parallel resolution input and digital mode resolution input); a starter device comprising a trigger with zero input asynchronous installation and a circuit consisting of series resistors and a capacitor connected to a power source; the first and second elements I; the first and second elements OR; a common point in series of connected resistor and capacitor is connected to the first inputs of the first and second elements And; the second input of the first element And forms the input pulse stopping the formation of output pulses; the output of the first element And is connected to the input of the installation of the trigger in the zero state; the first input of the first element OR is connected to the output of the trigger; the output of the first element OR is connected to the first input of the second element I; the output of the second element I is connected to the inputs of the asynchronous installation in the zero state of the first and second meters. Introduced the third and fourth elements And, with the startup device is made on an asynchronous RS-trigger. Instead of the second four-digit counter, a two-bit subtraction counter with the sequence of transitions 00-11-10-01-00, made on two JK triggers with the input of the asynchronous installation to zero, was introduced. The first JK trigger has inverted inputs J and K; the second JK flip-flop has inverted and direct inputs J and K, which are joined by I. The inverted inputs of the JK flip-flops are connected to the output of the second element OR and the input of the synchronous parallel load of the first counter. The direct inputs J and K of the second JK trigger are connected to the inverse output of the first JK trigger; the direct output of the first JK trigger is connected to the first inputs of the third and fourth elements I, with the second input of the first element OR, with the fourth input of the loading of the first counter. The first and third load inputs of the first counter are coupled to the inverse output of the first JK trigger; the second boot input is connected to logic zero; the direct output of the second JK trigger is connected to the second input of the fourth element I and the third input of the first element OR; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second element OR. The clock inputs of the first and second counters form the input of the shaper - the input of the filing of a periodic pulse sequence from the output of an external generator. The input of the asynchronous installation to a single state of the RS-trigger forms the input of the pulse start. The output of the third element I forms the output of the first phase (F1), and the output of the fourth element I forms the output of the second phase (F2) of the pulses.

Description

the second counters form the input of the shaper - the input of the supply of a periodic sequence of pulses from the output of the external generator. The input of the asynchronous unit to the single state of the H5 flip-flop forms the input of the supply of start-up pulses. The output of the third element I forms the output of the first phase (ET), and the output of the fourth element I forms the output of the second phase (E2) of pulses. what

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The useful model belongs to pulse, computing and measuring technology and is intended for the formation of a two-phase sequence of pulses with reconfigurable time parameters.

There are well-known generators that contain a quartz setting generator that operates in continuous mode, a synchronization device and an output device that ensures the formation of the necessary pulses, the time parameters of which are determined by the time parameters of the pulses supplied to the input (Y.V. Novikov Fundamentals of digital technology. - M.: MIR, 2001. - Fig. 5.13-5.18).

The disadvantage of known devices is the complexity of the internal structure.

Known generators of a periodic multiphase sequence of pulses with reconfigurable time parameters (Ukrainian patents for the invention Mo Me87081, 89240, 106091, 106395, 10807, 106867, 10888, 106091, 107028).

The disadvantage of the devices is the complexity of the structure due to the need to use two multi-bit binary counters, decoders.

As the closest analogue in terms of technical essence and the result achieved, a two-phase pulse sequence generator with reconfigurable time parameters (patent of Ukraine for utility model 63193) containing two binary counters, the first of which is reversible, configured for subtraction mode, with a supply input, was selected synchronization pulses, synchronous parallel download enable input and data feed inputs during download, count mode enable input, asynchronous setup input in the zero state, overflow output; a start-stop device containing a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a series-connected resistor and a capacitor connected to a power source; the first and second elements of I; the first and second OR elements, while the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the first AND element; the output of the first element AND is connected to the inputs of the asynchronous installation of counters in the zero state; the clock inputs of the counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external quartz generator; the inputs of the parallel loading of the first counter form the inputs of tuning the shaper to the given time parameters of the output pulses.

The disadvantage of this device is the complexity of the generator circuit, which is due to the construction of a start-stop device on a synchronous O-trigger and the use of a second four-digit counter and, as a result, high power consumption and high cost.

The useful model is based on the task of simplifying the reconstruction of the shaper for a given duration of pulses, reducing the power consumption and cost.

The task is solved by the fact that the generator of a two-phase sequence of pulses with reconfigurable time parameters, containing two binary counters, the first of which is reversible, configured for the subtraction mode, having an input for supplying synchronization pulses, an overflow output, an input for enabling synchronous parallel loading and inputs for data supply during loading, the enable input of the digital mode, the input of the asynchronous installation in the zero state (in this case, the active signal on the enable input of the synchronous parallel loading has priority in relation to the active signal on the enable input of the digital mode, and the active signal on the input of the asynchronous installation in the zero state has priority in relation to the active signal at the synchronous parallel download enable input and at the digital mode enable input); a start-stop device containing a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a resistor and a capacitor connected in series, connected to a power source; the first and second elements of I; the first and second OR elements; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the second input of the first element forms the input of the supply of pulses to stop the formation of output pulses; the output of the first element is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first OR element is connected to the first input of the second AND element; output of the second element I! connected to the inputs of the asynchronous installation in the zero state of the first and second counters, according to the useful model, the third and fourth elements of I are introduced, while the start-stop device is made on an asynchronous Co-trigger, and instead of the second four-digit counter, a two-digit subtractive counter with a sequence of transitions is introduced 00-11-10-01-00, executed on two UV-triggers with the input of the asynchronous unit in the zero state; the first UK flip-flop has inverse inputs .«/ and K; the second UC-trigger has inverse and direct inputs ./ and К, which are combined by И; the inverse inputs of the CC-triggers are connected to the output of the second OR element and the input of allowing synchronous parallel loading of the first OR counter; direct inputs U and K of the second Uk-trigger are connected to the inverse output of the first UkK-

trigger; the direct output of the first CC-trigger is connected to the first inputs of the third and fourth elements of Y, to the second input of the first OR element, to the fourth input of loading the first counter; the first and third loading inputs of the first counter are connected to the inverse output of the first UV-trigger; the second loading input is connected by a level of logical zero; the direct output of the second CC-trigger is connected to the second input of the fourth element AND and the third input of the first OR element; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous unit to the single state of the Ko5-trigger forms the input of the supply of start pulses; the output of the third element I forms the output of the first phase (ET), and the output of the fourth element I forms the output of the second phase (E2) of pulses.

In fig. 1 shows the scheme of the former.

The shaper contains: reversible binary counter 1 configured for subtraction mode, which has a clock pulse supply input C, a summation/subtraction mode debug input Ш, a synchronous parallel loading enable input Г and data input inputs Оо-Оз, a count mode enable input Е, the input of the asynchronous installation into the zero state of the KE; the first (2) and the second (3) CC-triggers with the transition permission input (inverse CC inputs) and the inputs of the asynchronous installation in the zero state K; K5-trigger 4; the first (5), second (6), third (7) and fourth (8) elements of I!; the first (9) and second (10) OR elements; resistor 11 and capacitor (12) connected in series, connected to the same power source.

The common point of the series-connected resistor 11 and capacitor 12 is connected to the first inputs of the elements 5, 6. The second input of the element 5 forms the input of the supply of stop pulses (Zior) of the formation of output pulses. The output of element 5 is connected to the input (K) of the installation in the zero state of the K5-trigger. The second input of element 6 is connected to the output of element 9. The output of element 6 is connected to the inputs of the asynchronous unit in the zero state of the counter 1 and UV-triggers (2, 3).

The inverse inputs of .«K flip-flops, which form the transition enable input of the second counter, are connected to the output of element 10 and the enable input of synchronous parallel loading (I) of counter 1. The direct inputs U and K of flip-flop Z are connected to the inverse output (1 ) of UV-trigger 2.

The direct output of the trigger 2 is connected to the first inputs of elements 7, 8 and to the second input of the element

From 9. The first (bo) and third (O2) loading inputs of counter 1 are connected to the direct output of UV trigger 2. The second (0) loading input is connected to the logical zero level. The fourth input (Oz) of the counter load is connected to the inverse output of the K-trigger 2. The direct output of the C-trigger is connected to the second input of the element 8 and the third input of the element 9. The outputs of the second (01), third (02) and the fourth (Oz) digits of counter 1 are connected to the inputs of element 10. The clock inputs (C) of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator. Input of asynchronous installation (5) in single state

The B5 flip-flop forms the start pulse supply input (Zag). The output of element 7 forms the output of the first phase (E1), and the output of element 8 forms the output of the second phase (E2) of pulses.

We will consider the function analysis for the setting option for the formation of a two-phase sequence, the duration of the pulses is equal to 5T, and the pauses between adjacent phases are equal to 8T, provided by the value of the signals generated at the inputs of the parallel loading of the counter 1. The presence of a chain consisting of a resistor 11 and a capacitor 12 connected in series, connected to the supply voltage bus, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 5 and 6, ensuring the formation of a logical zero level at their outputs, that is, at the inputs of the asynchronous installation in the zero state (K) of triggers 2, 3 , 4 and counter 1. After the capacitor is charged, the single value at the first input of element 6 remains unchanged.

After the end of the transient process associated with turning on the power supply, counter 1 and flip-flops go to the zero state, forming: a logical zero level at the outputs

Oo-Oz counter 1; at the output of element 10, the value of the signal at which is equal to the logical sum of the signals from the outputs СО, О2, Oz (I-О m О2 m Oz); on the direct outputs of triggers 2, 3; at the input of allowing synchronous loading of counter 1 and at the inverse inputs of y and K-triggers 2, З (at the input of allowing synchronous transition of the second counter); at the output of element 9, which is connected to the input of element 6, which provides a logic zero level at the inputs K of the asynchronous unit to the zero state of the counter 1 and triggers 2, C and after the transition process associated with the charge of the capacitor 12.

Since the mode of asynchronous setting of the counter 1 and triggers 2, Z to the zero state has priority in relation to all the last modes, as long as the logic zero level is maintained at the inputs of element 9, upon the arrival of clock pulses, the zero state of the counter 1 and triggers 2, C will remain unchanged, that is, the zero value at the outputs of the shaper (Е1-01.02, г2-01.02) will remain unchanged.

During the arrival of the start pulse (Zag) at the input 5 of the flip-flop, the 4 flip-flop goes into a single state, forming a level of a logical unit at its output (0-1), at the input and output of element 9, which provides a level of a logical unit at the inputs K of counter 1 and triggers 2, 3, removing the blocking. Since at the entrances | of counter 1 and triggers 2, C level of logical zero, then until the arrival of the next clock pulse, the first counter is in the mode of readiness for loading, and the second counter is in the mode of readiness for transition to the first next state. And then, during the entry of the first (after the end of the transition process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals generated at the inputs Yuo-O2-SI-Z, ri-Oz320. Counter 1 goes to state О3з020100-0101-5, the second counter goes to the next state (02-01-1), which leads to the formation of a single value at the output of element 10, at the inputs of counter 1, at the inverse inputs .) and K-triggers 2, 3, that is, before the prohibition of loading counter 1 and transition of the second counter, allowing the counting (subtraction) mode of counter 1.

During the arrival of subsequent clock pulses, the content of counter 1 will decrease, while the state of the second counter remains unchanged. As soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10. As a result, counter 1 will again go into download mode, and the second counter will go into transition mode. During the arrival of the next clock pulse, counter 1 is loaded in parallel with the values of the signals generated at the inputs ЮОо-01-02-0, ЮОз-1. Counter 1 goes into state

Oz3020100-1000-8, the second counter - to the next state (02-1, O01-0). In the future, the processes are similar, that is, as soon as the content of counter 1 becomes equal to 0001, a zero value is formed at the output of element 10, counter 1 again switches to loading mode, and the second counter to transition mode. Counter 1 is loaded in parallel with the values of the signals at the Oo-Yuz inputs. Counter 1 again goes to state 1010-10, and the second counter goes to the next state according to its transition graph, at the outputs of the second counter (at the outputs of triggers 2, 3) values are formed according to the state, which determine the values of the signals at the outputs of elements 7, 8 ( at the outputs of the shaper E1, E2).

Zo In fig. 2 shows the transition graph of the shaper consisting of four rings (the upper ring is the transition graph of counter 1, the second ring is the transition graph of the second counter, the third ring is the value of the signals at the output E1, the fourth ring is the value of the signals at the output E2 with a common peak corresponding to the zero state counters, and Fig. C shows diagrams illustrating the work for the configuration option for the formation of a two-phase sequence, the duration of which pulses is equal to 5T, and the pause between adjacent phases is equal to 817.

Stopping the process of forming the output sequence of pulses is carried out by applying a pulse corresponding to the level of a logical unit to the stop input (Bor), which forms an active signal level at the input K of the asynchronous unit K5-trigger, which leads to its transition to the zero state (0-0). The pulse 5i0or, as a rule, is asynchronous in relation to the pulses of the external generator and to the state of the counters.

If the second counter (triggers 2, 3) is in the zero state at the moment of the Bior pulse, then when trigger 4 goes to the zero state, a logical 0 level will be formed at the inputs of element 9 and its output, causing a logical zero level at the input and output of element 6 , which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of forming pulses at the outputs E1, E2.

If, at the time of arrival of the Bior pulse, the second counter is in a state other than zero, then the output of element 9 connected to the input of element 6 will have a level of logical unit. Since the second input of element 6 also has the level of a logical unit, determined by the unit value on the capacitor, then the output of element 6 (at the inputs K of the counter and triggers 2, 3) will have a level of logical unit. From this it follows that at the moment of the introduction of the pulse 5ior, the termination of the formation will not occur, thereby preventing the distortion of the last pulse in the output sequence. And only with the introduction of further clock pulses, when the transition of the second counter to the zero state will occur at the inputs of element 9 and its output, a level of logical 0 will be formed, causing the level of logical zero at the input and output of element b, which will lead to the transition of counter 1 to the zero state, and therefore to the termination of the process of formation.

With the arrival of the next start pulse, all processes are repeated.

In contrast to the known device, the simplification of the structure of the start-stop device and the second counter, made on two OK-triggers, made it possible to simplify the production technology of the former, to reduce the power consumption and cost.

Claims (1)

UTILITY MODEL FORMULA A two-phase pulse train generator with reconfigurable timing parameters, containing two binary counters, the first of which is reversible, configured for subtraction mode, having a sync pulse supply input, an overflow output, a synchronous parallel load enable input and load data inputs, digit mode enable input, asynchronous setup input to zero state (while the active signal at the synchronous parallel loading enable input has priority over the active signal at the digital mode enable input, and the active signal at the asynchronous setup input to zero state has priority over active signal at the synchronous parallel download permission input and at the digital mode permission input); a start-stop device containing a trigger with the input of an asynchronous installation in the zero state and a chain consisting of a resistor and a capacitor connected in series, connected to a power source; first and second elements AND first and second elements OR; the common point of the series-connected resistor and capacitor is connected to the first inputs of the first and second elements of I; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element AND is connected to the input of the trigger in the zero state; the first input of the first OR element is connected to the output of the trigger; the output of the first element is ORed to the first input of the second element !; the output of the second element I is connected to the inputs of the asynchronous installation in the zero state of the first and second counters, which differs in that the third and fourth elements I are introduced, while the start-stop device is made on an asynchronous H5 trigger, and instead of the second four-digit counter, a two-digit subtractive the counter with the sequence of transitions 00-11-10-01-00, made on two 9OK-triggers with the input of the asynchronous unit in the zero state; the first .K-flip-flop has inverse inputs. and K; the second Uk trigger has inverse and direct inputs ./ and К, which are combined by И; the inverse inputs of the K-triggers are connected to the output of the second OR element and the input of allowing synchronous parallel loading of the first counter; direct inputs U and K of the second UV-trigger are connected to the inverse output of the first UV-trigger; the direct output of the first UOK-trigger is connected to the first inputs of the third and fourth elements AND to the second input of the first OR element, to the fourth input of loading the first counter; the first and third loading inputs of the first counter are connected to the inverse output of the first .K-trigger; the second loading input is connected by a level of logical zero; the direct output of the second OK-trigger is connected to the second input of the fourth element AND and the third input of the first OR element; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element; clock inputs of the first and second counters form the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the input of the asynchronous installation to the single state of the No-trigger forms the input of the supply of start pulses; the output of the third element I forms the output of the first phase (E1), and the output of the fourth element I forms the output of the second phase (E2) of pulses. R sy b: eh yi ki ik a V z I oz EE v -- Y yasenya shiy ; ЗШ ши и я Кы sny я я ВХ В В Е Я онклчкн; tires SHE SHE: Well, me too. with A 1 i- STE zhu ! ZOV Ye rn yo and Bey V. Hey hams SHY! KE. Я шы шк рек дык K U ey ee Ma Y Kon ish SHY I 1 pov vyvyh kuas zanom td tde AK ku kA AzhikaAAKAA A u. to her EM Dakh shchi YAVNU nya ohfkhonyuhoko" will zh zho lyna NN Feya ad I NA M NT yah ho hom PMZH NN nt GEN KI 7 shi nonov ovo sen they 4 rya De Y se Mnrya EU NE TV NUK nn I" "BLADES NOT SHE oo kn OO yr yr a 33 I | ev eh ko an i Kk nannya EE Or one yutyyuute ko I ; and Du KM "g yah ho VUZh oon: and in V ns ; Shk VO sh her and WE NV MK UM NM iyau p "LMtt And her in them W KI fesettesnnnnkttyatlnyali N skv enny Ek nn B in Fig 2 her KK "Vi" MOZ HE VN i is " 1 Defiofkfroooioof io rooo ooo ro rorovom ovo rooo GUILTY ZSH NE N M rr nn enie meter nn nn ros shame oso ortho kn nn nn i mne nm m o ni v wa ne ny v nn a o NN EN KAK KA NE NKY JUST the root noorennn I i SE EVEiNVN volo PO MO ONKO, and man zny pi pi i my pok z M p AK YOU Piny m; we are connected to the network and POV in KK nyanya I EE p SE Z OO Vo Ko oas. rchne zho dkskieonnki so vy kn nin m o p in VE dekkkkkya E Her sei dk skik nya kyu inkky kin snninkn zhk VEN kinni ni rkyudooninki dnyni zr, Z