UA113592U - FORMER OF THE PERIODIC SEQUENCE OF IMPULSES WITH PROGRAMMABLE DURATION - Google Patents

Abstract

A periodic pulse shaper with a programmable duration, a delay of the start of the formation relative to the starting pulse and a fixed parity of seven, contains a synchronous D-trigger with the induction of the asynchronous zero setting; reversible binary counter tuned to subtraction mode, having clock input, digital mode resolution input, asynchronous zero input, overflow output, synchronous parallel load resolution input and load inputs; inverter; the first and second elements OR; the first and second two-port elements I; a circuit consisting of a series-connected resistor and a capacitor, the common point of the series-connected resistor and capacitor is connected to the information input of the D-trigger, with the inputs of the first and second elements And; the second input of the first element And forms the input pulse stopping the formation of output pulses; the output of the first element I is connected to the input of the asynchronous installation of the D-trigger in the zero state; the output of the D-trigger is connected to the first input of the first element OR, the output of which is connected to the second input of the second element And; the output of the second element I is connected to the input of the asynchronous installation of the counter in the zero state; the clock input of the counter forms the input of the shaper - the input of the filing of a periodic pulse sequence from the output of an external generator; the clock input of the D-flip-flop forms the input of the trigger pulse; parallel counter load inputs form the shaper programming inputs for a predetermined output pulse duration. Additionally introduced: third and fourth elements I; element OR NOT; module assembly inversion element two (NOXOR), first, second, and third synchronous DL triggers with zero input asynchronous installation forming a cyclic device (second counter) with transition sequence 000-001 –0101 01-011-110-100 -000.

Description

OR elements; the first and second two-input elements of the Y chain consisting of a series-connected resistor and capacitor, while the common point of the series-connected resistor and capacitor is connected to the information input of the Y-trigger, with the inputs of the first and second elements of I; the second input of the first element I forms the input of the supply of pulses of the stop of the formation of output pulses; the output of the first element I is connected to the input of the asynchronous installation of the Y-trigger in the zero state; the output of the Y-trigger is connected to the first input of the first OR element, the output of which is connected to the second input of the second AND element; the output of the second element I is connected to the input of the asynchronous counter installation in the zero state; the clock input of the counter forms the input of the shaper - the input of supplying a periodic sequence of pulses from the output of the external generator; the clock input of the SW-trigger forms the start pulse supply input; the inputs of parallel loading of the counter form the inputs of programming the shaper for the given duration of the output pulses, according to the useful model, entered: the third and fourth elements AND - element OR-NO; element inversion of addition modulo two (MOHOK), the first, second and third synchronous PI-triggers with the input of the asynchronous installation in the zero state, which form a cyclic device (second counter) with the sequence of transitions 000-001-010-101-011-110- 100-000, while the direct output of the first YI-trigger is connected to the Y input of the second OI-trigger by the first input of the MOHOK element, the output of which is connected to the Y input of the first I --trigger; the direct output of the second OI-trigger is connected to the input Y of the third OI-trigger and the first input of the third element I, the output of which forms the output of the shaper; the direct output of the third PI-trigger is connected to the second inputs of the third element I and the MOHOK element; the output of the lower digit of the first counter is connected to the input of the inverter, the output of which is connected to the first input of the OR-NOT element; the output of the OR-NOT element is connected to the inputs of I. PI -triggers; the outputs of the second, third and fourth digits of the first counter are connected to the inputs of the second OR element, the output of which is connected to the enable input of the synchronous parallel loading mode of the first counter and to the second input of the OR-NOT element; clock inputs of PI - triggers are connected to the input of the shaper; the inputs of the asynchronous installation in the zero state of PI .- triggers are connected to the output of the second element I.

The claimed former has a new composition of elements and a new organization of relationships between them, that is, it contains a new set of features that provide new technical properties.

The technical result, as a consequence of these properties, is the simplification of the structure of the former, its manufacturing technology and, as a result, the reduction of power consumption and cost reduction.

In fig. 1 shows the schematic diagram of the former.

The shaper contains: the first reversible binary counter (1), configured for the subtraction mode, which has an input for the supply of clock pulses C, an input for configuring the summation/subtraction mode I), an input for enabling synchronous parallel loading I, 1 input for data supply Out-Out, an input enabling the counting mode Po, the input of the asynchronous installation to the zero state K, the overflow output Po; synchronous IO-trigger (2) with the input of the asynchronous installation in the zero state; the first (3), second (4) 1 third (5) synchronous PI-triggers with the input of the asynchronous unit in the zero state, which form a cyclic device (second counter) with the sequence of transitions 000-001-010-101-011-110-100 -000, first (6), second (7) 1 third (8) elements And; first (9) 1 second (10) elements OR; element OR-NO (11); MOHOK element (12); inverter (13) chain consisting of series connected resistor (14) 1 capacitor (15).

The direct output of trigger 2 is connected to the I input of trigger 3 1 with the first input of element 12, the output of which is connected to the Y input of trigger 2. The direct output of trigger 3 is connected to the I input of trigger 4 1 with the first input of element 8, output which is formed by the output of the shaper E. The direct output of the trigger 4 is connected to the second inputs of elements 8, 12. The output of element 8 is connected to the second input of element 9. The output of the junior digit of the counter | is connected to the input of the inverter 13, the output of which is connected to the first input of the element 11. The output of the element 11 is connected to the inputs of the AND OI-triggers. The outputs of the second (01) third (02) 1 fourth (O3) digits of the counter 1 are connected to the inputs of the element 10, the output of which is connected to the second input of the element 11 1 input Y, of the counter 1. The common point of the series-connected resistor 13 1 capacitor 15 is connected to the input Y of the trigger 2, the input of the element b 1, the input of the element 7, the output of which is connected to the inputs of the asynchronous installation in the zero state of the first and second counters. The second input of the element b forms the stop input (5(or) of the formation of output pulses. The output of the element 6 is connected to the input of the asynchronous installation of the trigger 2 in the zero state.

Inputs Ю30201000 of parallel loading of counter I form inputs б30б2б15о for programming the shaper for the given duration of pulses at the output. The clock inputs C of the counter 1 1 I -triggers are connected to each other and form the input of the shaper - the input of the supply of a periodic sequence of pulses C from the output of the external generator. The clock input C of trigger 2 forms the start input (5(agi) formation of output pulses.

The former works in the following sequence.

The presence of a circuit consisting of a series-connected resistor 13 and a capacitor 15 connected to the supply voltage bus TE, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements b and 7, ensuring the formation of a logical zero level at their outputs, connected to the inputs K of the asynchronous installation in the zero state of the counter I 1 of the triggers 2, 3, 4, 5. After the end of the transient process associated with turning on the power source, the triggers and the counter | go to the zero state, forming a logical zero level on the direct outputs and on the overflow output Ri of the counter I, on the direct outputs of PI, triggers, on the output of element 10, on the input of allowing synchronous loading of the counter 1, a single value on the output of the inverter, a zero value on the output element 11 1 at the output of element 8 (at the output of the shaper), which leads to the formation of a logical zero level at the output of element 9, which is connected to the input of element 7, which ensures confirmation of the level of logical zero at its output, and after the transition process, associated with the charge of the capacitor 15, forming a level of logical zero at the inputs K of the asynchronous unit in the zero state of the counter I 1 of the ЮI/-triggers. Since the mode of asynchronous setting to the zero state has priority in relation to all the last modes, as long as the zero level remains at the input of element 7 (and therefore at its output), the zero state of the counter and PI triggers and the zero value at the output of the shaper will remain unchanged.

During the arrival of the trigger pulse (5iap) at the input C of flip-flop 2 along its edge, the flip-flop goes into a single state (0-1), forming a level of a logical unit at the output of element 9, and therefore at the input and output of element 7, which provides a level of a logical unit on inputs K of the counter and OI-triggers, removing the blocking of the zero value, as a result of which the counter 1 goes into the mode of readiness to receive information from the Bo-Yuz inputs. And then, during the onset of the first (after the end of the transition process associated with the removal of blocking) clock pulse C along its edge, counter 1 is loaded in parallel with the values of the signals bz3b2bi10b0, which are applied to the corresponding inputs Yuz3-O0, which leads to the formation of a single value on the overflow output of counter I, the unit value at the output of element 10, before the loading mode is disabled and the counting (subtraction) mode of counter 1 is enabled.

Since the zero value at the output of element 11 remained unchanged, the zero state of PI flip-flops remains unchanged. During the introduction of the next and subsequent clock pulses, the content of the counter | will decrease, and the zero state of PI flip-flops will remain unchanged, that is, the zero value on the direct outputs of PI flip-flops 1 at the output of the generator will remain unchanged until the content of counter 1 becomes equal to 0001. As a result of this transition at the output of element 10 1 at the input And, a logical zero level is formed in counter 1, and a logical one level is formed at the output of element 11, which leads to the transition of counter 1 to the loading mode, and the second counter (PI -triggers) to the transition mode to the next state, 1 then during the entry of the next clock pulse along its edge again parallel loading of the counter | by the values of the signals бз3зб2бибо, which are applied to the corresponding inputs 3-0, which leads to the formation of a single value at the output of element 10 (at input I, counter 1), which again leads to the prohibition of the loading mode, the permission of the counting (subtraction) mode of the counter I, and the first The YUI flip-flop goes into a single state. Zero value at the output of element 8, that is, at the output of the shaper.

During the introduction of subsequent clock pulses, the processes are similar. As soon as the second counter goes to the state 110 at the output of the element 85, that is, at the output of the shaper, a logic unit level will be formed, which will remain unchanged until the second counter goes to the next state (100). During the introduction of subsequent clock pulses, the processes are similar (illustrated on transition graphs - fig. 2 1 on time diagrams - fig. 3).

Thus, after the end of the transient process associated with the removal of the blocking, during input C of the generator of a periodic sequence of pulses with a period T, a periodic sequence of pulses 3 is generated at the output of the generator with a fixed frequency equal to seven, the programmed duration of pulses (In), which is determined by the value of the control word В - (-ВТ, 1 delay (iz) of the start of formation relative to the start pulse, the value of which also depends on the value of the control word В and the moment of onset of the pulse ap (ZVT«e58-1)Т)

Stopping the process of forming a sequence of pulses at the output of the generator is carried out by applying a pulse corresponding to the logical zero level to the stop input (bor), which forms a zero signal level at the input K of the asynchronous unit of the U-trigger 5, which leads to its transition to the zero state (0- 0).

The pulse 5i0or, as a rule, is asynchronous in relation to the pulses of the external generator and to the state of the counters. If at the moment of the arrival of the first clock pulse after the pulse is applied, the second counter (I-triggers) will be in a state different from the PO, in which the value of the signal at the output of element 8 is equal to zero (E-0), then when the trigger 5 goes to the zero state (0-0) at the inputs of element 9 and its output, a logical zero level will be formed, causing a zero level at the input and output of element 7 (on the inputs of the installation to the zero state of the counter 1! 1 UI-triggers), which will lead to the transition of the counters to zero state, i.e. termination of the generation process.

If, at the time of entry, the second counter will be in the state 110, which is characterized by a level of logic one at the output of element 8, connected to the input of element 9, causing a level of logic one at its output, connected to the input of element 7, the termination of generation will not occur, since at the second input of this element also has the level of a logical unit, determined by the voltage on capacitor 15, which was charged when the power source was turned on, then the output of element 7, and therefore the inputs K of the counter 1 and OI-triggers, will have a level of a logical unit. It follows from this that at the moment of the introduction of the pulse "Cor, the termination of the generation will not happen, thereby preventing the distortion of the last pulse in the output sequence. It is only with the introduction of further clock pulses, when the transition of the second counter to the next state (100) occurs, that a logical 0 level will be formed at the output of element 8, causing a level of 0 at the input and outputs and at the outputs of elements 9, 7, which will lead to the transition and blocking of zero state of the counter 1 1 PI -triggers, and therefore before the termination of the generation process. With the arrival of the next start pulse, all processes are repeated.

In fig. 2 shows the graph of transitions of the shaper consisting of three rings (the lower ring is the transition graph of counter I, the upper ring is the transition graph of the cyclic device (the second counter), the middle ring is the value of the signal at the output of the shaper) with a common peak corresponding to the zero state of the counters, and in fig. 3 - time diagrams illustrating the work for the B-3 programming variant, which determines the parameters of the output sequence of pulses - the duration of pulses is 3T, the frequency of pulses is seven, the duration of the delay of the start of formation relative to the starting pulse is within the range of more than 1571 1 less than 161.

Unlike the known device for forming a periodic sequence of pulses with a programmable duration, delaying the start of formation relative to the start pulse 1 with a fixed spacing equal to seven extends the scope of application of the former 1 and its functionality, and preventing the use of the adder simplifies the scheme.

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