UA113013U - SYMMETRIC SINGLE CODE SERIES OF PULSES WITH PROGRAMMED PARAMETERS - Google Patents

Abstract

Shaper symmetric single code series pulses with programmable parameters, contains: reversible binary counters, each of which has a pulse input pulse input, debug / summation input input, synchronous parallel load resolution input and input feed inputs, input feed input asynchronous zero setting, overflow output; inverter; element OR; a circuit consisting of a series resistor and a capacitor; start / stop device containing a synchronous D-flip-flop with zero input asynchronous setting, first and second two-input elements I. Introduced: third reversible binary counter having synchronization pulse input, summation input / subtraction input, input / subtraction input synchronous parallel loading and inputs of loading of the downloaded data, an input of the permission of the counting mode, an input of an asynchronous installation in a zero state, an output of overflow; a second synchronous D-trigger with zero input asynchronous installation; the second inverter; the third, fourth, fifth and sixth two-port elements of I.

Description

the overflow of the first counter, which forms the first output of the shaper, is connected to the first inputs of the third and fourth elements of T; the overflow output of the third counter is connected to its enable input of synchronous parallel loading, the second input of the third element |, the first input of the sixth element AND and the input of the second inverter, the output of which is connected to the enable input of the counting mode of the third counter, the input of the first element AND, the inputs of the first and third elements of Ii, the overflow output of the second counter, which forms the fourth output of the shaper, is connected to the load mode enable input of the first counter, the clock input of the third counter, the inputs of the fifth and sixth elements of I; the output of the third element AND forms the second output of the shaper; the output of the fourth element AND forms the third output of the shaper; the output of the fifth element forms the fifth output of the shaper; the output of the sixth element AND, which forms the sixth output of the shaper, is connected to the clock input of the second SW flip-flop, the inverse output of which is connected to its input 0, and the direct output is connected to the second input of the OR element; the inputs of the asynchronous installation in the zero state of the third counter and the second O-trigger are connected to the output of the second element I; the data load inputs of the third counter form the shaper tuning inputs for a given number of pulses in series.

The claimed former has a new composition of elements and a new organization of relationships between them, that is, it contains a new set of features that provide new technical properties.

The technical result, as a consequence of these properties, is the expansion of the former's functional capabilities.

In fig. 1 shows the scheme of the former. In fig. 2 shows a graph of transitions of the shaper, and in fig. C - graphs explaining the operation of the shaper for one debugging option.

The generator contains: the first (1), second (2) and third (3) reversible binary counters, each of which has: an input for supplying clock pulses C, an input for debugging the summation/subtraction mode and, an input for enabling synchronous parallel loading of the GI and input inputs of downloadable data Oo-Yuz, the input of the permission of the counting mode Po, the input of the asynchronous installation in the zero state K, the overflow output

Ra; the first (7) and second (4) synchronous O-triggers with the input of the asynchronous installation in the zero state; the first (12) and second (11) inverters; the first (8), second (9), third (13), fourth (14), fifth (15) and sixth (16) two-input elements I!; a chain of serially connected resistor (5) and capacitor (b), connected to a power source, the common point of which is connected to the information input of O-trigger 7, to one input of element 8 and to one input of element 9; the second input of element 9 is connected to the output of element 10. The output of element 9 is connected to the input of the asynchronous installation of counters and trigger 4 in the zero state. The output of the element 8 is connected to the input of the asynchronous O-trigger 7 in the zero state.

The inputs of the parallel loading Uo-UOz counter 1 form Borir2oz inputs for setting the shaper for the given duration of pulses in series, the loading inputs O0o-UOz of counter 2 form the dodid2az inputs for setting the shaper for the given duration of the pause between pulses in the series, the loading inputs O0o-UOz of counter Z form inputs rorirgr3 setting the shaper to a given number of pulses in a series.

The overflow output of counter 1, which forms the first output of the shaper Ei5, is connected to the inputs of elements 12, 13, 14 and the input Po of counter 2.

The overflow output of the counter 2, which forms the fourth output of the PE shaper, is connected to the inputs of elements 15, 16 and the inputs of H. counters 1, 2. The overflow output of the counter C is connected to the inputs of elements 11, 14, 16. The output of element 11 is connected to the input of Ro counter 3 and the inputs of elements 8, 13, 15. The clock inputs of counters 1, 2 are connected to each other, creating the input of the shaper - the input of supplying a continuous periodic sequence of pulses C from the output of the external generator.

The clock input of the SW flip-flop 7 creates the start pulse supply input (ag). The output of flip-flop 7 is connected to the input of element 10. The clock input of flip-flop 4 is connected to the output of element 16. The direct output of flip-flop 4 is connected to the input of element 10. The inverse output of flip-flop 4 is connected to its input 0.

The former works in the following sequence. The presence of a circuit consisting of a series-connected resistor 5 and a capacitor 6 connected to the bus of the supply voltage ZHE, when the power source is turned on for a certain period of time, forms a logical zero level at the inputs of elements 8 and 9, ensuring the formation of a logical zero level at their outputs, given with the inputs K of the asynchronous installation in the zero state, respectively, of triggers and counters 1, 2. After the end of the transient process associated with turning on the power source, the triggers and counters go to the zero state, forming a logic zero level, respectively, on the direct outputs of the triggers and on the overflow outputs Ра counters, which leads to the formation of a logical zero level at the output of element 10, connected to the input of element I 9, which confirms (blocks) the logical zero level at its output, and after the transition process associated with the charge of capacitor b, which provides a logical zero level at inputs K of asynchronous setting of counters in the zero state. Since the mode of asynchronous setting of the counters to the zero state has priority relative to all the last modes, as long as the level of logical zero is maintained at the input of element 9 (and therefore at its output), the zero state of the counters will remain unchanged.

During the arrival of the start pulse (eiag) to the clock input C of the Y-trigger 7 along its edge, the trigger goes to the single state (0-1), forming a logical unit level at the output of the OR element 10, and therefore at the input and output of the AND element 9, which ensures the level of a logical unit at the K inputs of counters 1, 2, removing blocking. The zero value of the signal from the overflow output Ra. of counter 1 enters the synchronous parallel loading permission inputs of G. counters 1, 2, preparing them to receive information from the Yuo-Yuz inputs.

During the onset of the first (after the end of the transient process associated with the removal of blocking) clock pulse C along its edge, counters 1, 2 are loaded in parallel with the values of the signals applied to the corresponding inputs Хуо-ХУоз, i.e. counter 1 goes into the rzb2bibo state, and counter 2 goes into the dzadga:do state. The zero state of counter Z and trigger 4 will remain unchanged. As a result of these transitions, a single value is formed at the first, second, fourth and fifth outputs, at the GI inputs of counters 1, 2 and at the Ro input of counter 1, as a result of which the first counter goes into the counting mode, and the second into the saving mode. The saving mode of counter Z and trigger 4 will remain unchanged. During the entry of the second (after the end of the transient process associated with the release of blocking) and subsequent clock pulses, the content of counter 1 will decrease, and the state of counters 2, C and flip-flop 4 will remain unchanged (equal to 0), until the content of the counter 1 will not become equal to 0. As a result, counter 1 goes into saving mode, and counter 2 into counting mode. During the arrival of the next and subsequent clock pulses, the content of counter 2 will decrease, and the state of counters 1, З and trigger 4 will remain unchanged (equal to 0) until the content of counter 2 becomes equal to 0. As a result of this transition, the counter З goes into the rorirgrz state and the second U-trigger to the single state. During the arrival of the next and subsequent clock pulses, a single value is formed on the third and sixth outputs, until the content of the counters and flip-flops becomes equal to 0. As a result, a logical 0 level will be formed at all inputs of the OR element 10 and its output, determining the logical level of zero at the input and output of element | 9, which will lead to the blocking of the zero state of the counters, and therefore to the termination of the generation process. With the arrival of the next start pulse, all processes are repeated.

Thus, after the end of the transient process associated with the removal of blocking, during the input C of the generator of a periodic sequence of pulses with a period T, symmetrical single coded series of pulses with programmable parameters that are multiples of the period of a continuous periodic sequence of supplied pulses are generated at the outputs of the generator to its input from the output of the quartz generator.

In fig. 2 shows the transition graph of the shaper consisting of four rings (the upper ring is the transition graph of the second U-trigger, the next ring is counter 3, the next ring is the transition graph of counter 2, the lower ring is the transition graph of counter 1) with a common vertex corresponding to zero states of the counters and the second Y-trigger, and figure Z shows diagrams explaining the operation of the shaper for the configuration option rzb2bibo-0011, dzagazdo-0010, rzrgriro--0011.

Unlike the known device for forming symmetrical single code series of pulses with programmable parameters, multiples of the period of a continuous periodic sequence of pulses fed to its input from the output of a quartz generator, expands the functionality and scope of use of the shaper.

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