TWM581284U - Chip resistor with bifacial series resistors - Google Patents

Abstract

A chip resistor includes a ceramic substrate and two resistance layers respectively deposited on two surfaces of the ceramic substrate. The two resistance layers are electrically series connected. Such a chip resistor may apply to thick high impedance product.

Description

Series double-sided chip resistor

The present invention relates to a chip resistor, and more particularly to a chip resistor in the form of a series double layer.

R-Chip is a passive component whose main function is to reduce voltage and limit current. Conventional resistive wafers use a ceramic substrate of alumina crystallized, printed with a thick metal film conductor, and coated with a uranium-protected wafer on the outer layer. Due to its small size and high power, the chip resistor is suitable for 3C products.

The present invention provides a wafer resistor having a series resistance disposed on two opposing surfaces of the wafer to increase the flexibility of the resistor design.

The present invention provides a chip resistor having a series resistance disposed on two opposite surfaces of a wafer, suitable for thick film high resistance wafer resistance, and applicable to dividers, hybrids, X-rays. Equipment, low signal detection circuit, amplification circuit, high impedance quartz amplifier or other test equipment.

According to the above, a chip resistor includes: a body having an opposite first surface and a second surface; and a plurality of sidewalls interposed between the first surface and the second surface; a first end electrode and a second end electrode are separately disposed on the first surface; a first resistance layer is disposed on the first surface, the first resistance layer has a long curved shape and has two end points a first resistance pattern, wherein any one end of the first resistance pattern is connected to the first terminal electrode, and the other end is connected to the second end electrode; a first protective layer covers the first resistance layer; a first conductive pad is disposed on the body for electrically connecting a circuit board of the outside; a second conductive pad and a third conductive pad are separately disposed on the second surface; a second resistance layer is disposed on the On the second surface, the second resistive layer has a long curved shape and has a second resistance pattern of two ends, wherein any one end of the second resistive pattern is connected to the second conductive pad, and the other The end surface is connected to the third conductive pad; a second protective layer covers the second resistance layer; and a first side guide is disposed on one of the side walls, the first side guide electrically connecting the second end An electrode and the second conductive pad.

In one embodiment, the chip resistor further includes a second side guide disposed on one of the sidewalls, wherein the first conductive pad is disposed on the second surface, and the second side guide is structurally connected to the first An end electrode and the first conductive pad, and the second side guide electrically connects the first terminal electrode and the first conductive pad.

In one embodiment, the first side guide and the second side guide are disposed on the same or different side walls.

In one embodiment, the second protective layer covers the second conductive pad, covering or exposing a portion of the second surface between the second conductive pad and the third conductive pad, and exposing the third conductive pad.

In one embodiment, the chip resistor further includes a fourth conductive pad disposed on the second surface, the fourth conductive pad structure is connected to the third conductive pad exposed by the second protective layer and electrically connected to the third Conductive pad.

In one embodiment, the second protective layer is interposed between the fourth conductive pad and the first side guide to electrically insulate the fourth conductive pad and the first side guide.

In one embodiment, the wafer resistor further includes a third protective layer covering the first side guide.

In one embodiment, the impedance of the wafer resistor ranges from 1 G to 2 G ohms.

In one embodiment, the first resistive layer and the second resistive layer are in a series relationship.

In one embodiment, the body is a ceramic substrate.

2, 4, 6, 8‧‧‧ chip resistance

12‧‧‧ first surface

14‧‧‧ second surface

16‧‧‧ side wall

22, 24‧‧‧ terminal electrode

21‧‧‧First resistance layer

29‧‧‧First protective layer

41‧‧‧second resistance layer

42‧‧‧First conductive pad

44‧‧‧Second conductive pad

46‧‧‧ Third conductive pad

48‧‧‧fourth conductive pad

49‧‧‧Second protective layer

62, 64‧‧‧ side guides

69‧‧‧ third protective layer

FIG. 1 is a top perspective view of the first embodiment of the chip resistor of the present invention.

2 is a bottom perspective view of the first embodiment of the wafer resistor of the present invention.

FIG. 3 is a top perspective view showing a partial structure of the first embodiment of the chip resistor of the present invention.

4 is a bottom perspective view showing the partial structure of the first embodiment of the wafer resistor of the present invention.

FIG. 5 is a bottom perspective view of the second embodiment of the wafer resistor of the present invention.

FIG. 6 is a bottom perspective view of the third embodiment of the wafer resistor of the present invention.

FIG. 7 is a bottom perspective view of the fourth embodiment of the wafer resistor of the present invention.

1 and 2 are respectively a top view and a bottom perspective view of the first embodiment of the chip resistor of the present invention. 3 and FIG. 4 are respectively a top plan view and a bottom perspective view showing a partial structure of the first embodiment of the chip resistor of the present invention. Referring to FIGS. 1 to 4, the chip resistor 2 has a quadrilateral type, including a body having a first The surface 12 and the second surface 14, and the four side walls 16 connect the first surface 12 and the second surface 14. In the first embodiment, the first surface 12 is provided with a terminal electrode 22, a terminal electrode 24, a first resistance layer 21 and a first protective layer 29. Next, the first resistive layer 21 has a long curved shape and has a first resistance pattern of two end points, wherein the two end points are respectively structurally adjacent to the spaced apart end electrodes 22 and the terminal electrodes 24, and are respectively electrically connected Terminal electrode 22 and terminal electrode 24. Further, the first protective layer 29 covers the entire first resistance layer 21, and thus, the terminal electrode 22, the terminal electrode 24, and a portion of the first surface 12 are exposed. Next, a side guide member 62 and a side guide member 64 are disposed on one side wall 16, wherein the end electrode 22 and the side guide member 62 are structurally adjacent and electrically connected, and the end electrode 24 and the side guide member 64 are structurally adjacent. And electrical connection, but the case is not limited to this aspect.

1 to 4, the first conductive pad 42, the second conductive pad 44, the third conductive pad 46 and the second resistance layer 41 are disposed on the second surface 14, wherein the first conductive pad 42 and the side conductive member 62 Structurally adjacent and electrically connected, the second conductive pad 44 and the side guides 64 (first side guides) are structurally adjacent and electrically connected. Secondly, the second resistive layer 41 has a second resistance pattern having a long curved shape and having two end points, wherein the two end points are respectively structurally adjacent to the second conductive pad 44 and the third conductive pad 46 which are disposed apart from each other. And electrically connecting the second conductive pad 44 and the third conductive pad 46, respectively. Furthermore, the second protective layer 49 covers the entire second resistive layer 41, the second conductive pad 44, and the second surface 14 of the portion between the second conductive pad 44 and the third conductive pad 46, thus, first The conductive pad 42 and the third conductive pad 46 are not covered by the second protective layer 49. Next, the fourth conductive pad 48 is disposed on the third conductive pad 46 and overlaps the portion of the second protective layer 49, wherein the fourth conductive pad 48 and the third conductive pad 46 are structurally overlapped and electrically connected. In addition, the third conductive layer 69 may be covered on the side guiding member 64, wherein the third protective layer 69 extends to the second protective layer 49, and the third protective layer 69 electrically isolates the side guiding member 64 and the fourth conductive pad 48. . Alternatively, the length of the fourth conductive pad 48 can be reduced to ensure electrical isolation from the side guides 64.

1 to 4, in an embodiment, in terms of a current path, current is entered by the terminal electrode 22, sequentially passing through the first resistive layer 21, the terminal electrode 24, the side guide 64, and the second conductive pad. 44. The second resistance layer 41 reaches the third conductive pad 46. Therefore, the first resistance layer 21 and the second resistance layer 41 are in a series relationship. Moreover, the first conductive pad 42 and the fourth conductive pad 48 can respectively serve as conductive pads for external circuit boards (not shown). Therefore, by the electrical connection of the first conductive pad 42, the side guide 62 and the terminal electrode 22, and the electrical connection of the fourth conductive pad 48 and the third conductive pad 46, current can be entered by the first conductive pad 42 through the above After the current path, it is transmitted to the outside by the fourth conductive pad 48.

According to the above, one of the structural features of the chip resistor is that a relatively large two surfaces of the body are respectively provided with a resistance layer, and the two resistance layers form a series relationship by the terminal electrode, the side guide and the conductive pad. Therefore, the chip resistance of this case can be applied to a thick film high resistance wafer resistor, and the extended resistance range can reach 1G~2G ohm. Secondly, at least one of the four side walls between the relatively large two surfaces may be provided with at least one side guide which is bridged by the side guides and electrically connects the resistive layers on the two surfaces. Furthermore, one of the relatively large two surfaces of the body of the chip resistor 2 may be provided with a conductive pad as a solder pad for fixing to an external circuit board and electrically connecting the external circuit board, wherein the conductive pads are electrically connected by the side guides. The terminal electrode on the other surface. It can be understood that the pattern, size and position of the terminal electrode, the resistance layer, the side guide and the conductive pad which can perform the above functions can be changed as needed, and are not limited to those shown in FIGS. 1 to 4 . Secondly, the conductive pads as solder pads are electrically insulated from the side conductors forming series resistors in series to prevent current from going directly through the shortest path without flowing through the resistive layer. Therefore, the conductive pad and the side guide can be electrically insulated by the protective layer or by adjusting the size of the conductive pad.

Further, there are various materials and structures for performing the above functions. For example, the body of the chip resistor can be a ceramic substrate; the terminal electrodes, the resistive layer and the conductive pads on the two surfaces can be used. The same or different conductive pastes are printed and then sintered and cured; the side guides may be formed on the side walls by vapor deposition of a conductive material; and the protective layer may be made of an insulating material such as an epoxy resin or a glass resin.

FIG. 5 is a bottom perspective view of the second embodiment of the wafer resistor of the present invention. Referring to FIG. 2 and FIG. 5 simultaneously, the wafer resistor 4 differs from the wafer resistor 2 of the first embodiment only in that the wafer resistor 4 omits the fourth conductive pad 48 of the wafer resistor 2, so that on the second surface 14, The second protective layer 49 exposes the first conductive pad 42 and the third conductive pad 46. Therefore, the third conductive pad 46 is used for both fixed and electrical connection with an external circuit board (not shown).

FIG. 6 is a bottom perspective view of the third embodiment of the wafer resistor of the present invention. Referring to FIG. 2 and FIG. 6 at the same time, the wafer resistor 6 differs from the wafer resistor 2 of the first embodiment only in that the wafer resistor 6 omits the difference in the size of the fourth conductive pad 48 and the second protective layer 49 of the wafer resistor 2. . The second protective layer 49 of the wafer resistor 6 is smaller, thus exposing a portion of the second surface 14.

FIG. 7 is a bottom perspective view of the fourth embodiment of the wafer resistor of the present invention. Referring to FIG. 2 and FIG. 7 simultaneously, the wafer resistor 8 differs from the wafer resistor 2 of the first embodiment only in that the side guides of the wafer resistor 8 are respectively disposed on different sidewalls and the wafer resistor 8 omits the wafer resistor 2 The fourth conductive pad 48. As shown in FIG. 7, the side guide 64 of the wafer resistor 8 is on one side wall, and the side guides (not shown) electrically connecting the first conductive pad 42 are disposed on the side wall different from the side guide 64. On the other side walls.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this new type is subject to the definition of the scope of the patent application.

Claims (10)

A chip resistor comprising: a body having a first surface and a second surface opposite to each other and a plurality of sidewalls between the first surface and the second surface; a first end electrode and a first a two-terminal electrode is disposed on the first surface separately; a first resistance layer is disposed on the first surface, the first resistance layer has a long curved shape and has a first resistance pattern of two end points, wherein One end of the first resistance pattern is connected to the first terminal electrode, and the other end is connected to the second terminal electrode; a first protective layer covers the first resistance layer; a first conductive pad is disposed on a second circuit pad and a third conductive pad are separately disposed on the second surface; a second resistance layer is disposed on the second surface, the second surface is disposed on the second surface The second resistive layer has a long curved shape and has a second resistance pattern of two end points, wherein any one end of the second resistive pattern is connected to the second conductive pad, and the other end point is connected to the third conductive pad a conductive pad; a second protective layer covering the second Layer; and a first side guide member disposed on one of the plurality of side walls, the first side guide member is electrically connected to the second terminal electrode and the second conductive pads. The chip resistor of claim 1, further comprising a second side guide disposed on one of the sidewalls, wherein the first conductive pad is disposed on the second surface, and the second side conductor is structurally Connecting the first terminal electrode and the first conductive pad, and the second side guide electrically connects the first terminal electrode and the first conductive pad. The wafer resistor of claim 2, wherein the first side guide and the second side guide are disposed on the same or different side walls. The chip resistor of claim 1, wherein the second protective layer covers the second conductive pad, covering or exposing a portion of the second surface between the second conductive pad and the third conductive pad, and exposing The third conductive pad is removed. The chip resistor of claim 1, further comprising a fourth conductive pad disposed on the second surface, the fourth conductive pad structure connecting the third conductive pad exposed by the second protective layer and electrically connected The third conductive pad. The wafer resistor of claim 5, wherein the second protective layer is interposed between the fourth conductive pad and the first side via to electrically insulate the fourth conductive pad and the first side via. The chip resistor of claim 1, further comprising a third protective layer covering the first side guide. The chip resistor of claim 1, wherein an impedance of the chip resistor ranges from 1 G to 2 G ohms. The chip resistor of claim 1, wherein the first resistive layer and the second resistive layer are in a series relationship. The wafer resistor of claim 1, wherein the body is a ceramic substrate.