TWM563659U - Chip on film package structure - Google Patents

Abstract

A chip on film package structure including a flexible circuit carrier, a chip, and a solder mask is provided. The flexible circuit carrier includes a flexible substrate and a circuit layer. The flexible substrate has a chip bonding area. The circuit layer is disposed on the flexible substrate. The circuit layer includes a plurality of inner leads, a plurality of circuits, and a plurality of outer leads. The inner leads are disposed corresponding to the chip bonding area. The circuits surround the inner leads. The circuits are disposed between the inner leads and the outer leads. The maximum thickness of the inner leads is smaller than the maximum thickness of the circuits. The chip is disposed on the flexible circuit carrier in the chip bonding area and electrically connected to the inner leads. The solder mask is disposed on the circuit layer and exposes the inner leads and outer leads.

Description

Thin film flip chip packaging structure

This new creation is about a packaging structure, and particularly about a thin film flip chip packaging structure.

With the continuous evolution of electronic technology, the integrated circuit components produced are lighter, thinner, shorter, and more complex in function, high I / O count, high frequency, and diversified. Under this development trend, thin film on chip (COF) packaging meets its packaging needs. Thin film flip-chip packaging is a packaging technology that uses conductive bumps to join the chip to the pins on the flexible circuit carrier board. Compared with the traditional printed circuit board, the thin film flip chip package directly installs the conductive circuit and its electronic components on the flexible substrate, so that the package structure can achieve the purpose of lighter, thinner, shorter and flexible.

In the current circuit structure of a flexible circuit carrier board, peeling may occur between the flexible substrate and the conductive circuit due to stress, especially between the inner leads of the conductive circuit and the flexible substrate Junction. Therefore, how to reduce the possibility of peeling of the flexible substrate and the conductive circuit to further improve the yield and product reliability of the thin-film flip-chip packaging structure has become a problem that is urgently to be solved.

The novel creation provides a thin film flip chip packaging structure, which has better yield and reliability.

The thin-film flip-chip packaging structure created by the novel includes a flexible circuit carrier board, a chip and a solder mask. The flexible circuit carrier includes a flexible substrate and a circuit layer. The flexible substrate has a wafer bonding area. The circuit layer is disposed on the flexible substrate. The circuit layer includes multiple inner pins, multiple lines, and multiple outer pins. The multiple inner pins correspond to the wafer bonding area configuration. Multiple lines surround multiple inner pins. Multiple lines are located between multiple outer pins and multiple inner pins, and the maximum thickness of the inner pins is less than the maximum thickness of the line. The chip is disposed on the flexible circuit carrier board and is located in the chip bonding area, and the chip is electrically connected to a plurality of inner pins. The solder mask layer is located on the circuit layer and exposes multiple inner pins and multiple outer pins.

In an embodiment of the present invention, the above-mentioned circuit structure has a Young's modulus greater than that of the flexible substrate.

In an embodiment of the invention, the ratio of the maximum thickness of the inner lead to the maximum thickness of the circuit is between 20% and 90%.

In an embodiment of the invention, the circuit layer is a single mold layer.

In an embodiment of the invention, the above-mentioned thin-film flip-chip packaging structure further includes a soldering layer. The soldering layer covers the circuit layer, and the material of the soldering layer is different from the material of the circuit layer.

In an embodiment of the invention, the above-mentioned thin-film flip-chip packaging structure further includes a plurality of connection terminals. The connection terminal is located between the chip and the flexible circuit carrier board, and the chip is electrically connected to the circuit layer through a plurality of connection terminals.

In an embodiment of the invention, the circuit described above has a first upper surface, the inner pin has a second upper surface, and the first upper surface and the second upper surface are not coplanar.

In an embodiment of the present invention, the maximum thickness of the external pin is smaller than the maximum thickness of the circuit.

In an embodiment of the present invention, the above-mentioned thin film flip chip packaging structure further includes a packaging layer. The packaging layer is at least located between the flexible circuit carrier and the chip, and covers the inner leads.

In an embodiment of the invention, the above-mentioned encapsulation layer further covers the chip.

Based on the above, in the thin-film flip-chip packaging structure created by the present invention, the chip is electrically connected to the inner pins of the circuit layer, and the maximum thickness of the inner pins is less than the maximum thickness of the circuit. Therefore, in the manufacturing process or finished product of the thin film flip chip packaging structure, the possibility of peeling of the circuit layer and the flexible substrate can be reduced. In this way, the thin film flip chip packaging structure can have better yield and reliability.

In order to make the above-mentioned features and advantages of the creation of the new model more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the attached drawings.

FIGS. 1A to 1G are schematic cross-sectional views of a method for manufacturing a thin film flip-chip package structure according to the first embodiment of the present invention. FIG. 1H is a schematic top view of a thin-film flip-chip packaging structure according to the first embodiment of the present invention.

The manufacturing method of the thin film flip-chip packaging structure 100 of this embodiment includes the following steps. First, referring to FIG. 1A, a flexible substrate 120 is provided. The material of the flexible substrate 120 is, for example, polyimide (PI) or other flexible materials, so that the thin film flip-chip packaging structure 100 with the flexible substrate 120 (shown in FIG. 1G or 1H) It can be correspondingly flexed or bent when subjected to external force.

1A, a conductive layer 130a is formed on the flexible substrate 120. In general, the conductive layer 130a can be formed on the surface 120a of the flexible substrate 120 by other suitable processes such as a deposition process and / or an electroplating process. In addition, based on the consideration of conductivity, the conductive layer 130a generally uses a metal material, but the present invention is not limited thereto. In other embodiments, the conductive layer 130a may also use alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, other suitable conductive materials, or stacked layers of metal materials and other conductive materials .

Next, referring to FIG. 1B, after the conductive layer 130a is formed on the flexible substrate 120, the conductive layer 130a covered on the surface 120a of the flexible substrate 120 (shown in FIG. FIG. 1A) is patterned to form a patterned conductive layer 130b. The patterned conductive layer 130b has an opening 130c to expose a portion of the flexible substrate 120. In the present embodiment, the patterned conductive layer 130b is, for example, strip-shaped, but the present invention is not limited thereto.

Next, referring to FIG. 1C, after forming the patterned conductive layer 130b, a portion of the patterned conductive layer 130b may be thinned to form the circuit layer 130. Specifically, a part of the patterned conductive layer 130b (shown in FIG. 1B) located near the opening 130c can be removed by an etching process to form the inner pin 131 of the circuit layer 130. In addition, the remaining portion of the patterned conductive layer 130 b that is not thinned may constitute the wiring 132 of the wiring layer 130. In other words, the lines 132 may surround the inner pins 131, and the maximum thickness 131h of the inner pins 131 is smaller than the maximum thickness 132h of the line 132.

In this embodiment, since the inner lead 131 is formed after a thinning process, the first upper surface 131a of the inner lead 131 and the second upper surface 132a of the circuit 132 are connected but not coplanar, The first lower surface 131b of the inner pin 131 is connected to the second lower surface 132b of the circuit 132 and is coplanar.

In this embodiment, a part of the patterned conductive layer 130 b located near the side 120 b of the flexible substrate 120 may be thinned to form the outer pin 133 of the circuit layer 130. In other words, the lines 132 may be located between the outer pins 133 and the inner pins 131, and the maximum thickness 133h of the outer pins 133 is smaller than the maximum thickness 132h of the line 132. In this embodiment, the maximum thickness 133h of the outer lead 133 is substantially the same as the maximum thickness 131h of the inner lead 131, but the invention is not limited thereto. In addition, since the outer pin 133 is formed after a thinning process, the third upper surface 133a of the outer pin 133 and the second upper surface 132a of the circuit 132 are connected but not coplanar, while The third lower surface 133b of 133 is connected to the second lower surface 132b of the circuit 132 and is coplanar.

In other embodiments, the external pin 133 may not be thinned. In other words, the maximum thickness 133h of the outer lead 133 and the maximum thickness 132h of the line 132 may be substantially the same.

In this embodiment, the Young's modulus of the circuit layer 130 is greater than the Young's modulus of the flexible substrate 120, and the maximum thickness of the circuit layer 130 is 132h (in this embodiment, it is the maximum of the circuit 132) Thickness 132h) is smaller than the thickness 120h of the flexible substrate 120. In this way, the thin-film flip-chip packaging structure 100 (shown in FIG. 1G or FIG. 1H) composed of the flexible substrate 120 and the circuit layer 130 can have better flexibility.

Next, please refer to FIG. 1D. In this embodiment, after the inner pin 131, the circuit 132 and the outer pin 133 of the circuit layer 130 are formed, the soldering layer 140 may be formed on the circuit layer 130. The soldering layer 140 can be formed by an electroplating process. That is to say, the soldering layer 140 may conformally cover the circuit layer 130. Generally speaking, the material of the soldering layer 140 is different from the material of the circuit layer 130, and compared with the material of the circuit layer 130, the material of the soldering layer 140 can be applied to the solder formed later. For example, the material of the circuit layer 130 may include copper, and the material of the soldering layer 140 may include tin, but the invention is not limited thereto.

In other embodiments, the soldering layer 140 similar to FIG. 1D may not be provided.

Next, referring to FIG. 1E, a solder resist layer 150 is formed on the circuit layer 130. The solder resist layer 150 covers the circuit 132 of the circuit layer 130 and exposes the inner pin 131 and the outer pin 133 of the circuit layer 130. The solder resist layer 150 has an opening, and the opening exposes the inner pins 131 of the circuit layer 130 and a portion of the flexible substrate 120 to define the wafer bonding area 121.

Next, referring to FIG. 1F, a wafer 170 is disposed on the circuit layer 130. The chip 170 is disposed in the chip bonding area 121 by flip-chip bonding, and the chip 170 is electrically connected to the inner pins 131. In detail, in this embodiment, a plurality of connection terminals 160 may be formed on the inner pins 131 first. The connection terminal 160 is, for example, a solder ball, but the invention is not limited thereto. Next, the wafer 170 is placed on the connection terminal 160 in such a manner that the active surface 171 of the wafer 170 faces the circuit layer 130, and the connection terminal 160 is melted and connected to the active surface 171 of the wafer 170 by pressing and heating Connected.

Generally speaking, when there is stress on the composite material, it is easy to cause cracks between the interfaces of the materials. The above-mentioned stresses may be external stresses generated by externally applied pressure, or internal stresses generated internally due to deflection, different expansion coefficients, or other possible reasons. That is to say, when the chip 170 and the circuit layer 130 are electrically connected by means of pressure and heating, the flexible substrate 120 and the circuit layer 130 or the circuit layer may be caused due to stress Within 130, cracks occurred and peeling occurred. In this embodiment, since the inner pin 131 is formed after the thinning process, the inner pin 131 of this embodiment has better stress tolerance than the inner pin without the thinning process . In this way, when the chip 170 is disposed on the inner pins 131, the peeling between the flexible substrate 120 and the circuit layer 130, or the internal breakage of the inner pins 131 can be reduced to make the thin film flip chip package structure 100 has better yield and reliability.

Next, referring to FIG. 1G, after the wafer 170 is disposed, the encapsulation layer 180 may be formed on the flexible substrate 120. The packaging layer 180 is located at least between the flexible circuit carrier 110 and the chip 170 to cover the inner lead 131, the connection terminal 160 and the active surface 171 of the chip 170.

After the above process, the fabrication of the thin film flip-chip packaging structure 100 of this embodiment can be substantially completed. Please refer to FIG. 1G and FIG. 1H at the same time. The above-mentioned thin film flip-chip packaging structure 100 includes a flexible circuit carrier 110, a chip 170, and a solder mask 150. The flexible circuit carrier 110 includes a flexible substrate 120 and a circuit layer 130. The flexible substrate 120 has a wafer bonding area 121. The circuit layer 130 is disposed on the flexible substrate 120. The circuit layer 130 includes a plurality of inner pins 131, a plurality of lines 132, and a plurality of outer pins 133. The plurality of inner pins 131 are arranged corresponding to the wafer bonding area 121. A plurality of lines 132 surround a plurality of inner pins 131. The multiple wires 132 are located between the multiple outer pins 133 and the multiple inner pins 131, and the maximum thickness 131h of the inner pins 131 is smaller than the maximum thickness 132h of the line 132. The chip 170 is disposed on the flexible circuit carrier 110 and is located in the chip bonding area 121, and the chip 170 is electrically connected to the plurality of inner pins 131. The solder resist layer 150 is located on the circuit layer 130 and exposes a plurality of inner pins 131 and a plurality of outer pins 133.

In this embodiment, the ratio of the maximum thickness 131h of the inner lead 131 to the maximum thickness 132h of the line 132 is between 20% and 90%. In this way, the inner pin 131 can have better conductivity and stress tolerance.

In this embodiment, the encapsulation layer 180 exposes the wafer back 172 of the wafer 170, but the invention is not limited thereto.

2A-2B are schematic cross-sectional views of a part of a method for manufacturing a thin film flip chip package structure according to a second embodiment of the present invention. The thin-film flip-chip package structure of this embodiment is similar in structure to the thin-film flip-chip package structure 100 of the foregoing embodiment, and the main difference lies in the manufacturing method.

Referring to FIG. 2A, in this embodiment, a patterned first conductive layer 230a may be formed on the flexible substrate 120.

Next, referring to FIG. 2B, after forming the patterned first conductive layer 230a, plating, deposition, or other suitable methods may be used to form contact with the first conductive layer 230a on a portion of the first conductive layer 230a的 second conductive layer 230b. In this way, the first conductive layer 230a and the second conductive layer 230b may constitute the circuit 132 of the circuit layer 130, and the remaining first conductive layer 230a not in contact with the second conductive layer 230b may constitute the inner pin of the circuit layer 130 131 与 外 针 133.

Then, a manufacturing method similar to that shown in FIGS. 1D to 1F can be continued to complete the thin film flip-chip package structure of this embodiment.

FIG. 3 is a schematic cross-sectional view of a thin-film flip-chip packaging structure according to a third embodiment of the invention. The thin-film flip-chip packaging structure 300 of this embodiment is similar to the thin-film flip-chip packaging structure 100 of the previous embodiment, the main difference is that the packaging layer 380 is located between the flexible circuit carrier 110 and the chip 170 to cover the inner leads 131, the connection terminal 160 and the active surface 171 of the wafer 170, and further covers the back surface 172 of the wafer 170.

In summary, in the thin-film flip-chip package structure created by the novel, the chip is electrically connected to the inner pins of the circuit layer by flip-chip bonding, and the maximum thickness of the inner pins is less than the maximum thickness of the circuit. Therefore, in the manufacturing process or finished product of the thin film flip chip packaging structure, the possibility of peeling of the circuit layer and the flexible substrate can be reduced. In this way, the thin film flip chip packaging structure can have better yield and reliability.

Although the new creation has been disclosed as above with examples, it is not intended to limit the creation of the new creation. Anyone with ordinary knowledge in the technical field of the subject can make some changes and without departing from the spirit and scope of the new creation. Retouch, so the scope of protection of this new creation shall be subject to the scope defined in the appended patent application.

100、300‧‧‧thin film flip chip packaging structure
110‧‧‧ Flexible circuit carrier board
120‧‧‧Flexible substrate
120a‧‧‧Surface
120b‧‧‧Side
120h‧‧‧Thickness of flexible substrate
121‧‧‧ Wafer bonding area
130‧‧‧ line layer
130a‧‧‧conductive layer
130b‧‧‧patterned conductive layer
130c‧‧‧ opening
131‧‧‧Inner pin
131h‧‧‧The maximum thickness of the inner lead
131a‧‧‧First upper surface
131b‧‧‧First lower surface
132‧‧‧ Line
132h‧‧‧Maximum thickness of the line
132a‧‧‧Second upper surface
132b‧‧‧Second lower surface
133‧‧‧External pin
133h‧‧‧Maximum thickness of external pin
133a‧‧‧third upper surface
133b‧‧‧third lower surface
140‧‧‧Welding layer
150‧‧‧Soldering layer
151‧‧‧ opening
160‧‧‧Connecting terminal
170‧‧‧chip
171‧‧‧ active surface
172‧‧‧chip back
180, 380‧‧‧ encapsulation layer
230a‧‧‧first conductive layer
230b‧‧‧Second conductive layer

FIGS. 1A to 1G are schematic cross-sectional views of a method for manufacturing a thin film flip-chip package structure according to the first embodiment of the present invention. FIG. 1H is a schematic top view of a thin-film flip-chip packaging structure according to the first embodiment of the present invention. 2A-2B are schematic cross-sectional views of a part of a method for manufacturing a thin film flip chip package structure according to a second embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a thin-film flip-chip packaging structure according to a third embodiment of the invention.

Claims (10)

A thin film flip-chip packaging structure includes: a flexible circuit carrier board, including: a flexible substrate with a wafer bonding area; and a circuit layer disposed on the flexible substrate, wherein the circuit layer includes a plurality of An inner pin, a plurality of lines, and a plurality of outer pins, the plurality of inner pins corresponding to the die bonding area configuration, the plurality of lines surround the plurality of inner pins, and the plurality of lines are located in the Between a plurality of outer pins and the plurality of inner pins, and the maximum thickness of the plurality of inner pins is smaller than the maximum thickness of the plurality of circuits; the chip is disposed on the flexible circuit carrier board And located in the bonding area of the chip, and the chip is electrically connected to the plurality of inner pins; and a solder resist layer is positioned on the circuit layer, and exposes the plurality of inner pins and the Multiple external pins. The thin film flip chip packaging structure as described in item 1 of the patent application range, wherein the Young's modulus of the circuit structure is greater than the Young's modulus of the flexible substrate. As in the thin-film flip-chip packaging structure described in item 1 of the patent application range, the ratio of the maximum thickness of the plurality of inner leads to the maximum thickness of the plurality of circuits is between 20% and 90%. The thin film flip-chip packaging structure as described in item 1 of the patent scope, wherein the circuit layer is a single mold layer. The thin-film flip-chip packaging structure as described in item 1 of the patent application scope further includes: a soldering layer covering the circuit layer, and the material of the soldering layer is different from the material of the circuit layer. The thin-film flip-chip packaging structure as described in item 1 of the patent application scope further includes: a plurality of connection terminals between the chip and the flexible circuit carrier board, and the chip passes the plurality of The connection terminal is electrically connected to the circuit layer. The thin film flip-chip packaging structure as described in item 1 of the patent application scope, wherein the inner leads have a first upper surface, a plurality of wires have a second upper surface, a plurality of the first upper surface and all The second upper surface is not coplanar. The thin film flip-chip packaging structure as described in item 1 of the patent application range, wherein the maximum thickness of the plurality of external leads is smaller than the maximum thickness of the plurality of circuits. The thin film flip-chip packaging structure as described in item 1 of the scope of the patent application further includes: a packaging layer located at least between the flexible circuit carrier and the chip and covering the plurality of inner leads. The thin film flip chip packaging structure as described in item 9 of the patent application range, wherein the packaging layer further covers the wafer.