TWM538163U

TWM538163U - Test device

Info

Publication number: TWM538163U
Application number: TW105217109U
Authority: TW
Inventors: 楊燾境; 黃國峰; 粘為裕
Original assignee: 日月光半導體製造股份有限公司
Priority date: 2016-11-09
Filing date: 2016-11-09
Publication date: 2017-03-11
Also published as: CN206531926U

Abstract

A test device includes a first socket, a second socket and a circuit board. The first socket has a plurality of first pins. The second socket has a plurality of second pins. The circuit board is located between and contacts the first pins and the second pins.

Description

Test device

本新型係關於一種測試裝置，且更特定言之，係關於一種具有雙層測試座之測試裝置。The present invention relates to a test device and, more particularly, to a test device having a double test stand.

習知電子裝置之製程中，至少一晶片係附著或電性連接至一模組電路板(Module PCB)上，以形成一模組(Module)，而可執行特定功能。該模組在出廠前或進到下一個工作站前，必須經過一測試步驟，以確定其良率。在模組廠之測試實務中，一模組測試電路板(Module Test Evaluation Board (EVB))係用以電性連接該模組電路板(Module PCB)以達到測試該模組(Module)之目的。而且，在該測試過程中，該模組測試電路板(Module Test Evaluation Board (EVB))需搭配一習用測試座(Socket)，方能進行測試。然而，該模組測試電路板(Module Test Evaluation Board (EVB))及該習用測試座(Socket)並無法用以測試該晶片。亦即，上述測試方式僅能測試該模組(Module)，無法單獨測試該晶片或該模組電路板(Module PCB)。若是該模組(Module)沒有通過測試（亦即：測試結果為失敗），則無法判斷是該晶片的問題，或是該模組電路板(Module PCB)的問題，或是該晶片與該模組電路板(Module PCB)間電性連接的問題。然而，若要單獨測試該模組上的晶片，則需另外開發一塊晶片測試電路板(Chip Test Evaluation Board (EVB))及搭配不同測試座方能進行測試。惟，另外開發該晶片測試電路板(Chip Test Evaluation Board (EVB))及測試座將使得整體測試成本大幅增加。因此，有必要提供一創新且具進步性之測試裝置，以解決上述問題。In the process of the conventional electronic device, at least one of the chips is attached or electrically connected to a module PCB to form a module, and a specific function can be performed. The module must undergo a test step to determine its yield before it leaves the factory or before moving on to the next workstation. In the testing practice of the module factory, a Module Test Evaluation Board (EVB) is used to electrically connect the module PCB to achieve the purpose of testing the module. . Moreover, during the test, the Module Test Evaluation Board (EVB) needs to be matched with a conventional test socket (Socket) for testing. However, the Module Test Evaluation Board (EVB) and the conventional test socket (Socket) cannot be used to test the wafer. That is to say, the above test method can only test the module, and the chip or the module PCB cannot be tested separately. If the module fails the test (ie, the test result is a failure), it is impossible to determine whether the chip is a problem, or the module PCB (Module PCB) problem, or the chip and the die The problem of electrical connection between the group boards (Module PCB). However, if you want to test the chip on the module separately, you need to develop another Chip Test Evaluation Board (EVB) and test it with different test sockets. However, the additional development of the Chip Test Evaluation Board (EVB) and test bench will result in a significant increase in overall test costs. Therefore, it is necessary to provide an innovative and progressive test device to solve the above problems.

在一實施例中，一種測試裝置包括一第一測試座、一第二測試座及一電路板。該第一測試座具有複數個第一頂針。該第二測試座具有複數個第二頂針。該電路板位於該等第一頂針與該等第二頂針之間，且接觸該等第一頂針及該等第二頂針。In one embodiment, a test device includes a first test socket, a second test socket, and a circuit board. The first test seat has a plurality of first thimbles. The second test seat has a plurality of second thimbles. The circuit board is located between the first ejector pins and the second ejector pins, and contacts the first ejector pins and the second thimble pins.

圖1顯示根據本新型之實施態樣的測試裝置10之分解圖。圖2顯示根據本新型之實施態樣的測試裝置10之組合圖。配合參閱圖1及圖2，本新型之測試裝置10包括一第一測試座11、一第二測試座12及一電路板13。該第一測試座11具有一底部11B、一側部11L、複數個第一頂針（或探針）111及一第一容置槽112。該側部11L連接該底部11B。在本實施例中，該側部11L係由該底部11B向上延伸，使得該側部11L及該底部11B定義出該第一容置槽112。此外，該第一容置槽112具有一第一寬度W1。在一實施例中，該第一測試座11之底部11B及側部11L之材質包含金屬。該等第一頂針111係插設於該底部11B，且該等第一頂針111係貫穿該底部11B。此外，該等第一頂針111係對應該第一容置槽112。各該第一頂針111具有一第一端111A及一第二端111B，各該第一端111A位於該第一容置槽112內，各該第二端111B位於該第一容置槽112外。該第一端111A係可電性導通至該第二端111B。在一實施例中，各該第一頂針111係位於該底部11B之貫穿孔中，且可在該貫穿孔中上下移動。該第一頂針111或該貫穿孔具有一卡掣結構或承接結構，以避免該第一頂針111掉出該貫穿孔。在一實施例中，各該第一頂針111更包括一彈性元件（例如：彈簧），使得該第一頂針111係為可伸縮或可彎曲。或者，該第一頂針111本身係為細長之金屬，其本身為可彎曲。在一實施例中，該第一頂針111之外週表面（除了該第一端111A及該第二端111B之外）可塗佈一絕緣材料，以避免與該底部11B電性連接。該第二測試座12連接於該第一測試座11，且較佳地，該第二測試座12係固設於該第一測試座11。該第二測試座12具有複數個第二頂針（或探針）121、一第二容置槽122、一針座部123及一底面12S。在一實施例中，該第二測試座12更具有一本體部12B及一結合部12C。該本體部12B具有一第三寬度W3，該第三寬度W3小於或等於該第一容置槽112之第一寬度W1，以使該本體部12B能置於該第一容置槽112內。該結合部12C連接該第一測試座11之側部11L，且較佳地，該結合部12C係固接（例如：鎖固）至該側部11L。在一實施例中，該第二測試座12之本體部12B、結合部12C及針座部123之材質包含金屬。該本體部12B與該針座部123定義出該第二容置槽122。該第二容置槽122具有一第二寬度W2，該第二寬度W2小於該第一容置槽112之第一寬度W1。該等第二頂針121係插設於該針座部123，且該等第二頂針121係貫穿該針座部123。此外，該等第二頂針121係對應該第二容置槽122。在一實施例中，相同單位面積下之該等第二頂針121的數量大於該等第一頂針111的數量，亦即，該等第二頂針121的分布密度大於該等第一頂針111的分布密度。此外，各該第二頂針121之寬度係小於各該第一頂針111。各該第二頂針121具有一測試端121A及一連接端121B，各該測試端121A位於該第二容置槽122內，各該連接端121B位於該第二容置槽122外。該測試端121A係可電性導通至該連接端121B。在一實施例中，各該第二頂針121係位於該針座部123之貫穿孔中，且可在該貫穿孔中上下移動。該第二頂針121或該貫穿孔具有一卡掣結構或承接結構，以避免該第二頂針121掉出該貫穿孔。在一實施例中，各該第二頂針121更包括一彈性元件（例如：彈簧），使得該第二頂針121係為可伸縮或可彎曲。或者，該第二頂針121本身係為細長之金屬，其本身為可彎曲。在一實施例中，該第二頂針121之外週表面（除了該測試端121A及該連接端121B之外）可塗佈一絕緣材料，以避免與該針座部123電性連接。該針座部123亦對應該第二容置槽122，且該針座部123位於該第一測試座11之第一容置槽112內。該電路板13位於該等第一頂針111與該等第二頂針121之間，且接觸該等第一頂針111及該等第二頂針121。在本實施例中，該電路板13之下表面接觸各該第一頂針111之第一端111A，且該電路板13之上表面接觸各該第二頂針121之連接端121B。該電路板13之上表面之線路層係電性連接至該電路板13之下表面之線路層，且該電路板13之上表面之線路層之線寬/線距(L/S)係小於該電路板13之下表面之線路層之線寬/線距(L/S)。該等第二頂針121的分布密度係對應該電路板13之上表面之線路層之線寬/線距(L/S)，該等第一頂針111的分布密度係對應該電路板13之下表面之線路層之線寬/線距(L/S)，因此，該等第二頂針121的分布密度大於該等第一頂針111的分布密度。此外，該電路板13具有一長度L，該長度L大於該第二容置槽122之第二寬度W2，且該長度L係小於或等於該第一容置槽112之第一寬度W1，使得該電路板13可容置於該第一容置槽112內。在本實施例中，為防止該電路板13於測試過程中發生偏移，該電路板13係設置於該第一測試座11之第一容置槽112內，以限位該電路板13。此外，該第二測試座12之底面12S頂抵該電路板13，亦可進一步限位該電路板13。在本實施例中，該電路板13及該第二測試座12係位於該第一測試座11之第一容置槽112內。然而，在其他實施例中，該第一測試座11可能不具有該側部11L，亦即僅有該底部11B，而沒有該第一容置槽112；而且該底部11B、該電路板13及該第二測試座12係利用一夾持裝置夾持住。另外，由於該電路板13之上表面可能具有至少一電路元件13E（例如：主動元件或被動元件），為避免該至少一電路元件13E干涉到該第二測試座12之設置，在本實施例中，該第二測試座12係具有至少一讓位槽124，該至少一讓位槽124對應該至少一電路元件13E，以提供讓位空間容置該至少一電路元件13E，進而避免該至少一電路元件13E干涉到該第二測試座12，或者可以避免該至少一電路元件13E被該第二測試座12壓壞。在本實施例中，該至少一讓位槽124係凹設於該針座部123之至少一側，且該至少一讓位槽124之數量及位置可依據該至少一電路元件13E之數量及位置進行對應調整。圖3顯示使用本新型之實施態樣的測試裝置進行晶片測試之示意圖。配合參閱圖2及圖3，該第二容置槽122係用以容置一晶片20，施加一下壓力31於一上蓋30並使該上蓋30輕壓該晶片20，以使該晶片20之導電凸塊21接觸該第二測試座12之該等第二頂針121之測試端121A。此外，在測試配置中，該電路板13係位於該第一測試座11之底部11B與該第二測試座12之針座部123之間，藉由該下壓力31可確保該等第二頂針121之連接端121B接觸該電路板13之上表面，且該電路板13之下表面接觸各該第一頂針111之第一端111A。較佳地，該電路板13與該第二測試座12之針座部123之間具有一間距G，且該電路板13不接觸該第一測試座11之底部11B，以使該電路板13之上方及下方能保有散熱空間。要注意的是，該電路板13係用以預計供該晶片20附著於其上，以形成一模組。亦即，該晶片20係預計以覆晶方式附著至與該模組相同之電路板13上，因此，該電路板13之上表面之線路層之佈線係對應該晶片20之導電凸塊21之分佈。當欲對該晶片20進行測試時，該測試裝置10更包括一測試電路板14，該測試電路板14位於該第一測試座11下方，且接觸該等第一頂針111。該測試電路板14可根據測試者所下達之測試指令，經由該等第一頂針111、該電路板13及該等第二頂針121，以對該晶片20進行功能測試（而非僅是電性測試或物理特性測試）。要注意的是，該功能測試係為將該晶片20及該電路板13視為一個模組所進行之功能測試，藉此，可了解該晶片20安裝於一應用電路板上之實際運作情形。該功能測試之項目包括但不限於：該晶片20及該電路板13所形成之模組是否運作正常、該測試電路板14發出測試指令後是否會收到回覆、該測試電路板14發出校準訊號後是否會收到正確回覆等等。在一實施例之測試方式中，於實際測試前，需先確認該電路板13為測試結果正常之電路板，方能利用該電路板13測試該晶片20位於模組時之實際運作情形。於實際測試過程中，若經由該測試電路板14發現測試結果為失敗時，則可判定該晶片20異常。當然，該電路板13經長時間測試操作後，亦有可能發生異常，因此，倘若在測試過程中連續發生多次測試結果為失敗的情況，則可能並非該晶片20發生異常，而是該電路板13發生異常，此時可先以一測試正常之晶片進行測試，若測試結果依然是失敗，則可判定是該電路板13異常，必須更換該電路板13，方能進行後續晶片測試。本新型之測試裝置10可直接測試預計安裝在模組上的晶片20，不用另外開發晶片測試電路板(Chip Test Evaluation Board (EVB))，故可省去開發新板及測試程式的時間，進而降低開發成本。此外，因該測試電路板14可使用與產線相同的模組測試電路板(Module Test Evaluation Board (EVB))，其二者會有相同的錯誤碼(Error Code)，故對於程式錯誤(Bug)的複製與分析會更容易。參閱圖4，其係顯示使用本新型之另一實施態樣的測試裝置進行晶片測試之示意圖。此實施態樣的測試裝置10a僅包括一第一測試座11a。該第一測試座11a具有一第一容置槽112a及複數個第一頂針113。該第一容置槽112a係用以容置一晶片20。各該第一頂針113具有一第一端113A及一第二端113B，各該第一端113A位於該第一容置槽112a內，各該第二端113B位於該第一容置槽112a外。一上蓋30a係用以輕壓該晶片20，以使該晶片20接觸該等第一頂針113。當欲對該晶片20進行測試時，一測試電路板14a係位於該第一測試座11a下方，且接觸該等第一頂針113。該測試電路板14a可根據測試者所下達之測試指令，對該晶片20進行電性測試或功能測試。要注意的是，該測試電路板14a與圖3之該測試電路板14a並不相同。上述實施例僅為說明本新型之原理及其功效，並非限制本新型，因此習於此技術之人士對上述實施例進行修改及變化仍不脫本新型之精神。本新型之權利範圍應如後述之申請專利範圍所列。1 shows an exploded view of a test device 10 in accordance with an embodiment of the present invention. 2 shows a combination of test devices 10 in accordance with an embodiment of the present invention. 1 and 2, the test device 10 of the present invention includes a first test stand 11, a second test stand 12, and a circuit board 13. The first test seat 11 has a bottom portion 11B, a side portion 11L, a plurality of first thimbles (or probes) 111, and a first accommodating groove 112. The side portion 11L is connected to the bottom portion 11B. In this embodiment, the side portion 11L extends upward from the bottom portion 11B such that the side portion 11L and the bottom portion 11B define the first receiving groove 112. In addition, the first accommodating groove 112 has a first width W1. In an embodiment, the material of the bottom portion 11B and the side portion 11L of the first test seat 11 comprises metal. The first ejector pins 111 are inserted into the bottom portion 11B, and the first ejector pins 111 are inserted through the bottom portion 11B. In addition, the first ejector pins 111 correspond to the first accommodating grooves 112. Each of the first pedestals 111 has a first end 111A and a second end 111B. The first end 111A is located in the first accommodating slot 112, and each of the second ends 111B is located outside the first accommodating slot 112. . The first end 111A is electrically conductive to the second end 111B. In an embodiment, each of the first thimbles 111 is located in the through hole of the bottom portion 11B and is movable up and down in the through hole. The first ejector pin 111 or the through hole has a latching structure or a receiving structure to prevent the first ejector pin 111 from falling out of the through hole. In an embodiment, each of the first thimbles 111 further includes a resilient member (eg, a spring) such that the first ejector pin 111 is telescopic or bendable. Alternatively, the first ejector pin 111 itself is an elongated metal that is itself bendable. In an embodiment, the outer peripheral surface of the first thimble 111 (except the first end 111A and the second end 111B) may be coated with an insulating material to avoid electrical connection with the bottom portion 11B. The second test socket 12 is connected to the first test socket 11 , and preferably, the second test socket 12 is fixed to the first test socket 11 . The second test socket 12 has a plurality of second thimbles (or probes) 121, a second accommodating groove 122, a needle seat portion 123 and a bottom surface 12S. In an embodiment, the second test seat 12 further has a body portion 12B and a joint portion 12C. The body portion 12B has a third width W3 that is less than or equal to the first width W1 of the first accommodating groove 112 so that the body portion 12B can be placed in the first accommodating groove 112. The joint portion 12C is coupled to the side portion 11L of the first test seat 11, and preferably, the joint portion 12C is fixed (eg, locked) to the side portion 11L. In one embodiment, the material of the body portion 12B, the joint portion 12C, and the hub portion 123 of the second test seat 12 includes metal. The second receiving groove 122 is defined by the body portion 12B and the socket portion 123. The second accommodating groove 122 has a second width W2 that is smaller than the first width W1 of the first accommodating groove 112. The second ejector pins 121 are inserted into the hub portion 123 , and the second ejector pins 121 are inserted through the hub portion 123 . In addition, the second ejector pins 121 correspond to the second accommodating grooves 122. In one embodiment, the number of the second ejector pins 121 in the same unit area is greater than the number of the first ejector pins 111, that is, the distribution density of the second ejector pins 121 is greater than the distribution of the first ejector pins 111. density. In addition, the width of each of the second thimbles 121 is smaller than each of the first thimbles 111. Each of the second ejector pins 121 has a test end 121A and a connecting end 121B. Each of the test ends 121A is located in the second accommodating groove 122, and each of the connecting ends 121B is located outside the second accommodating groove 122. The test end 121A is electrically connected to the connection end 121B. In an embodiment, each of the second ejector pins 121 is located in the through hole of the needle seat portion 123 and is movable up and down in the through hole. The second ejector pin 121 or the through hole has a latching structure or a receiving structure to prevent the second ejector pin 121 from falling out of the through hole. In an embodiment, each of the second thimbles 121 further includes a resilient member (eg, a spring) such that the second ejector pin 121 is telescopic or bendable. Alternatively, the second ejector pin 121 itself is an elongated metal that is itself bendable. In an embodiment, the outer peripheral surface of the second thimble 121 (except the test end 121A and the connecting end 121B) may be coated with an insulating material to avoid electrical connection with the hub portion 123. The needle seat portion 123 also corresponds to the second receiving groove 122 , and the needle seat portion 123 is located in the first receiving groove 112 of the first test seat 11 . The circuit board 13 is located between the first ejector pins 111 and the second ejector pins 121 and contacts the first ejector pins 111 and the second ejector pins 121. In this embodiment, the lower surface of the circuit board 13 contacts the first end 111A of each of the first thimbles 111, and the upper surface of the circuit board 13 contacts the connection end 121B of each of the second pedestals 121. The circuit layer on the upper surface of the circuit board 13 is electrically connected to the circuit layer on the lower surface of the circuit board 13, and the line width/line spacing (L/S) of the circuit layer on the upper surface of the circuit board 13 is smaller than The line width/line spacing (L/S) of the wiring layer on the lower surface of the board 13. The distribution density of the second ejector pins 121 is the line width/line spacing (L/S) of the circuit layer corresponding to the upper surface of the circuit board 13, and the distribution density of the first ejector pins 111 corresponds to the circuit board 13 The line width/line spacing (L/S) of the circuit layer of the surface, therefore, the distribution density of the second ejector pins 121 is greater than the distribution density of the first ejector pins 111. In addition, the circuit board 13 has a length L that is greater than the second width W2 of the second accommodating slot 122, and the length L is less than or equal to the first width W1 of the first accommodating slot 112, such that The circuit board 13 can be received in the first receiving slot 112. In the embodiment, in order to prevent the circuit board 13 from being displaced during the test, the circuit board 13 is disposed in the first receiving slot 112 of the first test socket 11 to limit the circuit board 13. In addition, the bottom surface 12S of the second test socket 12 abuts against the circuit board 13 and can further limit the circuit board 13. In this embodiment, the circuit board 13 and the second test socket 12 are located in the first receiving slot 112 of the first test socket 11 . However, in other embodiments, the first test seat 11 may not have the side portion 11L, that is, only the bottom portion 11B without the first receiving groove 112; and the bottom portion 11B, the circuit board 13 and The second test seat 12 is held by a clamping device. In addition, since the upper surface of the circuit board 13 may have at least one circuit component 13E (for example, an active component or a passive component), in order to prevent the at least one circuit component 13E from interfering with the setting of the second test socket 12, in this embodiment The second test socket 12 has at least one yielding slot 124 corresponding to the at least one circuit component 13E to provide a bit space for accommodating the at least one circuit component 13E, thereby avoiding the at least A circuit component 13E interferes with the second test socket 12, or the at least one circuit component 13E can be prevented from being crushed by the second test socket 12. In this embodiment, the at least one retaining slot 124 is recessed on at least one side of the socket portion 123, and the number and position of the at least one retaining slot 124 are responsive to the number of the at least one circuit component 13E and The position is adjusted accordingly. Figure 3 shows a schematic diagram of wafer testing using a test apparatus of an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, the second accommodating groove 122 is for accommodating a wafer 20, applying a pressure 31 to an upper cover 30, and causing the upper cover 30 to gently press the wafer 20 to electrically conduct the wafer 20. The bumps 21 contact the test ends 121A of the second thimbles 121 of the second test socket 12. In addition, in the test configuration, the circuit board 13 is located between the bottom portion 11B of the first test socket 11 and the socket portion 123 of the second test socket 12, and the second thimble is ensured by the downward pressure 31. The connecting end 121B of the 121 contacts the upper surface of the circuit board 13, and the lower surface of the circuit board 13 contacts the first end 111A of each of the first thimbles 111. Preferably, the circuit board 13 and the socket portion 123 of the second test socket 12 have a spacing G, and the circuit board 13 does not contact the bottom portion 11B of the first test socket 11 to make the circuit board 13 There is space for heat dissipation above and below. It is to be noted that the circuit board 13 is intended to be intended to be attached to the wafer 20 to form a module. That is, the wafer 20 is expected to be attached to the same circuit board 13 as the module in a flip chip manner. Therefore, the wiring of the wiring layer on the upper surface of the circuit board 13 corresponds to the conductive bump 21 of the wafer 20. distributed. When the wafer 20 is to be tested, the test device 10 further includes a test circuit board 14 located below the first test socket 11 and contacting the first ejector pins 111. The test circuit board 14 can perform functional testing on the wafer 20 via the first ejector pins 111, the circuit board 13 and the second ejector pins 121 according to the test instructions issued by the tester (not just electrical). Test or physical property test). It should be noted that the functional test is a functional test performed by the chip 20 and the circuit board 13 as a module, thereby understanding the actual operation of the wafer 20 mounted on an application circuit board. The functional test items include, but are not limited to, whether the module formed by the chip 20 and the circuit board 13 is functioning normally, whether the test circuit board 14 receives a test command, whether a reply is received, and the test circuit board 14 issues a calibration signal. Will you receive the correct reply afterwards? In the test mode of an embodiment, before the actual test, it is necessary to confirm that the circuit board 13 is a circuit board with a normal test result, and the circuit board 13 can be used to test the actual operation of the wafer 20 when it is located in the module. In the actual test process, if the test result is found to be a failure through the test circuit board 14, it can be determined that the wafer 20 is abnormal. Of course, after the long-term test operation of the circuit board 13, an abnormality may occur. Therefore, if a plurality of test results are consecutively failed during the test, the wafer 20 may not be abnormal, but the circuit may be The board 13 is abnormal. At this time, the test can be performed on a normal test wafer. If the test result is still a failure, it can be determined that the circuit board 13 is abnormal, and the circuit board 13 must be replaced before the subsequent wafer test can be performed. The test device 10 of the present invention can directly test the chip 20 that is expected to be mounted on the module, without separately developing a Chip Test Evaluation Board (EVB), thereby eliminating the time required to develop a new board and a test program. Reduce development costs. In addition, since the test circuit board 14 can use the same Module Test Evaluation Board (EVB) as the production line, both of which have the same Error Code, so the program error (Bug) ) Copying and analysis will be easier. Referring to Figure 4, there is shown a schematic diagram of wafer testing using a test apparatus of another embodiment of the present invention. The test device 10a of this embodiment includes only a first test stand 11a. The first test socket 11a has a first receiving groove 112a and a plurality of first ejector pins 113. The first accommodating groove 112a is for accommodating a wafer 20. Each of the first ejector pins 113 has a first end 113A and a second end 113B. The first end 113A is located in the first accommodating groove 112a, and the second end 113B is located outside the first accommodating groove 112a. . An upper cover 30a is used to lightly press the wafer 20 such that the wafer 20 contacts the first ejector pins 113. When the wafer 20 is to be tested, a test circuit board 14a is positioned below the first test socket 11a and contacts the first ejector pins 113. The test circuit board 14a can perform electrical or functional tests on the wafer 20 according to test instructions issued by the tester. It is to be noted that the test circuit board 14a is not the same as the test circuit board 14a of FIG. The above embodiments are merely illustrative of the principles and functions of the present invention, and are not intended to limit the present invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the present invention. The scope of the claims of the present invention should be as set forth in the appended claims.

10‧‧‧測試裝置
10a‧‧‧測試裝置
11‧‧‧第一測試座
11a‧‧‧第一測試座
11B‧‧‧底部
11L‧‧‧側部
111‧‧‧第一頂針
111A‧‧‧第一端
111B‧‧‧第二端
112‧‧‧第一容置槽
112a‧‧‧第一容置槽
113‧‧‧第一頂針
113A‧‧‧第一端
113B‧‧‧第二端
12‧‧‧第二測試座
12B‧‧‧本體部
12C‧‧‧結合部
12S‧‧‧底面
121‧‧‧第二頂針
121A‧‧‧測試端
121B‧‧‧連接端
122‧‧‧第二容置槽
123‧‧‧針座部
124‧‧‧讓位槽
13‧‧‧電路板
13E‧‧‧電路元件
14‧‧‧測試電路板
14a‧‧‧測試電路板
20‧‧‧晶片
21‧‧‧導電凸塊
30‧‧‧上蓋
30a‧‧‧上蓋
31‧‧‧下壓力
G‧‧‧間距
L‧‧‧長度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度10‧‧‧Testing device
10a‧‧‧Testing device
11‧‧‧First test seat
11a‧‧‧First test seat
11B‧‧‧ bottom
11L‧‧‧ side
111‧‧‧First thimble
111A‧‧‧ first end
111B‧‧‧second end
112‧‧‧First accommodating slot
112a‧‧‧First accommodating slot
113‧‧‧First thimble
113A‧‧‧ first end
113B‧‧‧ second end
12‧‧‧Second test seat
12B‧‧‧ Body Department
12C‧‧‧Combination Department
12S‧‧‧ bottom
121‧‧‧Second thimble
121A‧‧‧test side
121B‧‧‧Connected end
122‧‧‧Second accommodating slot
123‧‧‧ Needle seat
124‧‧‧Let the slot
13‧‧‧Circuit board
13E‧‧‧ circuit components
14‧‧‧Test circuit board
14a‧‧‧Test circuit board
20‧‧‧ wafer
21‧‧‧Electrical bumps
30‧‧‧Upper cover
30a‧‧‧上盖
31‧‧‧Under pressure
G‧‧‧ spacing
L‧‧‧ length
W1‧‧‧ first width
W2‧‧‧ second width
W3‧‧‧ third width

圖1顯示根據本新型之實施態樣的測試裝置之分解圖。圖2顯示根據本新型之實施態樣的測試裝置之組合圖。圖3顯示使用本新型之實施態樣的測試裝置進行晶片測試之示意圖。圖4顯示使用本新型之另一實施態樣的測試裝置進行晶片測試之示意圖。1 shows an exploded view of a test apparatus in accordance with an embodiment of the present invention. 2 shows a combination of test devices in accordance with an embodiment of the present invention. Figure 3 shows a schematic diagram of wafer testing using a test apparatus of an embodiment of the present invention. 4 is a schematic diagram showing wafer testing using a test apparatus of another embodiment of the present invention.

10‧‧‧測試裝置 10‧‧‧Testing device

11‧‧‧第一測試座 11‧‧‧First test seat

11B‧‧‧底部 11B‧‧‧ bottom

11L‧‧‧側部 11L‧‧‧ side

111‧‧‧第一頂針 111‧‧‧First thimble

111A‧‧‧第一端 111A‧‧‧ first end

111B‧‧‧第二端 111B‧‧‧second end

112‧‧‧第一容置槽 112‧‧‧First accommodating slot

12‧‧‧第二測試座 12‧‧‧Second test seat

12B‧‧‧本體部 12B‧‧‧ Body Department

12C‧‧‧結合部 12C‧‧‧Combination Department

12S‧‧‧底面 12S‧‧‧ bottom

121‧‧‧第二頂針 121‧‧‧Second thimble

121A‧‧‧測試端 121A‧‧‧test side

121B‧‧‧連接端 121B‧‧‧Connected end

122‧‧‧第二容置槽 122‧‧‧Second accommodating slot

123‧‧‧針座部 123‧‧‧ Needle seat

124‧‧‧讓位槽 124‧‧‧Let the slot

13‧‧‧電路板 13‧‧‧Circuit board

13E‧‧‧電路元件 13E‧‧‧ circuit components

G‧‧‧間距 G‧‧‧ spacing

Claims

A testing device comprising: a first test socket having a plurality of first thimbles; a second test socket having a plurality of second thimbles; and a circuit board located at the first thimbles and the second thimbles And contacting the first ejector pins and the second thimbles.

The test device of claim 1, wherein the first test socket has a first receiving slot, the first top is corresponding to the first receiving slot, and the second testing socket has a second receiving slot, and the second testing socket has a second receiving slot. The second top is for the second receiving slot.

The test device of claim 2, wherein the first receiving groove has a first width, and the second receiving groove has a second width, the second width being smaller than the first width.

The test device of claim 3, wherein the circuit board has a length greater than a second width of the second receiving slot.

The test device of claim 3, wherein the second test seat has a body portion, the body portion having a third width, the third width being less than or equal to a first width of the first receiving groove.

The test device of claim 2, wherein the circuit board is disposed in the first receiving slot.

The test device of claim 2, wherein the second test seat has a needle seat portion corresponding to the second receiving groove, and the needle seat portion is located in the first receiving groove of the first test seat .

The test device of claim 7, wherein the second ejector pins are inserted into the hub portion.

The test device of claim 7, wherein the first test socket has a bottom, the first ejector pins are inserted at the bottom, and the circuit board is located at a bottom of the first test seat and a second seat of the second test seat between.

The test device of claim 9, wherein the second test seat has a spacing between the hub portion and the circuit board.

The test device of claim 2, wherein each of the first ejector pins has a first end and a second end, each of the first ends is located in the first accommodating groove, and each of the second ends is located at the first accommodating Outside the slot, the circuit board contacts the first end of each of the first thimbles.

The test device of claim 2, wherein each of the second ejector pins has a test end and a connection end, and each test end is located in the second accommodating groove, and each of the connection ends contacts the circuit board.

The test device of claim 2, wherein the second receiving slot is for receiving a wafer.

The test device of claim 1, wherein the second test socket has a bottom surface that abuts against the circuit board.

The test device of claim 1, wherein the first test seat has a side portion, and the second test seat has a joint portion, and the joint portion of the second test seat is connected to a side portion of the first test seat.

The test device of claim 15, wherein the joint of the second test seat is fixed to a side of the first test seat.

The test device of claim 1, wherein the circuit board has at least one circuit component, the second test socket having at least one yielding slot, the at least one yielding slot corresponding to at least one circuit component.

The test device of claim 17, wherein the second test seat has a socket portion, and the at least one retaining groove is recessed on at least one side of the socket portion.

The test device of claim 1, wherein the number of the second thimbles in the same unit area is greater than the number of the first thimbles.

The test device of claim 1, further comprising a test circuit board located below the first test socket and contacting the first ejector pins.