TWM530955U - Test device for stacked package testing - Google Patents

Test device for stacked package testing Download PDF

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Publication number
TWM530955U
TWM530955U TW105209325U TW105209325U TWM530955U TW M530955 U TWM530955 U TW M530955U TW 105209325 U TW105209325 U TW 105209325U TW 105209325 U TW105209325 U TW 105209325U TW M530955 U TWM530955 U TW M530955U
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Taiwan
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test
socket unit
wafer
stacked package
probes
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TW105209325U
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Chinese (zh)
Inventor
guan-zhong Chen
zheng-hui Lin
jia-bin Sun
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Winway Technology Co Ltd
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Priority to TW105209325U priority Critical patent/TWM530955U/en
Publication of TWM530955U publication Critical patent/TWM530955U/en

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Description

應用於堆疊式封裝測試的測試裝置Test device for stacked package testing

本新型是有關於一種電子產品的測試裝置,特別是指一種應用於堆疊式封裝測試的測試裝置。The present invention relates to a test device for an electronic product, and more particularly to a test device for use in a stacked package test.

參閱圖1,為一堆疊式封裝測試裝置1,用以測試一待測晶片21,並包含一測試平台10、一上插座11,及一電連接於該測試平台10,並能配合該上插座11的下插座12。其中,該上插座11配合連接一良品晶片22,並包括一上本體111、一設置於該上本體111中的真空流道112、一連接於該真空流道112朝向該下插座12之一端的吸嘴113,及多數嵌設於該上本體111中,並各自具有一顯露於該上本體111外之測試接點101的測試探針114;該下插座12用以供該測試晶片21插設,並包括一下本體121,及多數嵌設於該下本體121中,並各自具有一顯露於該下本體121外之信號接點102的電連接件122。Referring to FIG. 1 , a stacked package test device 1 is used to test a wafer to be tested 21 , and includes a test platform 10 , an upper socket 11 , and an electrical connection to the test platform 10 , and can be matched with the upper socket The lower socket 12 of 11. The upper socket 11 is coupled to a good wafer 22, and includes an upper body 111, a vacuum flow path 112 disposed in the upper body 111, and a vacuum flow path 112 connected to one end of the lower socket 12. a nozzle 113, and a plurality of test probes 114 embedded in the upper body 111 and each having a test contact 101 exposed outside the upper body 111; the lower socket 12 is used for inserting the test wafer 21 And including a body 121, and a plurality of electrical connectors 122 embedded in the lower body 121 and each having a signal contact 102 exposed outside the lower body 121.

藉由該堆疊式封裝測試裝置1對該待測晶片21進行檢測時,該真空流道112連通於一真空泵浦(圖中未繪示),即能藉由該吸嘴113直接吸附擺放於特定位置的該待測晶片21,並且移動該待測晶片21。當該上插座11吸附該待測晶片21而移動至對應該下插座12的正確位置時,接著只要朝向該下插座12移動,即能如圖2所示地,使該待測晶片21插設於該下插座12,並讓該等電連接件122的信號接點102電連接於該待測晶片21。而當該上插座11自相反於該下插座12之一側同樣連接於該待測晶片21,並使得該等測試探針114的測試接點101電連接於該待測晶片21,則該待測晶片21、該下插座12、該上插座11、該良品晶片22,以及該測試平台10確實電連接,即能藉由該測試平台10的驅動,使電訊號在該良品晶片22及該待測晶片21中傳遞,藉由確認傳出的測試訊號,即能檢測該待測晶片21是否為良品。When the wafer 21 to be tested is detected by the stacked package test apparatus 1, the vacuum flow path 112 is connected to a vacuum pump (not shown), and can be directly adsorbed by the nozzle 113. The wafer 21 to be tested is in a specific position, and the wafer 21 to be tested is moved. When the upper socket 11 is attracted to the wafer to be tested 21 and moved to the correct position corresponding to the lower socket 12, then the wafer to be tested 21 can be inserted as shown in FIG. 2 as long as it is moved toward the lower socket 12. The lower socket 12 is electrically connected to the signal to be tested 21 of the electrical connector 122. When the upper socket 11 is also connected to the wafer 21 to be tested from the side opposite to the lower socket 12, and the test contacts 101 of the test probes 114 are electrically connected to the wafer 21 to be tested, the standby The test chip 21, the lower socket 12, the upper socket 11, the good wafer 22, and the test platform 10 are electrically connected, that is, the driving of the test platform 10 enables the electrical signal to be on the good wafer 22 and the waiting The test wafer 21 is transferred, and by confirming the transmitted test signal, it can be detected whether the wafer 21 to be tested is a good product.

由於該堆疊式封裝測試裝置1進行測試時,是藉由電訊號的傳遞而產生測試結果,故所述的電訊號若受到干擾,則有可能因而誤判測試結果,進而影響檢測的準確性。然而,通常為了降低製造成本,該上插座11是採用價格較為低廉且易於塑型的塑料材質,但是,可能干擾測試結果的電磁波卻會輕易通過所述的塑料材質,使得該等測試探針114之間產生交互干擾(crosstalk),該堆疊式封裝測試裝置1的檢測性能因而受到莫大影響,就提高檢測性能的角度而言,勢必需要一個有力的解決方案。When the stacked package test device 1 performs the test, the test result is generated by the transmission of the electrical signal. If the electrical signal is interfered, the test result may be misjudged, thereby affecting the accuracy of the test. However, usually in order to reduce the manufacturing cost, the upper socket 11 is made of a plastic material which is relatively inexpensive and easy to mold, but electromagnetic waves which may interfere with the test result can easily pass through the plastic material, so that the test probes 114 The crosstalk is generated, and the detection performance of the stacked package test apparatus 1 is greatly affected. In terms of improving the detection performance, a powerful solution is inevitable.

因此,本新型之目的,即在提供一種進行測試時得以避免干擾而提高準確性之應用於堆疊式封裝測試的測試裝置。Therefore, the object of the present invention is to provide a test apparatus for stacked package testing in which a test can be performed to avoid interference and improve accuracy.

於是,本新型應用於堆疊式封裝測試的測試裝置,適用於藉由一測試平台,配合一第一晶片而檢測一第二晶片,其中該第一晶片為一儲存有資訊的良品,確認該第二晶片電連接於該第一晶片後所傳出的測試訊號,即能檢測該第二晶片是否為良品。該應用於堆疊式封裝測試的測試裝置包含:一下插座單元;及一以一第一方向與該下插座單元彼此間隔設置的上插座單元。Therefore, the test device applied to the stacked package test is adapted to detect a second chip by using a test platform and a first wafer, wherein the first chip is a good product stored with information, confirming the first The test signal transmitted after the two wafers are electrically connected to the first wafer can detect whether the second wafer is a good product. The test device applied to the stacked package test comprises: a lower socket unit; and an upper socket unit spaced apart from each other by a first direction and the lower socket unit.

該下插座單元包括一個下主體,及多個顯露於該下主體之外的測試接點。該下插座單元是電連接於該測試平台,該下主體則是供承載該第二晶片,而該等測試接點與該測試平台電性導通。所述的測試接點是與該測試平台相互導通,並得以供其他電子元件連接,以與該測試平台一同運作。The lower socket unit includes a lower body and a plurality of test contacts exposed outside the lower body. The lower socket unit is electrically connected to the test platform, and the lower body is for carrying the second wafer, and the test contacts are electrically connected to the test platform. The test contact is electrically connected to the test platform and is connected to other electronic components for operation together with the test platform.

該上插座單元包括一個圍繞出多個呈貫穿狀之穿孔的上主體,及多個分別容置於該等穿孔中,且沿該第一方向延伸的探針。該等探針的一端是電連接於該第一晶片,該上主體有至少一部分是以金屬材質製成,所述的金屬材質至少一部分位於其中二探針之間。The upper socket unit includes an upper body surrounding a plurality of through-holes, and a plurality of probes respectively received in the holes and extending in the first direction. One end of the probes is electrically connected to the first wafer, and at least a portion of the upper body is made of a metal material, and at least a portion of the metal material is located between the two probes.

進行測試時,該上插座單元以該第一方向相對於該下插座單元移動,以配合該下插座單元,使該第二晶片電連接於該上插座單元之探針的另一端與該下插座單元的測試接點之間。該測試平台、該上插座單元、該下插座單元、該第一晶片,及該第二晶片形成訊號連接,使該第一晶片透過該等探針而與該第二晶片彼此傳輸電訊號。而由於金屬材質得以對電磁波產生良好的屏蔽效果,故該上插座單元得以藉由所述的金屬材質,在至少二探針之間產生屏蔽作用,避免當中所傳遞的電訊號受到交互干擾,藉此提高檢測的性能以及精準度。When the test is performed, the upper socket unit moves relative to the lower socket unit in the first direction to cooperate with the lower socket unit, so that the second chip is electrically connected to the other end of the probe of the upper socket unit and the lower socket The unit is tested between the contacts. The test platform, the upper socket unit, the lower socket unit, the first wafer, and the second wafer form a signal connection, such that the first wafer transmits electrical signals to the second wafer through the probes. Since the metal material can provide a good shielding effect on the electromagnetic wave, the upper socket unit can shield the at least two probes by the metal material, so as to avoid the interference of the electrical signals transmitted therebetween. This improves the performance and accuracy of the test.

本新型之功效在於:該上插座單元之上主體的至少一部分是採用金屬材質製成,故在該上插座單元與該下插座單元彼此配合而對該第二晶片進行測試時,得以藉由所述金屬材質,在至少二探針之間產生屏蔽作用,避免所傳遞的電訊號受到所產生之電磁波的交互干擾,有效提高檢測的性能以及精準度。The effect of the present invention is that at least a part of the upper body of the upper socket unit is made of a metal material, so that when the upper socket unit and the lower socket unit cooperate with each other to test the second wafer, The metal material has a shielding effect between at least two probes to prevent the transmitted electrical signals from being interfered by the generated electromagnetic waves, thereby effectively improving the performance and accuracy of the detection.

在本新型被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

參閱圖3,本新型應用於堆疊式封裝測試的測試裝置之一第一實施例,適用於藉由一測試平台90,配合一第一晶片91而檢測一第二晶片92,其中該第一晶片91通常為一儲存有資訊的記憶體晶片,並且為經檢測確認過的良品,配合進行檢測時,只要確認該第二晶片92連接於該第一晶片91時傳出的測試訊號是否正確,即能檢測該第二晶片92是否為良品。該第一實施例包含:一下插座單元3,及一以一第一方向D1與該下插座單元3彼此間隔的上插座單元4。Referring to FIG. 3, a first embodiment of the present invention is applied to a test apparatus for stacked package testing. The first embodiment is adapted to detect a second wafer 92 by a test platform 90 in cooperation with a first wafer 91, wherein the first wafer 91 is generally a memory chip that stores information, and is a good product that has been inspected and confirmed. When the detection is performed, it is confirmed whether the test signal transmitted when the second wafer 92 is connected to the first wafer 91 is correct, that is, Whether the second wafer 92 is good can be detected. The first embodiment comprises: a lower socket unit 3, and an upper socket unit 4 spaced apart from the lower socket unit 3 by a first direction D1.

該下插座單元3包括一個下主體31,及多個顯露於該下主體31之外的測試接點32。該下插座單元3是電連接於該測試平台90,而該下主體31是設置於該測試平台90上,並供承載該第二晶片92。所述的測試接點32是與該測試平台90彼此是電性導通,以與該測試平台90一同運作。而該上插座單元4包括一個圍繞出多個呈貫穿狀之穿孔410的上主體41,及多個分別容置於該等穿孔410中,且沿該第一方向D1延伸的探針42。該等探針42的一端是電連接於該第一晶片91,該上主體41具有一以與該第一方向D1垂直之方向延伸的金屬層411,及二於相反兩側以該第一方向D1分別連接於該金屬層411,並與該金屬層411同向延伸的非金屬層412、413。要特別說明的是,該等穿孔410是貫穿該金屬層411,使得該等探針42得以由該金屬層411所圍繞。The lower socket unit 3 includes a lower body 31 and a plurality of test contacts 32 exposed outside the lower body 31. The lower socket unit 3 is electrically connected to the test platform 90, and the lower body 31 is disposed on the test platform 90 and carries the second wafer 92. The test contacts 32 are electrically connected to the test platform 90 to operate together with the test platform 90. The upper socket unit 4 includes an upper body 41 surrounding a plurality of through-holes 410, and a plurality of probes 42 respectively received in the holes 410 and extending along the first direction D1. One end of the probes 42 is electrically connected to the first wafer 91. The upper body 41 has a metal layer 411 extending in a direction perpendicular to the first direction D1, and two opposite sides are opposite to the first direction. D1 is respectively connected to the metal layer 411 and non-metal layers 412, 413 extending in the same direction as the metal layer 411. It is specifically noted that the perforations 410 are through the metal layer 411 such that the probes 42 are surrounded by the metal layer 411.

參閱圖4,進行測試時,該上插座單元4以該第一方向D1朝向該下插座單元3移動,以配合該下插座單元3,使該第二晶片92電連接於該上插座單元4之探針42的另一端與該下插座單元3的測試接點32之間。該測試平台90、該上插座單元4、該下插座單元3、該第一晶片91,及該第二晶片92形成訊號連接,使該第一晶片91透過該等探針42而與該第二晶片92而傳遞電訊號。進行測試的過程中,電訊號會在該等探針42之間傳遞,只要藉由該金屬層411對電磁波產生屏蔽的特性,在每二探針42之間即能產生良好的屏蔽作用,避免所傳遞的電訊號受到所產生之電磁波的交互干擾,故能藉此提高檢測的性能以及精準度。Referring to FIG. 4, when the test is performed, the upper socket unit 4 is moved toward the lower socket unit 3 in the first direction D1 to cooperate with the lower socket unit 3 to electrically connect the second chip 92 to the upper socket unit 4. The other end of the probe 42 is between the test contact 32 of the lower socket unit 3. The test platform 90, the upper socket unit 4, the lower socket unit 3, the first wafer 91, and the second wafer 92 form a signal connection, so that the first wafer 91 passes through the probes 42 and the second The chip 92 transmits electrical signals. During the test, the electrical signal is transmitted between the probes 42. As long as the electromagnetic layer is shielded by the metal layer 411, a good shielding effect can be produced between each of the two probes 42 to avoid The transmitted electrical signal is interfered by the electromagnetic waves generated, so that the performance and accuracy of the detection can be improved.

參閱圖5,為本新型應用於堆疊式封裝測試的測試裝置之一第二實施例,該第二實施例與該第一實施例的差別在於:該上插座單元4之上主體41是採用金屬材質所製成,且該上插座單元4還包括一貫通該上主體41且一端用以連通一真空抽吸設備(圖中未繪示)的真空流道43,及一連接於該真空流道43相反於該真空抽吸設備之一端的吸嘴44。Referring to FIG. 5, a second embodiment of a test apparatus for a stacked package test according to the present invention is different from the first embodiment in that the upper body 41 of the upper socket unit 4 is made of metal. The upper socket unit 4 further includes a vacuum flow path 43 extending through the upper body 41 and connected to a vacuum suction device (not shown), and is connected to the vacuum flow path. 43 is opposite to the suction nozzle 44 at one end of the vacuum suction device.

由於該第二實施例的上插座單元4的上主體41是以金屬材質所製成,故進行檢測時同樣能藉由金屬的屏蔽效果而達到與該第一實施例相同的效果。另外,由於以金屬材質製成的該上主體41相較於例如塑膠之非金屬而言,具有相對較佳的剛性,除了在頻繁組裝又脫離的過程當中,得以因而產生增加該上插座單元4之使用壽命外,亦有利於進行貫通該上主體41的加工而製成該真空流道43。而該上主體41藉由以金屬材質製成而增強剛性時,在同等程度的剛性考量下,該上主體41的體積得以相對縮小,藉此能縮小該上插座單元4的整體體積,並得以製成薄型化的外觀。Since the upper main body 41 of the upper socket unit 4 of the second embodiment is made of a metal material, the same effect as that of the first embodiment can be achieved by the shielding effect of the metal when detecting. In addition, since the upper body 41 made of a metal material has a relatively better rigidity than a non-metal such as plastic, in addition to the process of frequent assembly and detachment, the upper socket unit 4 is thereby increased. In addition to the service life, it is also advantageous to perform the processing of the upper body 41 to form the vacuum flow path 43. When the upper body 41 is made of a metal material to enhance the rigidity, the volume of the upper body 41 can be relatively reduced under the same degree of rigidity, thereby reducing the overall volume of the upper socket unit 4, and Made into a thinned appearance.

參閱圖5與圖6,要特別說明的是,以該第二實施例進行測試時,該真空流道43相反於該吸嘴44之一端得以連通一真空抽吸設備,以提供抽吸該真空流道43中之空氣的動力,使該吸嘴44得以用來吸附物品。接著,只要直接移動該上插座單元4而以該吸嘴44吸附該第二晶片92,即能達成移動該第二晶片92的功效,得以藉由移動該上插座單元4的方式,輕易移動該第二晶片92並使該上插座單元4與該下插座單元3組接,以系統化、自動化的方式完成檢測,使得檢測的過程能更加有效率。Referring to FIG. 5 and FIG. 6, it is specifically noted that, when tested in the second embodiment, the vacuum flow path 43 is connected to a vacuum suction device opposite to one end of the suction nozzle 44 to provide suction of the vacuum. The power of the air in the flow passage 43 allows the suction nozzle 44 to be used to adsorb the articles. Then, as long as the upper socket unit 4 is directly moved and the second wafer 92 is sucked by the suction nozzle 44, the effect of moving the second wafer 92 can be achieved, and the upper socket unit 4 can be easily moved by moving the upper socket unit 4. The second wafer 92 and the upper socket unit 4 are assembled with the lower socket unit 3 to perform the detection in a systematic and automated manner, so that the detection process can be more efficient.

綜上所述,本新型應用於堆疊式封裝測試的測試裝置之上插座單元4之上主體41的至少一部分是以金屬材質製成,得以藉由金屬對電磁波所能產生之屏蔽效果,對於電訊號在該等探針42中傳遞時產生之電磁波產生屏蔽效果,避免所述電磁波干擾測試時傳遞之電訊號,藉此提升檢測的性能和準確度,故確實能達成本新型之目的。In summary, the present invention is applied to a test device of a stacked package test. At least a part of the main body 41 of the socket unit 4 is made of a metal material, and the shielding effect by the metal on the electromagnetic wave can be obtained. The electromagnetic waves generated when the probes are transmitted in the probes 42 have a shielding effect, and the electromagnetic waves are prevented from interfering with the electrical signals transmitted during the test, thereby improving the performance and accuracy of the detection, so that the object of the present invention can be achieved.

惟以上所述者,僅為本新型之實施例而已,當不能以此限定本新型實施之範圍,凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本新型專利涵蓋之範圍內。However, the above is only the embodiment of the present invention, and when it is not possible to limit the scope of the present invention, all the simple equivalent changes and modifications according to the scope of the patent application and the contents of the patent specification are still This new patent covers the scope.

3‧‧‧下插座單元
31‧‧‧下主體
32‧‧‧測試接點
4‧‧‧上插座單元
41‧‧‧上主體
410‧‧‧穿孔
411‧‧‧金屬層
412‧‧‧非金屬層
413‧‧‧非金屬層
42‧‧‧探針
43‧‧‧真空流道
44‧‧‧吸嘴
90‧‧‧測試平台
91‧‧‧第一晶片
92‧‧‧第二晶片
D1‧‧‧第一方向
3‧‧‧Under socket unit
31‧‧‧Lower subject
32‧‧‧Test contacts
4‧‧‧Upper socket unit
41‧‧‧Upper subject
410‧‧‧Perforation
411‧‧‧metal layer
412‧‧‧Non-metal layer
413‧‧‧Non-metal layer
42‧‧‧Probe
43‧‧‧vacuum runner
44‧‧‧ nozzle
90‧‧‧Test platform
91‧‧‧First chip
92‧‧‧second chip
D1‧‧‧ first direction

本新型之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中: 圖1是一示意圖,說明一現有的堆疊式封裝測試裝置; 圖2是一示意圖,說明該堆疊式封裝測試裝置吸附一待測晶片並進行檢測的情況; 圖3是一示意圖;說明本新型應用於堆疊式封裝測試的測試裝置的一第一實施例; 圖4是一示意圖,說明採用該第一實施例對一待測晶片進行測試的情況; 圖5是一示意圖,說明本新型應用於堆疊式封裝測試的測試裝置的一第二實施例;及 圖6是一示意圖,說明採用該第二實施例對該待測晶片進行測試的情況。Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic diagram illustrating a conventional stacked package test apparatus; FIG. 2 is a schematic diagram illustrating the stacked type FIG. 3 is a schematic view showing a first embodiment of the test device applied to the stacked package test; FIG. 4 is a schematic view showing the first use of the test device; FIG. 5 is a schematic view showing a second embodiment of the test device applied to the stacked package test of the present invention; and FIG. 6 is a schematic view showing the second implementation For example, the test of the wafer to be tested.

3‧‧‧下插座單元 3‧‧‧Under socket unit

31‧‧‧下主體 31‧‧‧Lower subject

32‧‧‧測試接點 32‧‧‧Test contacts

4‧‧‧上插座單元 4‧‧‧Upper socket unit

41‧‧‧上主體 41‧‧‧Upper subject

410‧‧‧穿孔 410‧‧‧Perforation

411‧‧‧金屬層 411‧‧‧metal layer

412‧‧‧非金屬層 412‧‧‧Non-metal layer

413‧‧‧非金屬層 413‧‧‧Non-metal layer

42‧‧‧探針 42‧‧‧Probe

90‧‧‧測試平台 90‧‧‧Test platform

91‧‧‧第一晶片 91‧‧‧First chip

92‧‧‧第二晶片 92‧‧‧second chip

D1‧‧‧第一方向 D1‧‧‧ first direction

Claims (4)

一種應用於堆疊式封裝測試的測試裝置,適用於藉由一測試平台,配合一第一晶片而檢測一第二晶片,該應用於堆疊式封裝測試的測試裝置包含: 一下插座單元,包括一個下主體,及多個顯露於該下主體之外的測試接點,該下插座單元電連接於該測試平台,該下主體是供承載該第二晶片,而該等測試接點與該測試平台電性導通;及 一上插座單元,以一第一方向與該下插座單元彼此間隔,並包括一個圍繞出多個呈貫穿狀之穿孔的上主體,及多個分別容置於該等穿孔中,且沿該第一方向延伸的探針,該等探針的一端是電連接於該第一晶片,該上主體有至少一部分是以金屬材質製成,所述的金屬材質至少一部分位於其中二探針之間; 進行測試時,該上插座單元以該第一方向相對於該下插座單元移動,以配合該下插座單元,使該第二晶片電連接於該上插座單元之探針的另一端與該下插座單元的測試接點之間,該測試平台、該上插座單元,及該下插座單元、該第一晶片,與該第二晶片形成訊號連接,使該第一晶片透過該等探針而與該第二晶片彼此傳輸電訊號,所述的金屬材質在至少二探針之間產生屏蔽作用而避免所述電訊號受到交互干擾。A test device for a stacked package test is adapted to detect a second wafer by using a test platform in conjunction with a first wafer. The test device for the stacked package test comprises: a socket unit, including a lower a main body, and a plurality of test contacts exposed outside the lower body, the lower socket unit is electrically connected to the test platform, the lower body is for carrying the second chip, and the test contacts are electrically connected to the test platform And an upper socket unit spaced apart from the lower socket unit by a first direction, and including an upper body surrounding a plurality of through-holes, and a plurality of respectively received in the perforations, And a probe extending along the first direction, one end of the probes is electrically connected to the first wafer, and at least a portion of the upper body is made of a metal material, and at least a part of the metal material is located therein Between the pins; when the test is performed, the upper socket unit moves relative to the lower socket unit in the first direction to cooperate with the lower socket unit to electrically connect the second wafer to the upper plug Between the other end of the probe of the unit and the test contact of the lower socket unit, the test platform, the upper socket unit, and the lower socket unit, the first wafer form a signal connection with the second chip, so that the The first wafer transmits electrical signals to the second wafer through the probes, and the metal material creates a shielding effect between the at least two probes to prevent the electrical signals from being interfered with each other. 如請求項1所述應用於堆疊式封裝測試的測試裝置,其中,該上插座單元之上主體具有一以與該第一方向垂直之方向延伸的金屬層,及至少一以該第一方向連接於該金屬層,並與該金屬層同向延伸的非金屬層,該等穿孔至少貫穿該金屬層。The test device applied to the stacked package test according to claim 1, wherein the upper body of the upper socket unit has a metal layer extending in a direction perpendicular to the first direction, and at least one is connected in the first direction And a non-metal layer extending in the same direction as the metal layer, the through holes extending through at least the metal layer. 如請求項1所述應用於堆疊式封裝測試的測試裝置,其中,該上插座單元之上主體是採用金屬材質所製成。The test device applied to the stacked package test according to claim 1, wherein the upper body of the upper socket unit is made of a metal material. 如請求項3所述應用於堆疊式封裝測試的測試裝置,其中,該上插座單元還包括一貫通該上主體且一端用以連通一真空抽吸設備的真空流道,及一連接於該真空流道相反於該真空抽吸設備之一端的吸嘴。The test device applied to the stacked package test according to claim 3, wherein the upper socket unit further comprises a vacuum flow path penetrating the upper body and one end for communicating with a vacuum suction device, and a vacuum is connected thereto The flow path is opposite to the suction nozzle at one end of the vacuum suction device.
TW105209325U 2016-06-22 2016-06-22 Test device for stacked package testing TWM530955U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607223B (en) * 2017-03-24 2017-12-01 Press-measuring mechanism for stacked package electronic components and test classification equipment for application thereof
CN113078079A (en) * 2020-03-26 2021-07-06 Tse有限公司 Semiconductor package testing device
TWI827216B (en) * 2021-08-27 2023-12-21 南韓商Tse有限公司 Test apparatus for semiconductor package

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607223B (en) * 2017-03-24 2017-12-01 Press-measuring mechanism for stacked package electronic components and test classification equipment for application thereof
CN113078079A (en) * 2020-03-26 2021-07-06 Tse有限公司 Semiconductor package testing device
TWI760155B (en) * 2020-03-26 2022-04-01 南韓商Tse有限公司 Test apparatus for semiconductor package
CN113078079B (en) * 2020-03-26 2023-09-22 Tse有限公司 Semiconductor package testing device
TWI827216B (en) * 2021-08-27 2023-12-21 南韓商Tse有限公司 Test apparatus for semiconductor package

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