TWM472195U - Testing apparatus for semiconductor chip - Google Patents

Description

Semiconductor wafer test device

The present invention relates to a test device for a semiconductor wafer, and more particularly to a component of a semiconductor wafer test device.

In a conventional semiconductor manufacturing process, after a wafer containing a plurality of semiconductor dies is sequentially diced and packaged, a plurality of semiconductor chips are formed. In general, these fabricated semiconductor wafers undergo a final test (FT, Final Test) to screen out defective semiconductor wafers.

Figure 1 shows a cross-sectional view of a test apparatus of a conventional semiconductor wafer applied to a test. As shown in FIG. 1, the test apparatus 100 for a semiconductor wafer includes a test socket (not shown) and an interface board 20. The test socket includes a test probe housing 10 and an upper cover (not shown). The upper cover is pivotally coupled to the test probe holder 10 and can cover the upper surface of the test probe holder 10. The test probe holder 10 is disposed between the semiconductor wafer 30 and the vial 20. The test probe holder 10 includes a plurality of through holes 110 and a plurality of test probes 111, 112. The through holes 110 respectively penetrate the upper and lower surfaces of the test probe holder 10, and the test probes 111 and 112 respectively penetrate the through holes 110 and protrude from the upper and lower surfaces of the test probe holder 10. The test probes 111 and 112 are electrically connected to the semiconductor wafer 30 and the interface panel 20 respectively.

In the above test of semiconductor wafers, both Power Integrity (PI) and Signal Integrity (SI) are important factors affecting test results. Prime. In order to maintain power integrity and signal integrity, a plurality of capacitive elements 121 are usually mounted on the interface panel 20, and the capacitive elements 121 can serve as a decoupling capacitor or a bypass capacitor. Reduce noise. In general, the shorter the distance between the capacitive element 121 and the semiconductor wafer 30, the better the effect of maintaining power integrity and signal integrity, and how to more effectively reduce noise to maintain power integrity and signal integrity. It is a problem that needs to be broken now in semiconductor wafer testing technology.

The present invention provides a test device for a semiconductor wafer that provides a capacitive element that is closer to the semiconductor wafer to be tested.

The present invention provides a test device for a semiconductor wafer, comprising a test socket and a dielectric panel, the test socket including a test probe holder and an upper cover; the upper cover is pivotally connected to the test probe holder and can cover the test probe An upper surface of the socket; the test probe holder is disposed between the semiconductor wafer and the interface panel, and has an upper surface, a lower surface, and a plurality of through holes extending from the upper surface to the lower surface, wherein the upper surface The test probe holder includes at least two conductive layers, at least one dielectric layer, and a plurality of test probes; the at least one dielectric layer is disposed between the conductive layers; the plurality of tests The probes respectively extend through the test probe holder and protrude from the upper and lower surfaces to electrically connect the semiconductor wafer and the dielectric panel respectively; wherein at least one test probe is electrically connected to one of the conductive layers, and the other The test probe is electrically insulated from the conductive layers.

Based on the above, in the test device for a semiconductor wafer of the present invention, the test probe holder body is composed of a printed circuit board composed of at least two conductive layers and at least one dielectric layer, and the printed circuit board is used to replace A test probe holder made of a non-conductive material is known.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and description, and are not intended to limit the creation.

100, 200, 300‧‧‧ Test equipment for semiconductor wafers

10‧‧‧Test probe holder

11‧‧‧ upper surface

12‧‧‧ Lower surface

20‧‧‧Intermediate panel

30‧‧‧Semiconductor wafer

121‧‧‧Capacitive components

122‧‧‧Discrete capacitive components

110‧‧‧through holes

111, 112‧‧‧ test probe

130a, 130b‧‧‧ Printed circuit boards

131‧‧‧ Conductive layer

132, 133‧‧‧ power circuit

1311‧‧‧Power layer

1312‧‧‧ dielectric layer

1313‧‧‧ Grounding layer

1314‧‧‧Signal layer

1 is a cross-sectional view of a test device of a semiconductor wafer of the prior art; and FIG. 2 is a schematic view of a test device for a semiconductor wafer according to the first embodiment of the present invention.

3 is a schematic view of a test apparatus for a semiconductor wafer according to a second embodiment of the present invention.

Referring to FIG. 2, FIG. 2 is a schematic diagram of a semiconductor wafer testing apparatus 200 disposed between a semiconductor wafer 30 and a test system (not shown), including a test socket (in accordance with an embodiment of the present invention). Socket, not shown in the figure) and a panel 20. The test socket further includes a test probe holder 10 and an upper cover (not shown). The test probe holder 10 has an upper surface 11 and a lower surface 12 and a plurality of through holes 110 extending from the upper surface 11 to the lower surface 12, wherein the upper surface 11 is for carrying a semiconductor wafer 30. The upper cover is pivotally connected to the test probe holder 10 and can cover the upper surface 11 of the test probe holder 10 and the semiconductor wafer 30. The test probe holder 10 includes at least two conductive layers 131, at least one dielectric layer 1312, and a plurality of test probes 111, 112, wherein at least one dielectric layer 1312 is disposed between the conductive layers 131 to make the two conductive layers 131 is insulated from each other.

In the present embodiment, the semiconductor component 30 is carried on the upper surface 11 of the test probe holder 10. The dielectric panel 20 is disposed on the lower surface 12 of the test probe holder 10 corresponding to the semiconductor component 30, wherein the interface panel 20 and the semiconductor wafer 30 are provided. The position relative to the test probe holder 10 is only used to illustrate Figure 2 of this creation. In practical use, the relative positions of the semiconductor wafer 30 and the interface panel 20 and the test probe holder 10 can be interchanged, and the present embodiment should not be construed as limiting the present invention.

The plurality of test probes 111, 112 are used to electrically connect and conduct the semiconductor wafer 30 and the dielectric panel 20 corresponding to the upper surface 11 and the lower surface 12 of the test probe holder 10. The test probe 111 is an electrical channel for transmitting the test signal, so the test probe 111 is electrically connected to the signal layer 1314 of the test probe holder 10. Test probe 112 is for The power supply and the ground are electrically connected to each other. Therefore, the test probe 112 and the power layer 1311 of the test probe holder 10 and the ground layer 1313 are electrically connected.

These test probes 111, 112 are elastic probes that provide a degree of telescopic travel, so that when the test probes 111, 112 contact the device under test, such as the semiconductor wafer 30, the surface flatness of the semiconductor wafer 30 can be overcome. The variation, surely contacts the semiconductor wafer 30 to be tested. The foregoing upper cover with the test probe holder 10 can cover the upper surface 11 of the test probe holder 10 and the semiconductor wafer 30 and can be in contact with the semiconductor wafer 30. The upper cover thus provides the pressure at which the semiconductor wafer 30 is in contact with the test probe holder 10.

The interface panel 20 is disposed between the test probe holder 10 and a test system (not shown), and includes a plurality of signals, a plurality of power sources, and a plurality of ground transmission circuits. The upper and lower surfaces of the interface panel 20 are provided with a plurality of connection lines such as a plurality of transmission lines, a plurality of vias or a plurality of pads. In one embodiment, the upper surface of the interface panel 20 is electrically connected to the plurality of test probes 111 and 112 of the test probe holder 10 through a plurality of connection terminals, and the lower surface of the interface panel 20 is electrically connected to the plurality of connection terminals. Sexually connected to a test system.

In detail, the different transmission circuits of the interface panel 20 can be electrically connected to the corresponding plurality of connection terminals of the semiconductor wafer 30 through the plurality of test probes 111 and 112 in the test probe holder 10, and the test probe holder 10 The plurality of conductive layers 131 are electrically connected to the signal layer 1314. That is, a plurality of signals, multiple powers, and signals of a plurality of ground transmission circuits in the interface panel 20 can pass through the plurality of test probes 111 in the test probe holder 10, 112 are respectively transferred to corresponding connection terminals of the semiconductor wafer 30. The electrical signals of the semiconductor wafer 30 can also be transferred to the corresponding transmission circuit of the interface panel 20 via the plurality of test probes 111, 112 in the test probe holder 10 for transmission to the test system.

In addition, in the present creation, the interface panel 20 can be, but is not limited to, a test board (Load Board), a test probe card (Probe PCB), and a carrier board (Substrate).

In an embodiment of the present invention, the test probe holder 10 includes at least one printed circuit board 130a, 130b and a plurality of test probes 111, 112, a plurality of test probes 111, 112 extend through the test probe holder 10 and protrude from the surface of the printed circuit board 130a, 130b. The printed circuit board 130a, 130b includes at least one power layer 1311 and at least one ground layer 1313. The power layer 1311 and the ground layer 1313 have a dielectric layer 1312. The power layer 1311 and the ground layer 1313 have opposite polarities, and the power layer 1311 The ground layer 1313 is electrically insulated from each other through the dielectric layer 1312, so that the power supply layer 1311, the ground layer 1313 and the dielectric layer 1312 form a parasitic capacitance element inside the printed circuit boards 130a, 130b.

In the present embodiment, the buried capacitor of the printed circuit boards 130a and 130b is a parasitic capacitance element, but the structure of the parasitic capacitance element is not limited to the planar capacitor shown in this embodiment. In detail, the buried capacitor of FIG. 2 can also be replaced with, for example, a capacitor having an interdigitated electrode or any other capacitor formed by a patterned at least one conductive electrode.

In practical use, the test device for a semiconductor wafer according to an embodiment of FIG. 2, wherein the test probe holder 10 includes two printed circuit boards 130a, 130b and a signal layer 1314 respectively disposed on the upper surface of the printed circuit board 130a. The signal layer 1314 is disposed on the lower surface of the printed circuit board 130b. At least one dielectric layer 1312 is disposed between the printed circuit boards 130a, 130b and the signal layer 1314.

The signal layer 1314 disposed on the upper surface of the printed circuit board 130a is connected to the upper side of the at least one dielectric layer 1312, and the upper surface of the printed circuit board 130a is connected to the lower side of the at least one dielectric layer 1312. In addition, the signal layer 1314 disposed on the lower surface of the printed circuit board 130b is connected to the lower side of the at least one dielectric layer 1312, and the lower surface of the printed circuit board 130b is connected to the upper side of the at least one dielectric layer 1312.

In the above embodiment, the test probe holder 10 includes two printed circuit boards 130a, 130b and at least one dielectric layer 1312 disposed therebetween to form a multilayer printed circuit board including two planar capacitors. Preferably, the power supply layer 1311 and the ground layer 1313 of the printed circuit boards 130a and 130b are arranged in the same order. For example, the power layer 1311, the dielectric layer 1312 and the ground layer 1313 are in the printed circuit board 130a. Printed in the lower direction and printed on the printed circuit board 130a The structure of the circuit board 130b corresponds to the printed circuit board 130a, which is also arranged in the vertical direction of the power supply layer 1311, the dielectric layer 1312, and the ground layer 1313. Therefore, the plurality of printed circuit boards in which the power supply layers 1311 are alternately arranged with the ground layers 1313 are formed.

The test probe holder 10 may also be spaced apart from the plurality of dielectric layers 1312 by the plurality of printed circuit boards 130a, 130b, and may be a build-up process or stack as is well known in the art. Multilayer printed circuit board manufactured by Overlay. Stacking holes, blind holes, buried holes, through holes (plated through holes), and transmission lines (conductive circuits) are provided in the test probe holder 10 by processes such as laser drilling process, etching process, hole column plating, and build-up method. And a conventional conduction structure such as a test pad, such that a plurality of power supply layers 1311 or a plurality of ground layers 1313 are electrically connected to each other. For example, a conductive material may be used to cover the holes of the through holes 110 to form a conductive conductive wall on the wall of the holes, so that the through holes 110 have electrical conductivity.

In one embodiment, the through holes 110 are electrically connected to the power supply layers 1311 and electrically connected to the ground layer 1313 and the signal layer 1314 by an anti-pad (not shown) such as an insulating ring or an annular region. Sexual insulation. In contrast, the through holes 110 are electrically connected to the ground layers 1313 and electrically insulated from the power layer 1311 and the signal layer 1314 . In detail, some of the through holes 110 are electrically connected and partially connected to the power supply layers 1311, and some of the through holes 110 are electrically connected and partially connected to the ground layers 1313, and the power supply layers 1311 and the ground layer 1313 are mutually parallel and staggered, that is, the plurality of power supply layers 1311 disposed in parallel with each other are electrically connected to each other via the common through holes 110, and a ground layer 1313 is disposed between the upper and lower power supply layers 1311. 1313 is electrically connected to each other via another through hole 110. Thereby, a plurality of upright multi-layer planar capacitive elements can be produced in the test probe holder 10. The dielectric layer 1312 of the printed circuit board 130a, 130b is formed of a dielectric material having no conductivity or low conductivity, and common materials include, but not limited to, FR4, FR5, CEM-1, CEM-3, ISOLA, Rogers, BT, GTEK, Polyimide, Polyester Fiber, ceramic or metal/alloy, etc., so the printed circuit board can be ceramic, glass and plastic substrates. Print The material of the conductive layer 131 (including the power layer 1311, the ground layer 1313) and the signal layer 1314 of the brush circuit board may be formed of any conductive material, and may be made of copper, a copper-based material, and other metals, and among them, preferably. For copper.

Referring to FIG. 3, FIG. 3 is a schematic diagram of a test apparatus for a semiconductor wafer according to a second embodiment of the present invention. The test device 300 of the semiconductor wafer of FIG. 3 is similar in structure to the test device 200 of the semiconductor wafer of FIG. 2, and the main difference between the two is that in the second embodiment of FIG. 3, the printed circuit board 130 further includes a plurality of Discrete capacitive element 122. The discrete capacitive elements 122 are directly embedded in the test probe holder 10 and electrically connected to the conductive layers 131 to form a plurality of discrete capacitive elements 122 in the test probe holder 10.

Referring to FIG. 3, the test probe holder 10 of FIG. 3 includes a plurality of parasitic capacitance elements and a plurality of discrete capacitors 122. In practical use, the test probe holder 10 may include only a plurality of The parasitic capacitive element, or only a plurality of discrete capacitive elements 122. Alternatively, the test probe holder 10 may also include a plurality of parasitic capacitive elements and discrete capacitive elements 122. This creation is not restricted.

The present invention is characterized in that a plurality of parasitic capacitance elements and discrete capacitance elements are formed by two adjacent dielectric layers of a power supply layer and a ground layer and at least one dielectric layer disposed therebetween, and the plurality of parasitic capacitance elements and discrete The capacitive element has the same function as filtering a plurality of capacitive elements disposed on the interface panel in FIG. 1 to reduce the accuracy and stability of the power supply disturbance interference test.

The test equipment for semiconductor wafers is often processed with voltage as a signal. To reduce the impedance generated by the power supply circuit, it is necessary to reduce the loop area formed by several capacitive elements and semiconductor wafers. That is, a plurality of capacitive elements are required to be as close as possible to the semiconductor elements to reduce the current loop flowing through the capacitors, and the inductance effect generated on the entire power supply loop is eliminated through several capacitive elements to maintain voltage stability and optimize power supply integrity.

As described above, the test probe holder is provided with a plurality of parasitic capacitance elements or discrete capacitance elements, so the distance between the capacitance elements and the semiconductor wafer is relatively smaller than The distance between the plurality of capacitive elements on the panel and the semiconductor wafer, so the test device of the semiconductor wafer can provide a capacitive element closer to the semiconductor wafer to be tested to form a smaller power supply loop, and can effectively reduce capacitance and semiconductor The parasitic inductance effect of the loop area between the die pieces effectively improves the performance of the PI. In view of the fact that the test probe holder forms a limit on the size of the printed circuit board in the test probe holder, the capacitance value in the printed circuit board is limited. Therefore, in another embodiment of the present invention, the power layer and the ground layer can be adjusted through the selection of different dielectric constant materials of the dielectric layer in the printed circuit board or through the selection of the dielectric layer thickness and the number of layers. The way to achieve a specific capacitance value. In one embodiment, the dielectric layer of the printed circuit board has a dielectric constant value of, for example, 4 or more and 100 or less. However, the present invention is not limited thereto.

It is to be noted that the foregoing is only a preferred embodiment to illustrate the present invention in detail, and not to limit the scope of the present invention, and those skilled in the art will understand various changes and modifications without departing from the scope of the present invention. This creation shall be subject to the following patent application.

200‧‧‧Testing device for semiconductor wafers

10‧‧‧Test probe holder

11‧‧‧ upper surface

12‧‧‧ Lower surface

20‧‧‧Intermediate panel

30‧‧‧Semiconductor components

110‧‧‧through holes

111, 112‧‧‧ test probe

121‧‧‧Capacitive components

130a, 130b‧‧‧ Printed circuit boards

131‧‧‧ Conductive layer

132, 133‧‧‧ power circuit

1311‧‧‧Power layer

1312‧‧‧ dielectric layer

1313‧‧‧ Grounding layer

1314‧‧‧Signal layer

Claims (7)

A test device for a semiconductor wafer, comprising: a test socket, comprising: a test probe holder having an upper surface, a lower surface, and a plurality of through holes extending from the upper surface to the lower surface, wherein the upper surface is for carrying a semiconductor wafer, the test probe holder comprising: at least two conductive layers; at least one dielectric layer disposed between the conductive layers; a plurality of test probes extending through the test probe holder and protruding therefrom And a panel, wherein the test probe holder is located between the interface panel and the semiconductor wafer, and the interface panel is electrically connected to one end of the plurality of test probes. The test device for a semiconductor wafer according to claim 1, wherein at least one of the test probes is electrically connected to one of the conductive layers, and the other test probes are electrically insulated from the conductive layers. The test device for a semiconductor wafer according to claim 1, wherein the dielectric layer electrically insulates the at least two conductive layers to form a parasitic capacitance. The test device for a semiconductor wafer according to claim 1, wherein the test probe holder is a multilayer printed circuit board. The test device for a semiconductor wafer according to claim 4, wherein the multilayer printed circuit board comprises a plurality of discrete capacitive elements electrically connected to at least two conductive layers. The test device for a semiconductor wafer according to claim 1, wherein the plurality of test probes are elastic probes. The test device for a semiconductor wafer according to claim 1, wherein the test probe holder further comprises a plurality of conductive walls formed on the holes of the through holes, the conductive walls respectively contacting the test probes needle.