M430702 五、新型說明： 【新型所屬之技術領域】 本創作是有關於一種晶片封裝體，且特別是有關於一 種具有空氣腔（air cavity)與排氣孔的晶片封裝體。 【先前技術】 現今有許多具有空氣腔的晶片封裝體，例如互補式金 屬氧化物半導體影像感測器（CMOS Image Sensor，CIS， φ 以下簡稱CMOS影像感測器）。這種晶片封裝體通常具有 一封裝殼、一晶片以及一載板。封裝殼具有一容置空間， 而封裝殼與晶片皆裝設在載板上，其中封裝殼罩蓋整個晶 片，所以晶片會位在容置空間内。在封裝殼與晶片裝設在 載板上之後，容置空間内會存留空氣，並且形成一空氣腔。 封裝殼通常是利用熱固性膠體來黏合載板，因此在進 行封裝殼黏合載板的過程中，被熱固性膠體所初步黏好的 φ 封裝殼與載板皆會置入於高溫爐中，以進行加熱流程。一 般而言，封裝殼具有一排氣孔，而在上述加熱流程中，容 置空間内的空氣會受熱而膨脹，因而從排氣孔釋出。如此， 可避免熱固性膠體被熱空氣擠破。 在進行完上述加熱流程之後，通常會在排氣孔内填入 膠材。此膠材會密封排氣孔，以防止水氣或灰塵進入容置 空間中，避免晶片被水氣或灰塵所干擾。然而，一旦膠材 密封排氣孔，且晶片封裝體又置於高溫環境的話，例如對 晶片封裝體進行加熱劣化測試，則容置空間内的空氣會受 3/17 /uz 熱而祕而可能將排氣孔内膠材擦 或灰塵可從排氣孔進Μ 、1'界的水氣 【新型内容】 -置工間令’從而干擾晶片的運作。 生上—種具有排氣孔的晶片封褒體，其能減少發 生上述排軋孔内的膠材被擠出的機率。 八M430702 V. New Description: [New Technical Field] The present invention relates to a chip package, and more particularly to a chip package having an air cavity and a vent hole. [Prior Art] There are many chip packages having an air cavity, such as a complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS, hereinafter referred to as a CMOS image sensor). Such a chip package typically has a package, a wafer, and a carrier. The package has an accommodating space, and the package and the wafer are mounted on the carrier, wherein the package covers the entire wafer, so that the wafer is positioned in the accommodating space. After the package and the wafer are mounted on the carrier, air is retained in the accommodation space and an air cavity is formed. The package is usually made of a thermosetting gel to bond the carrier. Therefore, during the process of bonding the package to the carrier, the φ package and the carrier, which are initially bonded by the thermosetting colloid, are placed in a high temperature furnace for heating. Process. In general, the package has a venting opening, and in the above heating process, the air in the accommodating space is heated and expanded, thereby being released from the venting opening. In this way, the thermosetting colloid can be prevented from being crushed by hot air. After the above heating process is completed, the vent hole is usually filled in the vent hole. This glue seals the venting holes to prevent moisture or dust from entering the accommodating space and to prevent the wafer from being disturbed by moisture or dust. However, once the rubber material seals the vent hole and the chip package is placed in a high temperature environment, for example, the wafer package is subjected to a heat degradation test, the air in the accommodating space is subject to 3/17 / uz heat and may be secret. Rubbing or dusting the glue in the vent hole can be carried out from the vent hole, and the water in the 1' boundary [new content] - the work space order" interferes with the operation of the wafer. A wafer seal body having a vent hole which reduces the probability of the rubber material in the above-mentioned discharge hole being extruded. Eight
本創作提供一種I右±.L & -rx ,, a Μ、一H 6 威的日心憶體，包括-封F 片又日日月與-岔封㈣才。封裝殼包括 4 外表面的内表面、一位 卜表面、一相對 ^ ^ 位於内表面的容置槽以及一鉗气3 /、t排氣孔具有-位於外表面 水， 面的第二端口，第一丨卜 而口以及一位於内表 排气：F丨/筮 而，孔徑與第二端口的孔徑皆大於 排軋孔在第一端口與苐、於 材，填充於排氣孔内。封P勺;^外的孔徑。密封膠 框牆圍繞晶片，且晶片配置在容置槽内心其中 基於上述，由於第一端口的孔徑 大於排氣孔在第-端口與第二^一^口的孔禮皆 當本創作的晶片封裝體置 以外的孔徑’因此 ^ Φ 0，,, , ^ 、同，凰兄哙，密封膠材不易被 h出如此，本創作能減少密 ☆ 匆极 率，進而增加曰g 夕 弟力而口擠出的機 曰加曰曰片封裝體1〇〇的可靠度（r—。 5 料徵和優，職更 =，並配合所附圖式，作詳細說明二下〜 【貫施方式】 圖1A是本創作第一實施例之 圖，而圖是圖1A中3 “的俯視示意 中曰曰片封裝體的剖面示意圖。請參閱 4/17 M4JU/U2 圖1A與圖1B ’晶片封裝體100包括-封裝殼110、-晶 片120與一從封膠材13〇。封襄殼㈣具有一排氣孔刚 =及二與排氣孔MG連通的容置槽15G，其中晶片120配 且在合置槽150内’而密封勝材13〇填充於排氣孔14〇内。 封U丨〇更具有一外表面1丨2與一相對外表面11 2 的内表面114 ’其中容置槽15〇位於内表面】μ。以圖iaThis creation provides a kind of I-day ±.L & -rx,, a Μ, a H 6 Wei, the heart of the memory, including - F-film, and the sun and the moon and - seal (four). The package shell includes an inner surface of the outer surface of the outer surface, a surface of the surface, a receiving groove on the inner surface, and a gas trapping gas. The first port and the inner exhaust are: F丨/筮, and the apertures of the aperture and the second port are larger than the row of the holes at the first port, and the material is filled in the vent. Seal the P spoon; ^ outside the aperture. The sealant frame wall surrounds the wafer, and the wafer is disposed in the inner core of the accommodating groove. Based on the above, since the aperture of the first port is larger than that of the vent hole at the first port and the second port, the chip package is created by the present invention. The aperture other than the body's ^ Φ 0,,, , ^, the same, the phoenix brother, the sealant is not easy to be out of h, this creation can reduce the density ☆ rush rate, and then increase 曰g 夕弟力口口The reliability of the extruded machine 曰 曰曰 封装 封装 ( ( ( ( ( ( r r r r r r r r r r r r r 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠 可靠1A is a view of the first embodiment of the present invention, and FIG. 1A is a schematic cross-sectional view of the top view package in the top view of FIG. 1A. Please refer to 4/17 M4JU/U2 FIG. 1A and FIG. 1B 'The chip package 100 The package body 110 includes a package body 110, a wafer 120, and a slave sealant material. The package body (4) has a vent hole and a venting groove 15G communicating with the vent hole MG, wherein the wafer 120 is matched and assembled. The inside of the groove 150 is filled with the sealing material 13〇 filled in the vent hole 14 。. The sealing U 丨〇 has an outer surface 1 丨 2 and an outer surface The inner surface 114' of the surface 11 2 is in which the receiving groove 15 is located on the inner surface. μ.
只圖1 B為例’外表面112具有-頂面112t以及-連接頂 面】12t的側壁面112s，而内表面114具有容置才曹150的一 側土面152 α及一連接側壁& 152的槽平面154。側壁面 112s與1)2皆為環形的表面，且二者位在彼此相對處。頂 面]12t與槽平面】54二者也位在彼此相對處。因此，内表 面]14會相對外表面112。 在本實施例中，封裝殼可以包括一框牆116與一 蓋體】18。框牆】16圍繞容置槽.150内的晶片120,而蓋體 118連接框牆n6 ’ i且遮蓋晶片]2〇。此外，框牆丨】^具 有側壁面l!2s與152，而蓋體n8具有頂面n2t、槽平面 154以及排氣扎丨4〇。 晶片封裝體1〇〇可為一種影像感測器，例如CM〇s影 像感測器或電荷耦合元件（Charge_c〇upled以丫⑹， CCD )。因此，晶片12〇可以是互補式金屬氧化物晶片或電 荷耦合晶片，並具有一主動區122，而蓋體U8更包括一 框架n8f與一透明板材118t。 承上所述’透明板材U8t遮蓋主動區]22，而框架U8f 5/17 M430702 圍繞透明板材118t，並且與透明板材11 8t結合。例如，框 架118f可以利用熱固性膠體，例如熱固性樹脂，來與透明 板材118t結合。因此，透明板材118t裸露於頂面112t。構 成透明板材118t的材料可為聚曱基丙烯酸曱酯 (Polymethylmethacrylate，PMMA，也稱為壓克力，Acrylic ) 或玻璃等透明材料，因此一般人可從透明板材118t看見晶 片120的主動區122。 晶片封裝體100可以更包括一線路基板190，而線路 基板190用來承載晶片120。詳細而言，線路基板190包 括一絕緣層170與一配置在絕緣層170上的線路層180, 其中晶片120可採用打線接合（wire bonding )的方式裝設 在線路基板190上以及電性連接線路層180，如圖1B所 示。不過，在其他實施例中，晶片120也可採用覆晶（flip chip )方式裝設在線路基板190上及電性連接線路層180。 因此，圖1B所示的晶片120裝設在線路基板1 90上的方式 僅供舉例說明，並非限定本創作。 另外，在圖1A與圖1B以外的實施例中，線路基板190 可僅包括一層線路層180，而不包括任何絕緣層170。例 如，線路層180可先製作在承載板（未繪示）上，而晶片 120被膠體（未繪示）所包覆，其中膠體能與線路層180 結合。在膠體與線路層180結合之後，利用剝離（peeling ) 或I虫刻（etching )等方法來去除承載板。如此，在沒有絕 緣層170情況下，晶片120仍可電性連接線路層180，所 M430702 以圖1B所示的絕緣々17〇僅供舉例說明，並非限定本創作。 請麥照圖1B與圖1C’圖⑴是圖m在虛圓處的放大 示意圖。排氣孔140為一種通孔（th_gh h〇le )，並具有_ 位在外表面112的第·-端σ 14Ga與—位在内表面ιΐ4的第 二端口 140b，所以排氣孔⑽會裸露於外表面ιΐ2。以圖 】B與圖1C為例’排氣孔14〇裸露於頂面仙。此外，第 知口 140a的孔役w與第二端口 14〇b的孔徑皆大於 排氣孔140在第-端口 14〇a與第二端口屬以外的孔 徑’所以排氣孔H0白勺二端端口（即第一端口 i4〇a與第二 端口 140b)的孔徑最大。 請參閱目ic，在本實施例中，封裝殼n〇具有一位於 排氣孔140内的凸緣142，且凸緣142位在第-端口】4〇a 與第二端口 14〇b之間，並且凸出於排氣孔的壁面144。 凸緣142具有一連接於第一段孔〜面的第一環形平面 ⑷a’與-相連於第二段孔？2壁面的内環曲面⑽，直 中第一環形平面仙相連於第—段孔P1的壁面盘内環曲 面之間。此外，凸、缘⑷與排氣孔14〇二者皆可以利 用模内射出成型的方式來形成。 凸緣142將排氣孔14〇區分為一第一段孔 段孔P2’其中第-段孔ρι具有第一端口 ]術，而第二: 孔P2具有第二端口】4〇b。第一段孔…的孔徑可從第一端 口 140a朝向⑽142而漸缩，而第二段孔p2的孔巧也可 從第二端ϋ 1働朝向凸緣⑷而漸縮。此外，第Γ段孔 7/17 M430702 P1的冰度D1與第二段孔p2的深度D2的比值可以是任意 值，例如在較佳實施例令，深度D1與深度D2的比值可以 介於0.7至2之間，所以深度⑴可以等於、大於或小於深 度D2。有關深度D1與深度D2的比值，在此強調，以上 所述的永度D1與深度D2的比值（即介於Q 7至2之間的 比值）僅作為舉例說明，並非限定本創作。 基於上述，由於封裝殼】所具有的排氣孔140與容 置;^ 150連通，且排氣孔14〇裸露於外表面】a，因此在 利用熱固性膠體將封裝殼11〇黏合於線路基板】9〇 (或承 載板）的過程中，當加熱被熱固性膝體所初步黏好的封裝 殼H〇與線路基板190 (或承載板）時，位在容置槽150 内的氣體（例如空氣）會受熱膨脹.，並且從排氣孔刚釋 出。、如此’排氣孔140能防止封裝殼11〇與線路基板19〇 (或承載板）之間的熱固性膠體被上述氣體擠破。 在熱固性膠體受熱而固化後，封裝殼11〇與線路基板 190 (或承載板）二者得以結合在一起。此時，從第一端口 HOa填入密封勝材13〇,以密封排氣孔14()。密封膠材w 在填入排氣孔140的時候為流體，也就是說，密封膠材13〇 可隨著排氣孔 狀。 140内的空間形狀不同而改變成不同的形 由於第-段孔P1的孔徑可從第一端口 14如朝向凸緣 而漸縮，因此處於流體狀態的密封膠材丨3〇會受到重 力的影響’以至於從第一端口 140a進入的密封膠二〇可 8/17 M430702 以附著於壁面144，且沿著第一段孔P1的壁面144朝向凸 緣142匯集。所以，密封膠材130能充滿位在凸緣142處 的排氣孔140，從而密封排氣孔140。由此可知，第一段孔 P1的結構能減緩密封膠材130的流速，以避免密封膠材130 直接滴入容置槽150。 當密封膠材130通過凸緣142之後，受到重力的影響， 密封膠材130能沿著第二段孔P2的壁面144繼續朝向第二 端口 140b流動。因此，在密封膠材130固化之後，密封膝 鲁材130凸出於内表面114，並凹陷於外表面112 (例如頂面 112t)’如圖1C所示。 密封膠材130可以是熱固性膠體或熱固性膠體以外的 可固化性膠體，而在本實施例中’密封膠材13〇可以是一 種光固化膠體，其例如是紫外光（Ultraviolet，UV)固化 膠。因此’待密封膠材130將排氣孔140密封後，可從第 一端口 140a照射紫外光，使密封膠材丨3〇產生不可逆的固 鲁化反應並於排氣孔140内形成固體。如此’固化後密封膠 材130不再隨溫度變化而改變型態，從而能防止水氣或灰 塵等異物進入容置槽150中’以避免干擾晶片120的運作。 在密封膠材130固化並密封排氣孔丨4〇之後，若是將 晶片封裝體100置於高溫環境的話，例如對晶片封裝體1 〇〇 進行後續的加熱劣化測试’則容置槽15 0内的空氣會受熱 而膨脹，並推擠位在排氣孔140内的密封膠材130。 由於第二段孔P2之孔徑可從第二端口抖沘朝向凸緣 9/17 M430702 142而漸縮’因此當容置槽丨5〇内的熱空氣推擠密封膠材 130時，密封膠材130會壓迫第二段孔P2内的壁面144， 而第二段孔p2内的壁面144會施於反作用力於密封膠材 13〇，從而阻礙密封膠材13〇朝向第一端口 14〇a移動。如 此，可減少密封膠材13〇從第一端口 14〇a擠出的機率，進 而增加晶片封裝體10〇的可靠度（reliability)。 圖2是本創作第二實施例之晶片封裝體的剖面放大示 意圖。請比較圖1C與圖2,本實施例的晶片封裝體2〇〇與 第一實^例的晶片封裝體相似，例如晶片封裝體 與200二者功效相似，且也包括一些相同的元件，惟二者 的差異在於：晶片封裝體200所包括的封裝殼21〇，其結 構不同於封裴殼110。 請參閱圖2，封裝殼210具有一排氣孔24〇以及一位 於排氣孔240内的凸緣242，其中凸緣242具有第一環形 ，面242a、—内環曲面242c與一第二環形平面242b。與 第一實施例相同地，凸緣242將排氣孔240區分為第一段 孔P3與第二段孔P4，其中第一段孔j>3具有 一 第二段_具有第二端口鳩。、^ 然而’與第一實施例不同的是，凸緣242具有第一環 形平面242a，且第—環形平面242a相連在第一段孔P3的 壁面與内每曲面242e之間，而第二環形平面242b相連在 第一段孔P4的壁面與内環曲面242c之間。也就是說，第 裱形平面242a與第二環形平面242b相對，且連接於内 10/17 M430702 環曲面242c的兩側。 由此可知，在密封膠材130固化並密封排氣孔24〇之 後，凸緣242會嵌入於密封膠材13〇中，以至於密封膠材 會穩固地配置在排氣孔240内。如此，當晶片封裝體 2〇〇處於高溫環境時，凸緣242可以阻礙密封膠材】％移 動，以減少密封料13M皮擠出的機率，$而大幅增加晶 片封裝體200的可靠度。 S 3曰 立圖3是本創作第三實施例之晶片封裝體的剖面放大示 意圖。請比較圖1C與圖3,本實施例的晶片封裝體3齡 弟一貫施例的晶片封裝體相似，例如晶片封裝體_ 與、30田0Γ者功效相似，且也包括一些相同的元件，惟二者 的是異在於：晶片封裝體300所包括的封裝殼310’其結 構不同於封裝殼1 ]〇。 以σ 請參閱圖3,封裝殼310具有一排氣孔34 蝴可區分為第一段孔Ρ5與第二段孔ρ6，其中第」: =广Ρ6二者的壁面彼此相連，即排氣孔在 此外又盘第二段孔Ρ6連接處的壁面344彼此相連。 此外，與弟—實施例不同的是，封 凸緣。即使封裝殼310沒有任何凸緣%具有任何 膠材U0時，第-严 田…工虱推擠密封 I—，從 機率。 文弟鳊口】4〇a擠出的 综上所述 當 本創作的晶片封I體置於高溫環境時， 11/17 M430702 雖然密封膠材會被容置槽内的熱空氣推擠 具有的排氣孔，其壁面會阻礙密封膠材移動。如此、， ==密封膠材―率，增力…封 =上所述，僅為本創作的具體實施例知詳細說 疋而已，並非用以限定本創作，本創 巴 述之申請專利範圍為準，任何孰―枯：有耗圍應以下 領域内，可以變化或是修飾皆可==本創作之 申請專利範圍。 本木所界定之 L圖式簡單說明】 圖1Α是本創作第一實施例之晶 〜a日乃封裝體立 圖1B是圖1A中晶片封裝體的剖面示意圖。、不思圖 圖1C是圖1B在虛圓處的放大示音曰 · 圖2疋本創作第一貫施例之晶只去 圖。 曰曰片封裝體的剖面放大示 封裝體的剖面放大示意 晶片封裝體 封裝殼 外表面 頂面 圖3是本創作第三實施例之晶片 圖。 【主要元件符號說明】 100 、 200 、 300 110 、 210 、 310 112 112t 12/17 M430702Only FIG. 1B is a side wall surface 112s of the outer surface 112 having a top surface 112t and a top surface 12t, and the inner surface 114 has a side surface 152α for accommodating the core 150 and a connecting side wall & Slot plane 154 of 152. The side wall faces 112s and 1) 2 are both annular surfaces, and the two are located opposite each other. The top surface 12t and the groove plane 54 are also located opposite each other. Therefore, the inner surface 14 will be opposite the outer surface 112. In this embodiment, the package can include a frame wall 116 and a cover 18 . The frame wall 16 surrounds the wafer 120 in the receiving slot 150, and the cover 118 connects the frame wall n6'' and covers the wafer]2. In addition, the frame wall has a side wall surface l! 2s and 152, and the cover body n8 has a top surface n2t, a groove plane 154, and an exhaust shovel. The chip package 1 can be an image sensor such as a CM 〇s image sensor or a charge coupled device (Charge_c〇upled 丫(6), CCD). Therefore, the wafer 12A may be a complementary metal oxide wafer or a charge coupled wafer and has an active region 122, and the cover U8 further includes a frame n8f and a transparent plate 118t. The 'transparent sheet U8t covers the active area' 22 is attached, and the frame U8f 5/17 M430702 surrounds the transparent sheet 118t and is combined with the transparent sheet 11 8t. For example, the frame 118f may be bonded to the transparent sheet 118t using a thermosetting colloid such as a thermosetting resin. Therefore, the transparent plate 118t is exposed to the top surface 112t. The material constituting the transparent plate 118t may be a transparent material such as polymethylmethacrylate (PMMA, also known as Acrylic) or glass, so that the active region 122 of the wafer 120 can be generally seen from the transparent plate 118t. The chip package 100 may further include a circuit substrate 190 for carrying the wafer 120. In detail, the circuit substrate 190 includes an insulating layer 170 and a wiring layer 180 disposed on the insulating layer 170. The wafer 120 can be mounted on the circuit substrate 190 and electrically connected by wire bonding. Layer 180 is shown in Figure 1B. However, in other embodiments, the wafer 120 may also be mounted on the circuit substrate 190 and electrically connected to the circuit layer 180 by a flip chip. Therefore, the manner in which the wafer 120 shown in Fig. 1B is mounted on the circuit substrate 1 90 is for illustrative purposes only and is not intended to limit the creation. In addition, in the embodiment other than FIGS. 1A and 1B, the wiring substrate 190 may include only one wiring layer 180 without including any insulating layer 170. For example, the circuit layer 180 can be fabricated on a carrier board (not shown), and the wafer 120 is covered by a colloid (not shown), wherein the glue can be bonded to the circuit layer 180. After the colloid is combined with the wiring layer 180, the carrier sheet is removed by a method such as peeling or etching. Thus, in the absence of the insulating layer 170, the wafer 120 can still be electrically connected to the wiring layer 180. The insulating layer 17 shown in FIG. 1B is used for illustration only, and is not intended to limit the creation. Please refer to Fig. 1B and Fig. 1C' (1) for an enlarged view of Fig. m at the imaginary circle. The vent hole 140 is a through hole (th_ghh〇le) and has a second port 140b located at the first end σ 14Ga of the outer surface 112 and the inner surface ι 4, so the vent hole (10) is exposed The outer surface is ιΐ2. Taking Fig. B and Fig. 1C as an example, the vent hole 14 is exposed to the top surface. In addition, the apertures of the apertures w and the second ports 14〇b of the first port 140a are larger than the apertures of the exhaust holes 140 outside the first port 14〇a and the second port, so the two ends of the exhaust hole H0 The apertures of the ports (ie, the first port i4〇a and the second port 140b) are the largest. Referring to the above, in the embodiment, the package casing 〇 has a flange 142 located in the vent hole 140, and the flange 142 is located between the first port 4 〇 a and the second port 14 〇 b And protrudes from the wall 144 of the vent. The flange 142 has a first annular plane (4) a' connected to the first section of the hole-to-face and is connected to the second section of the hole. 2 The inner ring curved surface (10) of the wall, the straight first first annular flat surface is connected between the inner ring curved surfaces of the first-stage hole P1. Further, both the convex portion, the edge (4) and the vent hole 14 can be formed by in-mold injection molding. The flange 142 divides the vent hole 14 为 into a first segment hole hole P2' in which the first segment hole ρι has the first port, and the second: hole P2 has the second port 〇 4 〇 b. The aperture of the first segment of the aperture ... can taper from the first port 140a toward the (10) 142, and the aperture of the second segment of the aperture p2 can also taper from the second end ϋ 1 働 toward the flange (4). In addition, the ratio of the ice degree D1 of the third-stage hole 7/17 M430702 P1 to the depth D2 of the second-stage hole p2 may be an arbitrary value. For example, in a preferred embodiment, the ratio of the depth D1 to the depth D2 may be 0.7. Between 2, so the depth (1) can be equal to, greater than or less than the depth D2. Regarding the ratio of the depth D1 to the depth D2, it is emphasized here that the ratio of the permanent D1 to the depth D2 described above (i.e., the ratio between Q 7 and 2) is merely illustrative and does not limit the creation. Based on the above, since the vent hole 140 has the vent hole 140 and the accommodating portion 150, and the vent hole 14 〇 is exposed on the outer surface 】 a, the package case 11 〇 is bonded to the circuit substrate by using the thermosetting colloid] In the process of 9 〇 (or carrier plate), when the package H 〇 and the circuit substrate 190 (or carrier plate) which are initially adhered by the thermosetting knee body are heated, the gas (for example, air) located in the accommodating groove 150 is heated. Will be thermally expanded. And just released from the vent. Thus, the vent hole 140 prevents the thermosetting colloid between the package case 11 and the circuit substrate 19 (or the carrier plate) from being crushed by the above gas. After the thermosetting colloid is cured by heat, the package 11's and the wiring substrate 190 (or the carrier) are bonded together. At this time, the sealing material 13 is filled from the first port HOa to seal the vent hole 14 (). The sealant w is fluid when it is filled into the vent hole 140, that is, the sealant 13 〇 can follow the vent hole. The shape of the space in 140 is changed to a different shape. Since the aperture of the first-stage hole P1 can be tapered from the first port 14 toward the flange, the sealing material 丨3〇 in the fluid state is affected by gravity. So that the sealant enters 8/17 M430702 entering from the first port 140a to adhere to the wall surface 144 and is collected toward the flange 142 along the wall surface 144 of the first length of the hole P1. Therefore, the sealant 130 can be filled with the vent hole 140 at the flange 142, thereby sealing the vent hole 140. Therefore, the structure of the first hole P1 can slow down the flow rate of the sealant 130 to prevent the sealant 130 from directly dropping into the accommodating groove 150. After the sealant 130 passes the flange 142, the sealant 130 can continue to flow toward the second port 140b along the wall 144 of the second length of aperture P2, as a result of gravity. Thus, after the sealant 130 is cured, the seal knee 130 protrudes from the inner surface 114 and is recessed into the outer surface 112 (e.g., top surface 112t) as shown in Figure 1C. The sealant 130 may be a curable colloid other than a thermosetting colloid or a thermosetting colloid, and in the present embodiment, the sealant 13 may be a photocurable colloid such as an ultraviolet (UV) curable adhesive. Therefore, after the sealing material 130 seals the vent hole 140, ultraviolet light can be irradiated from the first port 140a to cause an irreversible refining reaction of the sealing material 并3, and a solid is formed in the vent hole 140. Thus, after the curing, the sealing material 130 is no longer changed in shape with temperature change, so that foreign matter such as moisture or dust can be prevented from entering the accommodating groove 150 to avoid interfering with the operation of the wafer 120. After the sealant 130 is cured and the vent hole 密封 is sealed, if the chip package 100 is placed in a high temperature environment, for example, the wafer package 1 〇〇 is subjected to a subsequent heat degradation test ‘the accommodating groove 150 The air inside is expanded by heat and pushes the sealant 130 positioned in the vent 140. Since the aperture of the second section of the hole P2 can be tapered from the second port to the flange 9/17 M430702 142, so when the hot air in the receiving groove 5〇 pushes the sealing material 130, the sealing material 130 will press the wall surface 144 in the second section of the hole P2, and the wall surface 144 in the second section of the hole p2 will exert a reaction force on the sealing material 13〇, thereby hindering the movement of the sealing material 13〇 toward the first port 14〇a. . Thus, the probability of the sealing material 13 挤出 being extruded from the first port 14 〇 a can be reduced, thereby increasing the reliability of the chip package 10 〇. Fig. 2 is an enlarged cross-sectional view showing the chip package of the second embodiment of the present invention. 1C and FIG. 2, the chip package 2 of the present embodiment is similar to the chip package of the first embodiment. For example, the chip package and the 200 are similar in function, and also include some identical components. The difference between the two is that the package package 21 included in the chip package 200 has a structure different from that of the package case 110. Referring to FIG. 2, the package housing 210 has a venting opening 24 and a flange 242 located in the venting opening 240. The flange 242 has a first annular shape, a surface 242a, an inner ring curved surface 242c and a second portion. Annular plane 242b. As in the first embodiment, the flange 242 divides the vent hole 240 into a first segment hole P3 and a second segment hole P4, wherein the first segment hole j > 3 has a second segment _ having a second port 鸠. However, 'unlike the first embodiment, the flange 242 has a first annular plane 242a, and the first annular plane 242a is connected between the wall surface of the first section hole P3 and the inner surface 242e, and the second The annular plane 242b is connected between the wall surface of the first segment hole P4 and the inner ring curved surface 242c. That is, the first circular plane 242a is opposed to the second annular plane 242b and is coupled to both sides of the inner 10/17 M430702 annular curved surface 242c. It can be seen that after the sealant 130 is cured and the vent hole 24 is sealed, the flange 242 is embedded in the sealant 13 so that the sealant is stably disposed in the vent 240. Thus, when the chip package 2 is in a high temperature environment, the flange 242 can hinder the sealing material from being % moved to reduce the probability of the sealing material 13M being extruded, and the reliability of the wafer package 200 is greatly increased. Fig. 3 is an enlarged cross-sectional view showing the chip package of the third embodiment of the present invention. Please compare FIG. 1C with FIG. 3, the chip package of the embodiment of the present invention is similar to the chip package of the same embodiment, for example, the chip package _ is similar to the 30 Γ Γ, and also includes some of the same components. The difference between the two is that the package body 310 included in the chip package 300 has a structure different from that of the package case 1 . Referring to FIG. 3, the encapsulating shell 310 has a venting opening 34. The butterfly can be divided into a first section of the aperture 5 and a second section of the aperture ρ6, wherein the walls of the second: Ρ6 are connected to each other, that is, the venting opening. In addition, the wall faces 344 at the junction of the second segment of the disk 6 are connected to each other. Further, unlike the embodiment, the flange is sealed. Even if the encapsulating shell 310 does not have any flange % with any glue U0, the first - sturdy ... pushes the seal I -, from the probability. Wendi 鳊口] 4〇a extrusion in summary, when the created wafer seal I body is placed in a high temperature environment, 11/17 M430702 although the sealant will be pushed by the hot air in the accommodating tank The vent hole has a wall that prevents the sealant from moving. Thus, the == sealant material-rate, booster, seal, and the above description are only for the detailed description of the specific embodiment of the present invention, and are not intended to limit the creation. The patent application scope of the present invention is Quasi-, any 孰---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a first embodiment of the present invention. FIG. 1B is a cross-sectional view of the chip package of FIG. 1A. FIG. Fig. 1C is an enlarged view of Fig. 1B at the imaginary circle. Fig. 2 shows the crystal of the first embodiment of the present invention. Cross-sectional view of the package of the chip package is enlarged. Outline of the package. Chip package Package case External surface Top surface Fig. 3 is a wafer diagram of the third embodiment of the present invention. [Main component symbol description] 100, 200, 300 110, 210, 310 112 112t 12/17 M430702
112s > 152 側壁面 114 内表面 116 框牆 118 蓋體 118f 框架 118t 透明板材 120 晶片 122 主動區 130 密封膠材 140、2M、340 排氣孔 140a 、 240a 第一端口 140b ' 240b 第二端口 142 ' 242 凸緣 142a、242a 第一環形平面 142b 、 242c 内環曲面 144 、 344 壁面 150 容置槽 154 槽平面 170 絕緣層 180 線路層 190 線路基板 242b 第二環形平面 P卜 P3、P5 第一段孔 13/17 M430702 P2 、 P4 、 P6 第二段孔 D1 ' D2 深度 R1、R2 孔徑 14/17112s > 152 Side wall surface 114 Inner surface 116 Frame wall 118 Cover 118f Frame 118t Transparent sheet 120 Wafer 122 Active area 130 Sealant 140, 2M, 340 Vents 140a, 240a First port 140b '240b Second port 142 ' 242 flanges 142a, 242a first annular plane 142b, 242c inner ring curved surface 144, 344 wall surface 150 receiving groove 154 groove plane 170 insulating layer 180 circuit layer 190 circuit substrate 242b second annular plane P P3, P5 first Segment hole 13/17 M430702 P2, P4, P6 Second section hole D1 ' D2 Depth R1, R2 Aperture 14/17