TWI553797B - Lid-pressing type semiconductor package and method for manufacturing the same - Google Patents

Description

Capped stamped semiconductor package structure and method of manufacturing same

The present invention relates to the field of semiconductor package in the form of two substrates, and particularly relates to a capped laminated semiconductor package structure and a manufacturing method thereof, which can be applied to an image sensing wafer, an optoelectronic wafer, a microelectromechanical wafer, an integrated circuit. Wafer encapsulation technology for wafers, etc., and can be applied to Chip Scale Package (CSP), Fan-Out Wafer Level Package (FOWLP), and ball grid array package structure (BGA package) ) and other package types.

In industrial manufacturing, press-bonding of two substrates is a technique that is extremely commonly used. In the semiconductor packaging process, related technologies are also used. Different industries, depending on the product requirements, the two rigid substrates that need to be bonded and bonded may be glass-to-wafer bonding, or may be wafer-to-wafer pressing. The bonding of the glass-to-wafer or panel-type semiconductor package sheet, the bonding of two wafers or panel-type semiconductor package sheets of the same size, and the press-fitting of the metal heat sink to the wafer are different. Generally, a substrate pressing surface provided with an active element is formed as a non-flat surface, and another substrate pressing surface pressed thereon is formed into a flat surface, and the adhesive layer is not easy to flow uneven portions of the non-flat surface, so Produces irregular and uncontrolled pores on non-flat surfaces. After the substrate is pressed, the semiconductor package process may be followed by crystal back grinding, drilling, After the process steps of vapor deposition, electroplating, etching, mold-sealing, singulation, etc., irregular pores may cause an enlargement of a large area of ineffective adhesive regions, resulting in an increase in defective packages.

It is known that the press bonding of a wafer containing a CIS image sensing wafer to a glass sheet requires the use of a patterned adhesive layer. When the surface height difference of the wafer active surface is larger, the adhesion layer between the wafer and the glass sheet is more likely to form voids. The factors affecting the surface height drop may be the pattern opening of the surface protective layer, the pad, the microlens, the color filter or the dicing itself itself (precut sag).

In order to solve the above problems, the main object of the present invention is to provide a capped laminated semiconductor package structure and a manufacturing method thereof, thereby preventing generation of irregular voids between two stacked press plates, thereby eliminating agglomerates in the post-packaging process. The formation of large areas of ineffective adhesive areas is possible.

A second object of the present invention is to provide a capped press-fit semiconductor package structure and a method of fabricating the same, which can be designed to meet the gap between different regions to improve the gap generation after the press-fitting is completed by different adhesive layer shape designs.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a capped laminated semiconductor package structure comprising an element substrate, an adhesive layer and a stack of pressure plates. The element substrate has a non-flat surface on which a plurality of convex regions are formed. The adhesive layer is formed on the non-flat surface, and the adhesive layer covers the convex regions, and the adhesive layer is a pressed front view Forming a plurality of first airbag apertures, the first airbag apertures are arranged not to overlap the convex regions and are arranged around the convex regions, or in different embodiments, the adhesive layer covers a concave region And aligning the first airbag holes with the convex regions. The laminated plate has a flat surface, and the flat surface is pressed against the non-flat surface such that the laminated plate is adhered to the adhesive layer on the element substrate, wherein the adhesive layer is first adhered to one of the non-flat surfaces The area is greater than the second adhesion area of the adhesive layer to one of the flat faces. The present invention further discloses a method of fabricating the above-described capping-type semiconductor package structure.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the above-mentioned capping-type semiconductor package structure, the non-flat surface may include a component mounting region, and the adhesive layer may further have a window-shaped hole to expose the component mounting region, and the adhesive layer may have a plurality of The second airbag apertures may be arranged around the window apertures without overlapping the component placement area.

In the capping-fit semiconductor package structure, the component mounting region may include a plurality of image sensing components, and the laminated plate may be a light transmissive sheet.

In the capping-fit semiconductor package structure, the component mounting region may be formed on a first recessed area of the component substrate, and the periphery of the non-flat surface may be formed as a second recessed region, the second recessed region The system is further recessed in the first recessed area.

In the capping-type semiconductor package structure, the lands may be formed by a plurality of protruding electrodes, and the device substrate may further have a plurality of longitudinal conducting mechanisms, wherein the one of the component substrates is non-compressed Sexual conduction to these prominent electrode.

In the capping-type semiconductor package structure, the device substrate may be selected from the group consisting of an image sensing wafer, an optoelectronic chip, a microelectromechanical wafer, a wafer size package, a fan-out wafer level package, an integrated circuit substrate, and One of the circuit substrates, the laminated plate may be selected from one of a glass sheet, a metal sheet, a wafer and a pre-formed wafer body.

In the capping-fit semiconductor package structure described above, the first balloon holes are specifically elliptical holes.

In the capping-fit semiconductor package structure, the air pressure in the first air bag holes may be no more than one atmosphere.

According to the above technical means, in a specific application, the present invention can understand different regions on the first substrate such as a device wafer, which are non-flat surfaces including active components, such as wafer active. The design of the adhesive layer of the highest or non-recessed area is designed as an opening through the design of the reticle, and the opening of the special pattern is not required in the lowest or lower concave area. Before the substrate bonding step of the semiconductor packaging process, the adhesive layer such as the film may be attached to the non-flat surface of the first substrate such as the device wafer, or the adhesive layer may be covered by spin coating. On the device wafer, through the yellowing process of exposure and development, the adhesive layer pattern covering different heights and positions is developed, and further, the glass can be pressed onto the adhesive layer, because the adhesive layer is viscous and flowing. Therefore, when the pressing is performed, the difference between the height of the original device wafer and the pattern of the adhesive layer can be well covered, and no voids are generated.

10‧‧‧First substrate

11‧‧‧ cutting road

20‧‧‧second substrate

100‧‧‧Capped press-fit semiconductor package construction

110‧‧‧ element substrate

111‧‧‧ non-flat surface

112‧‧‧ convex area

113‧‧‧Component setting area

114‧‧‧First pit

115‧‧‧second recess

116‧‧‧Non-pressed surface

117‧‧‧Longitudinal conduction mechanism

118‧‧‧ Conductive metal layer

119‧‧‧ protruding electrode

120‧‧‧Adhesive layer

121‧‧‧First airbag hole

122‧‧‧Second airbag hole

123‧‧‧Window hole

130‧‧‧Laminated plate

131‧‧‧flat surface

141‧‧‧Insulation

142‧‧‧ facing the protective layer

143‧‧‧Back protective layer

150‧‧‧External terminals

151‧‧‧Electrical bonding layer

200‧‧‧Capped press-fit semiconductor package construction

215‧‧‧ recessed area

221‧‧‧First airbag hole

260‧‧‧ Sealant

1 is a cross-sectional view showing a capped laminated semiconductor package structure in accordance with a first preferred embodiment of the present invention.

2 is a top plan view of an adhesive layer of the capped press-fit semiconductor package structure on a non-flat surface in accordance with a first preferred embodiment of the present invention.

3A to 3K are views showing a cross-sectional view of an element in each main step of the method of manufacturing the capped laminated semiconductor package structure according to a first preferred embodiment of the present invention.

Figure 4 is a top plan view of the component of the adhesive layer covering area in Figure 3C, in accordance with a first preferred embodiment of the present invention.

Figure 5 is a cross-sectional view showing another capped laminated semiconductor package structure in accordance with a second preferred embodiment of the present invention.

Figure 6 is a top plan view showing the adhesive layer of the captive laminated semiconductor package structure on a non-flat surface in accordance with a second preferred embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. Number, shape and size of actual implementation The ratio is an optional design, and the detailed component layout may be more complicated.

In accordance with a first preferred embodiment of the present invention, a capped press-fit semiconductor package structure 100 is illustrated in a cross-sectional view of FIG. 1 and a top plan view of the adhesive layer of FIG. 2 on a non-flat surface. The capped press-fit semiconductor package structure 100 includes an element substrate 110, an adhesive layer 120, and a stack of press plates 130.

Referring to FIG. 1 , the element substrate 110 has a non-flat surface 111 on which a plurality of convex regions 112 are formed. The laminated plate 130 has a flat surface 131. The component substrate 110 can be selected from one of an image sensing wafer, an optoelectronic wafer, a microelectromechanical wafer, a wafer size package, a fan-out wafer level package, an integrated circuit substrate, and a circuit substrate. The 130 series may be selected from one of a glass sheet, a metal sheet, a wafer, and a pre-formed wafer body. In the embodiment, the element substrate 110 is an image sensing wafer, and the laminated plate 130 is a glass piece.

Generally, the element substrate 110 includes an active element such as an integrated circuit, an image sensing element, a photoelectric element, or a microelectromechanical element, which is formed in one of the element setting regions 113 of the non-flat surface 111, and in particular, the element setting region 113 The image sensing component can be a plurality of micro-mirror structures, and the lamination plate 130 can be a light transmissive sheet. Therefore, the uneven surface 111 is not flattenable. The main system of the component substrate 110 can be a semiconductor substrate. In this embodiment, in addition to the active component, the non-planar surface 111 is further formed with an inner insulating layer 141, a protective layer 142, and a plurality of pads. The flat surface 111 has regions of different heights.

The lands 112 may be formed by the protruding electrodes 119, for example, protruding from the plurality of pads facing the protective layer 142 for power supply detection. more detail The component placement region 113 is formed on one of the first recesses 114 of the component substrate 110. The periphery of the non-planar surface 111 is formed as a second recess 115, and the second recess 115 is further recessed. In the first recess 114.

The element substrate 110 can further have a plurality of longitudinal conduction mechanisms 117, such as conductive vias, electrically connected to the protruding electrodes 119 by one of the non-compression surfaces 116 of the element substrate 110. In the present embodiment, the longitudinal conduction mechanisms 117 are meandering through holes (TSV). The non-pressing surface 116 is formed with a conductive metal layer 118 electrically connected to the longitudinal conducting mechanisms 117. For example, an insulating back protective layer 143 covers the lines of the non-compression surface 116 and the conductive metal layer 118, but does not cover the connection pads of the conductive metal layer 118. A conductive bonding layer 151 is further formed on the connection pad of the conductive metal layer 118 for bonding a plurality of solder balls to the terminal 150, or an IC control wafer or a memory chip may be bonded to the conductive metal layer 118. Connection pad.

Referring to FIGS. 1 and 2, the adhesive layer 120 is formed on the non-flat surface 111, and the adhesive layer 120 is a photosensitive adhesive. The adhesive layer 120 covers the convex regions 112. The adhesive layer 120 is patterned before pressing and has a plurality of first airbag holes 121. The first airbag holes 121 do not overlap the convex regions 112. Arranged around the lands 112 (as shown in FIG. 2). The first airbag holes 121 have the functions of preventing irregular expansion of the pressing pores and absorbing sudden stresses, and more importantly, are close to the convex regions 112, and the first airbag holes 121 are adjacent to the convex regions 112. The horizontal distance should not be greater than the length or width of the convex regions 112 in the same horizontal direction. When more than two convex regions 112 are arranged, at least one first airbag hole 121 can be disposed on Between the two convex regions 112 (as shown in Fig. 2). In this embodiment, the first airbag holes 121 may be elliptical holes, so that the effect of pore and stress absorption is better. After the pressure bonding, the air pressure in the first airbag holes 121 may be no more than one atmosphere, and the adsorption effect of the adhesive layer 120 on the laminated plate 130 and the pore air on the adhesive surface above the convex regions 112 may be increased. . In this embodiment, the air pressure in the first airbag holes 121 is about 0.001 mBar.

Referring to FIG. 1 , the flat surface 131 is pressed against the non-flat surface 111 such that the laminated plate 130 is adhered to the adhesive layer 120 on the element substrate 110 , wherein the adhesive layer 120 is opposite to the non-flat surface 111 . A first adhesive area is greater than a second adhesive area of the adhesive layer 120 to the flat surface 131.

Referring to FIGS. 1 and 2, the adhesive layer 120 may further have a window-shaped opening 123 for exposing the component setting area 113. The adhesive layer 120 may further include a plurality of second airbag holes 122, and the second The airbag holes 122 may be arranged around the window-shaped holes 123 without overlapping the element setting region 113 (as shown in Fig. 2). The second airbag holes 122 may also be oval holes. The air pressure in the second airbag holes 122 may not be greater than one atmosphere, and the adsorption effect of the adhesive layer 120 on the laminated plate 130 and the pore air on the adhesive surface of the component mounting region 113 may be increased.

Therefore, the present invention provides a capping-type semiconductor package structure and a manufacturing method thereof for preventing irregular pores between two stacks of press plates, thereby eliminating the possibility of formation of large-sized ineffective adhesive regions in a post-packaging process. .

The manufacturing method of the capping-type semiconductor package structure 100 described above is as follows, and the 3A to 3K drawings are shown in the capped press-fit semiconductor package. A cross-sectional view of the elements of each of the main steps in the manufacturing method of the manufacturing method of FIG. 3, and FIG. 4 is a top view of the elements of the area covered by the adhesive layer 120 in FIG. 3C.

First, referring to FIG. 3A, a first substrate 10 is provided, which includes a plurality of integrally connected component substrates 110. The component substrates 110 have a non-flat surface 111, and the non-flat surface 111 is formed with a plurality of convexities. Area 112. The plurality of dicing streets 11 are formed between the element substrates 110. The first substrate 10 can be a semiconductor wafer, a wafer type semiconductor package sheet or a panel type semiconductor package sheet. In this embodiment, the first substrate 10 is a device wafer of a CMOS image sensor. More specifically, the non-flat surface 111 is further formed with a plurality of first recessed regions 114 and at least one second recessed region 115. The plurality of component-arranged regions 113 of the component substrate 110 are formed in the corresponding first recessed regions 114. The second recess 115 is formed on the periphery of the element substrates 110. The second recess 115 is further recessed in the first recesses 114. The second recess 115 extends further to a plurality of dicing streets 11 between the element substrates 110.

Thereafter, referring to FIG. 3B, an adhesive layer 120 is formed on the non-flat surface 111 by film attaching, spin coating or printing, and the adhesive layer 120 covers the convex regions 112. .

Thereafter, referring to FIGS. 3C and 4, a pair of pre-pressing patterning operations of the adhesive layer 120, such as exposure and development, are performed such that the adhesive layer 120 has a plurality of first airbag holes 121. When the adhesive layer 120 covers the convex regions 112, the first airbag holes 121 are not overlapped with the convex regions 112 and are arranged around the convex regions 112. In addition, in this step, the adhesive layer 120 has more corresponding components. a window-shaped hole 123 of the substrate 110 to expose the component setting area 113; the adhesive layer 120 further has a plurality of second airbag holes 122, and the second airbag holes 122 are not arranged to overlap the component setting area 113. Around the window hole 123 (please refer to Figure 4). The adhesive layer 120 is further formed in the scribe lines 11 after the embossing patterning operation. Alternatively, in the structure of the second preferred embodiment, when the adhesive layer 120 covers the second recessed area 115, the first airbag holes 121 may be aligned on the convex areas 112.

Then, referring to FIGS. 3D and 3E, a second substrate 20 and a first substrate 10 are laminated, and the second substrate 20 includes a plurality of integrally connected laminated plates 130 having a flat surface. The adhesive layer 130 is adhered to the adhesive layer 120 on the component substrate 110, wherein the adhesive layer 120 is one of the non-flat surfaces 111. An adhesive area is greater than a second adhesive area of the adhesive layer 120 to the flat surface 131 (as shown in FIG. 3E). The size of the second substrate 20 may correspond to the size of the first substrate 10. In this embodiment, the second substrate 20 is a glass piece having a device wafer size. In the process of pressing the second substrate 20 and the first substrate 10, preferably, the adhesive layer 120 is vacuumed at the same time, so that the air pressure in the first airbag holes 121 is about 0.001 mBar. Not more than one atmosphere.

Then, referring to FIG. 3F, a bonding operation of the first substrate 10 and the second substrate 20 is performed, and the non-pressing surface 116 of the first substrate 10 is polished to reduce the component substrates 110. thickness.

Thereafter, referring to FIG. 3G, the first substrate 10 and the second substrate are The embossing body of 20 performs a drilling operation such that the component substrates 110 have through holes of a plurality of longitudinal conducting mechanisms 117 which are electrically connected to the protruding electrodes 119 by the non-pressing surfaces 116 of the component substrates 110.

Then, referring to FIG. 3H, a conductive layer deposition and plating operation is performed on the bonding body of the first substrate 10 and the second substrate 20, and a conductive metal layer 118 is formed on the non-pressing surface of the first substrate 10. 116, and may be formed in the through hole walls of the longitudinal conducting mechanisms 117 to form the longitudinal conducting mechanisms 117 electrically connecting the protruding electrodes 119.

Thereafter, referring to FIG. 3I, an insulating layer deposition operation is performed on the bonding body of the first substrate 10 and the second substrate 20, and an insulating back protective layer 143 is formed on the non-pressing surface 116 and covers the conductive layer. The lines of metal layer 118 do not cover the connection pads of the conductive metal layer 118. In addition, a conductive bonding layer 151 is formed on the connection pads of the conductive metal layer 118. As shown in FIG. 3J, a ball bonding operation is performed on the pressed body of the first substrate 10 and the second substrate 20 so that a plurality of solder ball external terminals 150 are bonded to the conductive bonding layer 151.

Finally, referring to FIGS. 3J and 3K, the manufacturing method further includes a singulation cutting step along which the first substrate 10, the second substrate 20 and the adhesive layer 120 are cut to form a single body. The bonded body of the element substrate 110 and the laminated plate 130 is separated to form a plurality of capped laminated semiconductor package structures 100 separated as shown in FIG.

The adhesive layer 120 is non-flat surface 111 of the first substrate 10 after the pressing step and the post-packaging process before the singulation cutting step. The adhesive interface and the adhesive interface of the flat surface 131 of the second substrate 20 do not generate irregular voids, thereby eliminating the possibility of formation of a large area of ineffective adhesive regions in the post-packaging process.

According to a second preferred embodiment of the present invention, another capping-fit semiconductor package structure 200 is illustrated in a cross-sectional view of FIG. 5 and a top view of the adhesive layer on the non-flat surface of FIG. 6, wherein The components of the same name and function are denoted by the component numbers of the first preferred embodiment, and the same detailed features are not described again. The capped press-fit semiconductor package structure 200 includes an element substrate 110, an adhesive layer 120, and a stack of press plates 130. The component substrate 110 can be selected from one of an image sensing wafer, an optoelectronic wafer, a microelectromechanical wafer, a wafer size package, a fan-out wafer level package, an integrated circuit substrate, and a circuit substrate. The 130 series may be selected from one of a glass sheet, a metal sheet, a wafer, and a pre-formed wafer body.

Referring to FIG. 5 , the element substrate 110 has a non-flat surface 111 formed with a plurality of convex regions 112 and at least one concave region 215 protruding from a protective layer. 142, the recessed area 215 is recessed in the protective layer 142. The different regions of the uneven surface 111 are composed of various patterns and elements disposed on the insulating layer 141 of one of the element substrates 110. In this embodiment, the convex regions 112 may be formed by the protruding electrodes 119, and the concave regions 215 may be formed on the periphery of the uneven surface 111. The component substrate 110 may be a fan-out wafer level package, and the component substrate 110 may include a sealant 260 covering a wafer side and at least a portion or a complete form of the sealant 260. A wiring layer, such as one of the conductive metal layers 118 on the non-compression surface 116, is disposed. The non-flat surface 111 of the element substrate 110 further includes a component setting region 113. The component setting area 113 can include a plurality of image sensing elements, and the laminated plate 130 can be a light transmissive sheet.

Referring to FIGS. 5 and 6, the adhesive layer 120 is formed on the non-flat surface 111. The adhesive layer 120 covers the concave portion 215. The adhesive layer 120 is patterned before pressing and has a plurality of first airbags. The holes 221, the first airbag holes 221 are aligned with the convex regions 112. The air pressure in the first airbag holes 221 may be no more than one atmosphere, and the adsorption effect of the adhesive layer 120 on the laminated plate 130 and the pore air on the outer peripheral adhesive faces of the convex regions 112 may be increased. In addition, the adhesive layer 120 may further have a window-shaped hole 123 to expose the component setting area 113. The adhesive layer 120 may further have a plurality of second airbag holes 122, and the second airbag holes 122 may not overlap. The element-shaped area 113 is arranged around the window-shaped hole 123, but does not communicate with the window-shaped hole 123. The second airbag holes 122 may be elliptical holes. The air pressure in the second airbag holes 122 may also be no more than one atmosphere.

Referring to FIG. 5 , the laminated plate 130 has a flat surface 131 , and the flat surface 131 is pressed against the non-flat surface 111 such that the laminated plate 130 is adhered to the adhesive layer 120 on the component substrate 110 . The first adhesive area of the adhesive layer 120 to the non-flat surface 111 is greater than the second adhesive area of the adhesive layer 120 to the flat surface 131. Due to the formation positions of the first airbag holes 221, the convex regions 112 of the component substrate 110 preferably do not contact the laminated plate 130, and are not longitudinally bonded by the colloid of the adhesive layer 120.

Referring to FIG. 5 , the component substrate 110 can further have a plurality of longitudinal conduction mechanisms 117 , which can be electrically connected to the protruding electrodes 119 by one of the non-compression surfaces 116 of the component substrate 110 , and the conductive metal Layer 118 is electrically connected. In this embodiment, the longitudinal conduction mechanisms 117 can be through-type molded vias (TMV), molded metal posts, molded solder balls, or side stereoscopic lines. A back protective layer 143 is formed on the non-compression surface 116 and covers the conductive metal layer 118. A plurality of external terminals 150 are electrically connected to the conductive metal layer 118 via a conductive bonding layer 151 at the bottom thereof.

The method of fabricating the capped-type semiconductor package structure 200 can follow the main process steps as shown in Figures 3A through 3K in the fabrication method of the capped-press-type semiconductor package structure 100 of the first preferred embodiment.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

100‧‧‧Capped press-fit semiconductor package construction

110‧‧‧ element substrate

111‧‧‧ non-flat surface

112‧‧‧ convex area

113‧‧‧Component setting area

114‧‧‧First pit

115‧‧‧second recess

116‧‧‧Non-pressed surface

117‧‧‧Longitudinal conduction mechanism

118‧‧‧ Conductive metal layer

119‧‧‧ protruding electrode

120‧‧‧Adhesive layer

121‧‧‧First airbag hole

122‧‧‧Second airbag hole

123‧‧‧Window hole

130‧‧‧Laminated plate

131‧‧‧flat surface

141‧‧‧Insulation

142‧‧‧ facing the protective layer

143‧‧‧Back protective layer

150‧‧‧External terminals

151‧‧‧Electrical bonding layer

Claims (18)

A capping-type semiconductor package structure comprising: an element substrate having a non-flat surface on which a plurality of convex regions are formed; an adhesive layer formed on the non-flat surface, the adhesive layer Covering the convex regions, the adhesive layer is patterned before pressing and has a plurality of first airbag holes, and the first airbag holes are arranged not around the convex regions and are arranged around the convex regions; a stack of press plates having a flat surface, the flat surface facing the non-flat surface being pressed such that the laminated plate is adhered to the adhesive layer on the element substrate, wherein the adhesive layer is first to the non-flat surface The adhesive area is greater than the second adhesive area of the adhesive layer to the flat surface. The capping-type semiconductor package structure of claim 1, wherein the non-flat surface comprises a component placement region, the adhesive layer further having a window-shaped aperture to expose the component placement region, the adhesive layer The system further has a plurality of second airbag holes, and the second airbag holes are arranged around the window-shaped hole without overlapping the component setting area. The capping-type semiconductor package structure of claim 2, wherein the component mounting region comprises a plurality of image sensing elements, and the laminated plate is a light transmissive sheet. The capping-type semiconductor package structure of claim 3, wherein the component mounting region is formed on one of the first recessed regions of the component substrate, and the periphery of the non-flat surface is formed as a second recessed region. The second recess is further recessed in the first recess. The capping-type semiconductor package structure of claim 3, wherein the lands are formed by a plurality of protruding electrodes, and the component substrate further comprises a plurality of longitudinal conducting mechanisms, wherein the component substrate is One of the non-compressed surfaces is electrically connected to the protruding electrodes. The capping-type semiconductor package structure of claim 1, wherein the component substrate is selected from the group consisting of an image sensing wafer, an optoelectronic wafer, a microelectromechanical wafer, a wafer size package, and a fan-out wafer level package. One of a body, an integrated circuit substrate and a circuit substrate, the laminated plate being selected from one of a glass sheet, a metal sheet, a wafer and a pre-formed wafer body. The capped-fit semiconductor package structure of any one of claims 1 to 6, wherein the first balloon holes are elliptical holes. The capped press-fit semiconductor package structure according to any one of claims 1 to 6, wherein the air pressure in the first air bag holes is not more than one atmosphere. A capping-type semiconductor package structure comprising: an element substrate having a non-flat surface, wherein the non-flat surface is formed with a plurality of convex regions and at least one concave region, the convex regions protruding from a protective layer The recessed area is recessed in the protective layer; an adhesive layer is formed on the non-flat surface, the adhesive layer covers the concave area, and the adhesive layer is patterned before pressing and has a plurality of first airbags a hole, the first airbag holes are aligned with the convex regions; and a stack of pressing plates having a flat surface, and the flat surface faces the non-flat surface by a pressing manner such that the laminated plate is adhered to the element substrate The adhesive layer, wherein the first adhesive area of the adhesive layer to the non-flat surface is greater than the second adhesive area of the adhesive layer to the flat surface. The capping-type semiconductor package structure of claim 9, wherein the non-flat surface comprises a component placement region, the adhesive layer further having a window-shaped aperture to expose the component placement region, the adhesive layer The system further has a plurality of second airbag holes, and the second airbag holes are arranged around the window-shaped hole without overlapping the component setting area. The capping-type semiconductor package structure of claim 10, wherein the component mounting region comprises a plurality of image sensing elements, and the laminated plate is a light transmissive sheet. The capping-type semiconductor package structure of claim 9, wherein the recess is formed on a periphery of the non-flat surface, and the bumps are formed by a plurality of protruding electrodes. The capped-type semiconductor package structure of claim 12, wherein the component substrate further comprises a plurality of longitudinal conduction mechanisms electrically connected to the protrusions by a non-compression surface of the component substrate electrode. The capping-type semiconductor package structure of claim 9, wherein the component substrate is selected from the group consisting of an image sensing wafer, an optoelectronic wafer, a microelectromechanical wafer, a wafer size package, and a fan-out wafer level package. One of a body, an integrated circuit substrate and a circuit substrate, the laminated plate being selected from one of a glass sheet, a metal sheet, a wafer and a pre-formed wafer body. The capped-type semiconductor package structure of any one of claims 9 to 14, wherein the first air bag holes have a gas pressure of not more than one atmosphere. A method for manufacturing a capping-type semiconductor package structure includes: providing a first substrate, comprising a plurality of integrally connected component substrates, wherein the component substrates have a non-flat surface, and the non-flat surface is formed with a plurality of a convex region and at least one concave region; forming an adhesive layer on the non-flat surface; performing a pre-pressing patterning operation on a pair of the adhesive layer, the adhesive layer having a plurality of first airbag holes, when the adhesive layer Covering the convex regions, the first airbag holes are arranged not around the convex regions and are arranged around the convex regions, or when the adhesive layer covers the concave regions, the first airbag holes are paired And a second substrate and a first substrate, the second substrate comprises a plurality of integrally connected laminated plates, wherein the laminated plates have a flat surface with the flat surface facing The non-flat surface is pressed in such a manner that the laminated plates are adhered to the adhesive layer on the component substrates, wherein the first adhesive area of the adhesive layer to the non-flat surface is greater than the adhesive layer is one of the flat surfaces Second adhesion area. The method of fabricating a captive-type semiconductor package structure according to claim 16, wherein the recess extends further to a plurality of scribe lines between the element substrates. The method of manufacturing a capped-type semiconductor package structure according to claim 16 or 17, wherein the first substrate is formed as a plurality of dicing streets between the component substrates, and the adhesive layer is formed on the dicing layer. In the dicing streets, the manufacturing method further comprises the steps of: cutting the first substrate, the second substrate and the adhesive layer along the scribe lines to singly separate the bonding between the element substrate and the laminated plate In order to produce a plurality of separate capping press-fit semiconductor package structures.