TWI743120B - Chip packaging structure with lead tabs on top and manufacturing method thereof - Google Patents

Abstract

A chip package structure with a guide tab on the top and a manufacturing method thereof. The chip package structure includes: a substrate; a plurality of bonding pads on the substrate; at least one chip whose lower surface is placed on the substrate; There are multiple soldering pads, which can be connected to multiple soldering pads on the substrate via wires; at least one conductive tab, the conductive tab is a thin plate-like material; each of the conductive tabs is pasted on the corresponding chip The upper surface; where the material of the guide tab is different from the material of the structure to be packaged later.

Description

Chip packaging structure with lead tabs on top and manufacturing method thereof

The present invention relates to a chip package structure, in particular to a chip package structure with a conductive sheet on the upper side and a manufacturing method thereof.

In the semiconductor manufacturing process, certain types of wafers must be light-sensitive or electromagnetically induced. Therefore, the package structure above the chip must be made relatively thin, so that the lower wafer can be light-sensitive or electromagnetically induced. Such as fingerprint recognition chip or image chip formed by CMOS. The fingerprint recognition chip presses the fingerprint on the top of the chip, and the chip can sense the fingerprint on the top through photosensitive or electromagnetic induction. The image chip formed by CMOS can be used for fingerprint recognition and image capture. In order to produce a good image effect, the upper package structure must be thin. For example, the thickness required to be packaged above the wafer is only 150 to 200 μm. It is quite difficult to manufacture such a thin package structure with the current semiconductor manufacturing process, and the cost is also high.

Therefore, this case hopes to propose a new chip package structure with conductive tabs on the top and a manufacturing method thereof to solve the above-mentioned defects in the prior art.

Therefore, the purpose of the present invention is to solve the above-mentioned problems in the prior art. In the present invention, a chip package structure with conductive tabs on the upper side and a manufacturing method thereof are proposed. The splice is very thin, with the current technology, it can be between 60μm and 100μm, which is thinner than the traditional packaging technology, and the manufacturing technology is quite simple. On the other hand, you can choose the required guide tabs to meet the needs of the used chip, and produce better results. In particular, fingerprint recognition and imaging chips are required in this regard. If the traditional packaging method is used, the packaging layer in the sensing area above the chip must be made quite thin, but it is quite difficult in manufacturing technology, and its sensing ability is worse than directly selecting appropriate sensing materials.

In order to achieve the above objective, the present invention proposes a chip package structure with conductive tabs on the top, including: a substrate; a plurality of bonding pads on the substrate; at least one chip whose lower surface is placed on the substrate; There are multiple soldering pads, which can be connected to multiple soldering pads on the substrate via wires; at least one conductive tab, the conductive tab is a thin plate-like material; each of the conductive tabs is pasted on the corresponding chip The upper surface; where the material of the guide tab is different from the material of the structure to be packaged later.

In this case, a method for manufacturing a chip package structure with lead pads on the top is also proposed, in which a large number of lead pads are attached to the wafer at the same time before the chip is separated from the entire wafer to form separate chips. Above, its position corresponds to the top of each chip after dicing; subsequent semiconductor manufacturing processes such as dicing, separation, packaging, etc. are carried out; wherein the conductive sheet is a thin plate-shaped material; each conductive sheet is pasted on Corresponding to the upper surface of the chip; wherein the material of the conductive tab is different from the material of the structure to be packaged later; and when the package is packaged, the conductive tab can be exposed to the outside.

The features and advantages of the present invention can be further understood from the following description, and please refer to the accompanying drawings when reading.

10‧‧‧Substrate

20‧‧‧Chip

30‧‧‧Guide piece

40‧‧‧Packaging structure

50‧‧‧wafer

70‧‧‧Adhesive bottom plate

80‧‧‧Wire

100‧‧‧Solder pad

200‧‧‧Solder pad

Figure 1 shows a schematic diagram of the component assembly in this case.

Fig. 2 shows a schematic cross-sectional view of Fig. 1.

Fig. 3 shows another illustrative example of the component assembly diagram of this case.

Fig. 4 shows a schematic cross-sectional view of Fig. 3.

Figure 5 shows a schematic diagram of the wafer placed on the adhesive substrate in the process of this case.

FIG. 6 shows a schematic diagram of the wafer dicing into multiple wafers in the process of this case.

Fig. 7 shows a schematic diagram of the lead pad and the chip in the manufacturing process of this case.

FIG. 8 shows a schematic diagram of the bonding of the lead pad and the chip in the manufacturing process of this case.

Figure 9 shows a flow chart of the manufacturing process in this case.

With regard to the structural composition of this case, and the effects and advantages that can be produced, in conjunction with the drawings, a preferred embodiment of this case is described in detail as follows.

Please refer to FIG. 1 to FIG. 4, which show the chip package structure with the conductive tabs on the top of the present invention, which includes the following components: A substrate 10. There are a plurality of bonding pads 100 on the substrate.

At least one chip 20 has a lower surface placed on the substrate 10. Each chip 20 has a plurality of bonding pads 200, and the plurality of bonding pads 100 on the substrate 10 can be connected via wires 80.

At least one guiding piece 30 is a sheet-like plate material. Each of the guide tabs 30 is adhered to the upper surface of the corresponding chip 20.

A packaging structure 40 is used for packaging the at least one chip 20 and the substrate 10 so that the at least one conductive sheet 30 can be exposed to the outside.

The material of the conductive tab 30 is different from the material of the packaging structure.

In an embodiment of the present case, the material of the conductive sheet 30 is an electromagnetically permeable material, such as plastic material (PI, PET) or glass. The chip 20 is a fingerprint recognition chip. Therefore, when a finger is placed above the guide piece 30, the fingerprint of the finger can reflect the electromagnetic wave emitted by the chip 20, so that the chip 20 receives the fingerprint signal for related applications, such as fingerprint storage or recognition.

In another embodiment of the present case, the material of the conductive sheet 30 is a light-transmissive material. The chip 20, such as a CMOS chip, can be used for image sensing, such as photography or fingerprint recognition. For example, for fingerprint recognition, when the finger is placed above the guide piece 30, the fingerprint can reflect the light waves of the chip, so that the chip 20 can receive the fingerprint signal for related applications, such as fingerprint storage or recognition.

When the CMOS chip is used in photography, it must be able to effectively receive external light waves. In this case, a transparent material guide sheet 30 can be used so that the external light can almost completely penetrate the guide sheet 30 to obtain good effect.

1 and 2 show that the substrate 10 has only a single chip 20 on the structure. However, this case can also be used in the case of multiple wafers 20. As shown in FIGS. 3 and 4, the structure of the substrate 10 with multiple wafers 20 is shown. However, the connection positions and connection methods of the soldering pads and wires shown in the drawings are not used to limit the structure of this case, and other connection positions and connection methods are within the scope of this case.

A major advantage in the process in this case is that it is possible to apply a unified process method to directly place a large number of guide tabs 30 directly on each wafer when the wafer 20 has not been separated from the wafer into individual independent wafers. Corresponding to the upper side of the chip 20, the package structure is then fabricated, so the manufacturing process is quite convenient.

In the chip manufacturing process, a wafer must be combined with a substrate, and then diced to form a large number of chips, and then these chips are packaged separately. In this case, when each chip is not separated from the wafer to form an independent chip, a large number of conductive tabs 30 can be attached to the wafer at one time in the manufacturing process, thereby saving the overall manufacturing process.

An example is given as follows. FIGS. 5 to 8 show an embodiment of the manufacturing process in this case. In this embodiment, the same components as the previous embodiment are denoted by the same symbols, and their functions are the same, so they will not be described in detail. As shown in FIG. 9, the present embodiment includes the following steps: placing a wafer 50 on an adhesive substrate 70 (commonly known as blue tape) (step 100), as shown in FIG. 5.

The wafer 50 is diced into a plurality of wafers 20, but the wafers 20 are still adhered to the adhesive base plate 70, and the integrity of the appearance of the wafer 50 is substantially maintained (step 110), as shown in FIG. 6.

The plurality of guide tabs 30 are placed on the plurality of wafers 20, and the aligned relationship is maintained substantially. Each of the guide tabs 30 is pasted onto the corresponding chip 20 (step 120), as shown in FIGS. 7 and 8.

The adhesive bottom plate 70 is torn off, and then the multiple chips 20 are placed on the substrate to enter the separation, soldering, wire connection and packaging procedures (step 130). This is a generally known packaging procedure and will not be explained in this case.

The advantage of the packaging method in this case is that, because the lead tab is attached to the top of the chip, the lead tab can be made very thin. With the current technology, it can be between 60μm and 100μm, which is thinner than the traditional packaging technology. , And the production technology is quite simple. On the other hand, you can choose the required guide tabs to meet the needs of the used chip, and produce better results. In particular, fingerprint recognition and imaging chips are required in this regard. If the traditional packaging method is used, the packaging layer in the sensing area above the chip must be made quite thin, but it is quite difficult in manufacturing technology, and its sensing ability is worse than directly selecting appropriate sensing materials.

In summary, the humanized and considerate design of this case is quite in line with actual needs. Compared with the conventional technology, the specific improvement of the existing defects is obviously a breakthrough advantage, and it does have an increase in efficacy, and it is not easy to achieve. This case has not been disclosed or disclosed in domestic and foreign documents and markets, and it has complied with the provisions of the Patent Law.

The above detailed description is a specific description of a possible embodiment of the present invention, but this embodiment is not intended to limit the scope of the patent of the present invention. Any equivalent implementation or modification that does not deviate from the technical spirit of the present invention shall be included in In the scope of the patent in this case.

10‧‧‧Substrate

20‧‧‧Chip

30‧‧‧Guide piece

40‧‧‧Packaging structure

80‧‧‧Wire

100‧‧‧Solder pad

200‧‧‧Solder pad

Claims (11)

A method for manufacturing a chip package structure with lead pads on the top, where a large number of lead pads are attached to the top of the wafer at the same time before the chip is separated from the entire wafer to form separate chips. Corresponding to the top of each chip after dicing; and then perform subsequent dicing, separation, packaging and other semiconductor manufacturing processes; wherein the conductive tab is a thin plate-shaped material; each conductive tab is pasted on the corresponding chip The upper surface; wherein the material of the guide tab is different from the material of the structure to be packaged later; and the guide tab can be exposed to the outside during packaging. According to the method described in item 1 of the scope of patent application, the material of the conductive sheet is electromagnetically permeable material. The method described in item 1 of the scope of patent application, wherein the chip is a fingerprint recognition chip. According to the method described in item 1 of the scope of patent application, the material of the guide sheet is a light-transmissive material. The method described in item 1 of the scope of patent application, wherein the chip is a CMOS chip for image sensing or fingerprint recognition. A chip package structure with conductive tabs on the top manufactured by the method in the scope of patent application 1 to 5, including: A substrate; the substrate has a plurality of bonding pads; at least one chip, the lower surface of which is placed on the substrate; each chip has a plurality of bonding pads, which can be connected to the plurality of bonding pads on the substrate via wires; at least one The guiding piece is a sheet-like plate material; each of the guiding pieces is pasted on the upper surface of the corresponding chip; wherein the material of the guiding piece is different from the material of the structure to be packaged later. For example, the chip packaging structure with conductive tabs on the upper part of the patent application scope includes: a package structure for packaging the at least one chip and the substrate, so that the at least one conductive tab can be exposed to the outside. As described in item 6 of the scope of the patent application, the chip package structure with a conductive sheet on the upper side, wherein the material of the conductive sheet is an electromagnetic permeable material. As described in item 6 of the scope of patent application, the chip package structure with the lead tab on the top, wherein the chip is a fingerprint identification chip. As described in item 6 of the scope of the patent application, the chip package structure with the conductive tabs above, wherein the material of the conductive tabs is a light-permeable material. As described in item 6 of the scope of the patent application, the chip package structure with conductive tabs above, wherein the chip is a CMOS chip, used for image sensing or fingerprint identification.

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