五、新型說明： 【新型所屬之技術領域】 本創作係有關於一種雙埠靜態隨機存取記憶體（static Random Access Memory ’簡稱sram)，尤指一種可降低漏電流（leakage current)且麟決f知具單__位元叙料SRAM寫人邏輯丨困難 之雙埠靜態隨機存取記憶體。 【先前技術】 δ己憶體在電腦：L業中扮演著無可或缺的角色^通常，記憶體可 依照其戒否在電源關閉後仍能保存資料，而區分為非揮發性 (non-volatile)記憶體及揮發性（v〇latile)記憶體，非揮發性記憶 體所儲存之倾並不會因電源關或中_消失，而儲存在揮發性 記憶體之資料則會隨著電源關閉或中斷而被消除。常見的揮發性記 憶體有動態隨機存取記憶體（DRAM)及靜態隨機存取記憶體 (SRAM)兩種。動態隨機存取記憶體（DRAM)具有面積小及價 格，等優點’但操作時必須不時地更新（refresh)以防止資料因漏 電流而遺失，而導致存在有高速化_及絲功較等缺失。相反 地’靜態隨機存取記憶體（SRAM)的操作職·易且毋須更新 操作，因此具有高速化及消耗功率低等優點。 目則以行動電話為代表之行動電子設備所採用之半導體記惊裝 置’係以SRAM為主流β此乃由於SRAM待機電流小，適於連續 通話時間、連續待機時間盡可能延長之手機。 習知之靜態隨機存取記憶體（SRAM)如第la圖所示，其主要 包括一記憶體陣列（memoly a卿），該記憶體陣列係由複數個記 憶體區塊（memoty block ’ MB】、MB2等）所組成，每—記憶體區 Μ4〇δ〇99 塊更由複數列記憶體晶胞（a plurality of rows of memory cells )與複 數行記憶體晶胞（a plurality of columns of memory cells)所組成， 每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶 胞；複數條字元線（word line，WI4、WL2等），每一字元線對應 至複數列記憶體晶胞中之一列；以及複數位元線對（bitlinepairs， BL!、ΒΙΒ^.ΒΙ^、BLBm等），每一位元線對係對應至複數行記憶 體晶胞中之一行，且每一位元線對係由一位元線（BLi.-.BLm)及 一互補位元線（BLBi...BLBm)所組成。 第lb圖所示即是6T靜態隨機存取記憶體（SRAM)晶胞之電 路示意圖，其中’ PMOS電晶體(P1)和(P2)稱為負載電晶體（i〇ad transistor) ’ NMOS電晶體(Ml)和(M2)稱為驅動電晶體（driving transistor)，NMOS電晶體(M3)和(M4)稱為存取電晶體（access transistor) ’ WL為字元線（word line) ’而BL及BLB分別為位元 線（bit line )及互補位元線（compiementary仙iine )，由於該sraM 晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅動能 力比（即單元比率（cell ratio))通常設定在2.2至3.5之間，而導 致存在有高集積化困難及價格高等缺失。 第lb圖所示6T靜態隨機存取記憶體晶胞於寫入操作時之 HSPICE %態分析模擬結果’如第2圖所示，其係以level 49模型且 使用TSMC 0.18微米CM0S製程參數加以模擬。 用來減少6T靜態隨機存取記憶體（SRAM)晶胞之電晶體數之 =種方式係揭露於第3圖中。第3 _示-種僅具單n線之5T 靜態隨機存取記憶體晶胞之電路示意圖，與第i圖之叮靜態隨機 子取。己It體sb胞相比’此種5T靜態隨機存取記憶體晶胞比6τ靜離 隨機存取記憶體«少— «Μ及少—條元線，_ 5τ贿 隨機存取記鐘騎在不變更pMGS電雜ρι和ρ2以及觸s 4 M408099 電晶體Μ卜M2和M3的通道寬長比的情況下存在寫入邏輯1相當 困難之問題。茲考慮記憶晶胞左側節點Α原本儲存邏輯〇的情況， 由於節點A之電荷僅單獨自寫入用位元線（wbL)傳送，因此很難 將節點A中先前寫入的邏輯〇蓋寫成邏輯j。第3圖所示5T靜態 隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結 果’如第4圖所示，其係以level 49模型且使用TSMc 〇 18微米 CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之 5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 迄今，有許多具單一位元線之5T靜態隨機存取記憶體晶胞之 技術被提出，例如非專利文獻1( I. Carlson et al.，，，A high density，low leakage, 5T SRAM for embedded caches,Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp.215-218,2004.)之5T SRAM由於係藉由重新設計晶胞中之二驅 動電晶體、二負載電晶體以及一存取電晶體之通道寬長比以解決寫 入邏輯1困難之問題’而造成破壞原有晶胞中之驅動電晶體與負載 電晶體之對稱性關係並從而易受製程變異的影響；非專利文獻2( M Wieckowski et al. ,,5 A novel five-transistor ( 5T ) SRAM cell for high performance cache,” IEEE Conference on SOC, pp. 1001-1002,2005.) 之5T SRAM由於係將一長通道長度之存取電晶體設置於晶胞中之 二負載電晶體之間以解決寫入邏輯1困難之問題，而造成降低存取 速度之缺失；專利文獻3 (98年6月1日第TWM358390號）所提 出之「寫入操作時降低電源電壓之單埠SRAM」雖可有效解決寫入 邏輯1困難之問題’惟寫入操作時’由於缺乏有效的放電路徑，而 造成於高記憶容量及/或高速操作時存在低寫入速度之缺失。 接下來討論靜態隨機存取記憶體(SRAM)之單槔及雙槔架構，第 lb圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存 5 取記憶體(SRAM)晶胞之—例，其係使用兩條位元線bl及blb做 讀寫的動作’也就是讀與寫均是經由同樣的—對位元線來達成，是 以在同-時_只能進行讀或寫_作，因此，#欲設計具有同時 讀寫能力之雙埠靜騎機存取記憶料，便f要多加人兩顆存取電 晶體以及另-對位元線（請參考第5圖所示電路，其中ML及 WBLB為寫人祕元線、咖及咖B為讀_位元線、瓢為 寫入用字7L線、RWL為讀取財元線），這使得記憶晶麟面積大 大地增加’如果我們能夠簡化記憶晶胞的架構，使得一條位元線負 責讀取的動作’而另-條位元線負責寫人的動作，則在設計雙埠靜 態隨機存取記碰時’記憶晶胞便不需要多加人兩顆電晶體及另一 對位7G線’這樣記憶晶胞的面積便會減小許多。傳統的雙璋靜態隨 機存取記賴晶胞之所以不採料種方法，是因為如祕述之無法 達成寫入邏輯1的問題。 有鑑於此，本創作之主要目的係提出一種具共享控制電路之單 埠靜態隨機存取記憶體，其能藉由控制電路以有效避免習知具單一 位70線之雙轉祕赫取記紐g胞存在冑人祕丨相當困難之 問題。 、 本創作作之次要目的係提出一種具共享控制電路之單埠靜態隨機 存取記憶體，其能藉由控制電路财效降低賴模式之漏電流。 【新型内容】 本創作提出一種具共享控制電路之單埠靜態隨機存取記憶體， 其主要包括一記憶體陣列以及複數個控制電路（2)，該記憶體陣 列係由複數個記憶體區塊所組成，每一記憶體區塊設置一個控制電 路，且每一記憶體區塊更包括複數個記憶體晶胞（1)，每一記憶 體晶胞（1)則由一 NMOS存取電晶體（M3)、二NMOS驅動電 晶體（Ml和M2)、二PMOS負載電晶體（pi和P2)及一第一和 第二讀取用電晶體（M4和M5)所組成。每一控制單元係連接至對 應記憶體區塊中之每一記憶晶胞的二NMOS驅動電晶體的源極 端，以便因應不同操作模式而控制該等源極端之源極電壓，於寫入 模式時，將選定晶胞中較接近寫入用位元線（WBL)之驅動電晶體 (Ml )的源極设疋成較接地電壓為高之一預定電壓且將選定晶胞中 另一驅動電晶體（M2)的源極電壓設定成接地電壓，以便防止寫入 邏輯1困難之問題，於待機模式時’將所有記憶體晶射之驅動電 晶體的源極f壓設定成健地電壓為高之該預定電壓，以便降低漏 電流；而讀取模式時則將所有記憶體晶胞巾之驅動電晶體的源極電 壓設定成接地電壓，以便維持讀取穩定度。綜上所述，本創作所提 出之具共享㈣電路之科靜紐機存取記，隨，雜可有效避免 1知具單-位元線之單蟑SRAM所存在寫人邏輯丨相當困難之問 通，並且也能兼具待機模式時降低漏電流之功效。 實施方式】 根據上述之主要目的，本齡提丨—種具共享控制電路之單淳 靜態隨機存取記憶體，其主要包括—記，該記憶體陣列係 由複數個記紐區麟組成，每—記紐區塊更包括有複數個記憶 體晶胞（1);以及複數健制電路⑴，每一記憶體區塊設置一 個控制電路（2)。在此值得注意的是，該記憶艇塊可簡單至僅 為一列記憶體晶胞或一行記憶體晶胞》 為了便於說明起見，第6圖所示之具共享控制電路之單埠靜態 隨機存取記憶體僅以一個記憶體晶胞（1)、一條寫入用字元線 (WWL)、一條位元線（WBL)、一條讀取用字元線（RWL)、一條 讀取用位元線（RBL)以及一控制電路（2)做為實施例來說明。該 記憶體晶胞（1 )係包括一第一反相器（由第一 pM〇s電晶體P1與 第一 NMOS電晶體Ml所組成）、一第二反相器（由第二pM〇s電 晶體P2與第二NMOS電晶體M2所組成）、一第三NMOS電晶體 (M3)、一第一讀取用電晶體（M4)以及一第二讀取用電晶體 (M5) ’其中，該第一反相器和該第二反相器係呈交互耦合連接， 亦即該第一反相器之輸出（即節點A)係連接該第二反相器之輸入， 而該第二反相器之輸出（即節點B)則連接該第一反相器之輸入， 並且該第一反相器之輸出（節點A)係用於儲存SRAM晶胞之資料， 而該第二反相器之輸出（節點B )則用於儲存SRAM晶胞之反相資 料，該第三NMOS電晶體（M3) ’係連接在該儲存節點（a)與 寫入用位元線（WBL)之間’且閘極連接至寫入用字元線（wwL)， 以作為記憶體晶胞之存取電晶體使用，而該第二讀取用電晶體(M5) 之源極、閘極與汲極係分別連接至接地電壓、該第二反相器之輸出 (節點B)與該第一讀取用電晶體（M4)之源極，該第一讀取用電 晶體（M4)之源極、閘極與>及極係分別連接至該第二讀取用電晶體 (M5)之及極、該讀取用字元線（RWL)與該讀取用位元線（RgL)。 請再參考第6圖，該控制電路（2)係由一第四nmos電晶體 (M21)、一第五NMOS電晶體（M22)、一第六nm〇S電晶體 (M23)、一第七NMOS電晶體（M24)、一第ANM〇s電晶體 (M25 )、一第九NMOS電晶體（M26 )、一第十NMOS電晶體 (M27)以及一第十一 NMOS電晶體（M28)所組成，該第四nmos M408099 電晶體（M21)之源極係連接至接地電壓，而閘極與汲極係連接在 一起，並連接至一第一低電壓節點（VL1);該第五_〇8電晶體 (M22)之源極、閘極與沒極係分別連接至接地電壓、一反相待機 模式控制信號（¾)與一第二低電壓節點（VL2)，而該第六NM〇s 電晶體（M23)源極、閘極與汲極係分別連接至該第二低電壓節點 (VL2)、一待機模式控制信號與該第一低電壓節點（vli); 該第七NMOS電晶體（M24)之源極連接至接地電壓，汲極連接至 該第一低電壓節點（VL1)，而閘極則連接至一第ANM〇s電晶體 • (M25)之汲極、一第九NM〇S電晶體（M26)之汲極與一第十 NMOS電晶體（M27)之源極；該第八nm〇S電晶體（M25)之源 極、閘極與汲極係分別連接至接地電壓、一寫入用字元線（WWL) 與該第七NMOS電晶體(M24 )之閘極;該第九nm〇s電晶體(M26 ) 之源極、閘極與汲極係分別連接至接地電壓、該待機模式控制信號 (S)與該第七NMOS電晶體（M24)之閘極；該第十nm〇s電晶 體（M27)之源極、閘極與沒極係分別連接至該第七nmos電晶體 (M24)之閘極、一反相用字元線^ψψι )與一第_一 nm〇S電 鲁晶體（M28)之源極；該第十一 nmos電晶體（M28)之源極、閘 極與沒極則分別連接至該第十NMOS電晶體（M27)之汲極、該反 相待機模式控制信號（互）與一電源供應電壓（Vdd)。在此值得注 意的是，該反相待機模式控制信號（互）係由該待機模式控制信號 (s)經一反相器而獲得，而一反相寫入用字元線^ WWL)亦係由 該寫入用字元線（WWL)經一反相器而獲得。 該控制電路（2)係設計成可因應不同操作模式而控制該第一低電 壓節點（VL1)與該第二低電壓節點（VL2)之電壓位準，於寫入 模式時’將該第一低電壓節點（VU)設定成較接地電壓為高之一 9 M408099 預定電壓且將該第二低電壓節點（VL2)設定成接地電壓，以便防 止寫入邏輯1 _之問題；於待機模式時，將該第—低電壓節點 (VU)與該第二低電壓_ (VL2)設域較接地電縣高之該 預疋電壓，以便降低漏電流；而於讀取模式時則將該第一低電壓節 點（VL1)與該第二低電壓節點（VL2)設定成接地電壓，以便維 持續取穩定度。其詳細工作電壓位準如表1所示，其中節點C之電 壓即為該第七NMOS電晶體(M24 )之閘極電壓，Max Vtm27 ) • 表示V™27與V™28中之較大者，該Vtm27與乂顶28分別表示該第十 NMOS電曰曰曰體（M27)及該第十一 nm〇S電晶體（M28)之臨界電 壓（threshold voltage )，而V·丨則表示該第四麵〇§電晶體（M2 i ) 之臨界電壓，在此值得注意的是，於寫入丨時該第一低電壓節點 (VL1)之電壓為Vtmu，而寫入〇時該第一低電壓節點（yj^)之 電壓為0V。 WE S 節點c VL1 VL2 模式 0 0 VDD-Max(VTM28，VTM27) 0 0 其他 0 V〇d 0 ^TM21 VjM2I 待機 Vdd 0 0 VTM21 或 〇 0 寫入 表1 各種工作模式下之電壓位準 兹依具共享控制電路之單埠靜態隨機存取記憶體之工作模式說 明第6圖之本創作較佳實施例的工作原理如下： (I )寫入模式（writemode) 此時該寫入用字元線（WWL)為邏輯高位準，該待機模式控制 10 M408099 信號（s)為邏輯低位準，而該反相待機模式控制信號（g)為邏 輯高位準，該邏輯高位準之該反相待機模式控制信號（玄）可使得 該控制電路（2)申之該第五NMOS電晶體（M22)導通（on)， 而該邏輯低位準之該待機模式控制信號（S)使得該第六_〇3電 晶體（M23)截止（OFF)，於是可將該第二低電壓節點（VL2) 之電壓拉低至接地電壓，而該第一低電壓節點（VL1)之電壓位準 於寫入操作前則等於該第四NMOS電晶體（M21)之臨界電壓之位 準，俾藉此以有效防止寫入邏輯1困難之問題。 • 接下來依具共享控制電路之單埠靜態隨機存取記憶體晶胞之4 種寫入狀態來說明第6圖之本創作較佳實施例如何完成寫入動作。 (一） 節點A原本儲存邏輯〇，而現在欲寫入邏輯〇 : 在寫入動作發生前（該寫入用字元線WWL為接地電壓），該 第一 NMOS電晶體（Ml)為導通（ON) »因為該第一 nmos電 晶體（Ml)為（ON)，所以當寫入動作開始時，該寫入用字元線 (WWL)由Low (接地電壓）轉High (電源供應電壓Vdd)。當 該寫入用字元線（WWL)的電壓大於該第三nm〇s電晶體（M3) % (即存取電晶體）的臨界電壓時，該第三NMOS電晶體（M3)由 截止（OFF)轉變為導通（0N)，此時因為寫入用位元線（WBL) 是接地電壓，所以會將該節點A放電，而完成邏輯〇的寫入動作， 直到寫入週期結束。 (二） 節點A原本儲存邏輯〇，而現在欲寫入邏輯1 : 在寫入動作發生前（該寫入用字元線WWL為接地電壓），該 第一 NMOS電晶體（Μι)為導通（ON)。因為該第一 電 晶體（Ml)為（ON)，所以當寫入動作開始時，該寫入用字元線 (WWL)由Low (接地電壓）轉High (該電源供應電壓Vdd)， 該節點A的電壓會跟隨該寫入用字元線（wwl)的電壓而上升。 11 當該寫入用字元線（職L)的電壓大於該第SNMOS電晶體 (M3)的臨界電虔時，該第三麵⑽電晶體（M3)由截止（〇ff) 轉變為導通（ON) ’此時因為該寫入用位元線（該 電源供應電壓VDD)，並且因為該第一丽〇5電晶體㈤）仍為 ON且該節點B仍處於電壓位準為接近於該電源供應電壓（Vdd) 之電壓位準的初始狀態，所以該第一 PM〇s電晶體ρι仍為截止 (OFF) ’而該節點a則會朝一分壓電壓位準快速充電，該分壓電 壓位準等於（rm1+Rm2i) / (RM3 + rm1 + rm21)乘以該電源供應電 壓（Vdd)，其中該RM3表示該第三nmos電晶體（M3)之導通等 效電阻，該RM1表示該第一 NMOS電晶體（M1)之導通等效電阻， 而該Rm:m表示該第四NMOS電晶體（M21)之導通等效電阻，此 時因為第三NMOS電晶體（M3 )仍工作於飽和區（saturation regi()n ) 且該第一NMOS電晶體（Ml)仍工作於線性區（trioderegion)， 雖然該第三NMOS電晶體（M3)之導通等效電阻（rM3)會遠大於 該第一 NMOS電晶體（Ml)之導通等效電阻（rm1)，但由於該第 四NMOS電晶體（M21)係呈二極體連接，因此可於該第一低電壓 節點（VL1)處提供一等於該第四nmos電晶體（]V[21)之閘源極 電壓VGS之電壓位準，結果節點a所呈現的該分壓電壓位準，其電 壓值會比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點a之 電壓位準還要高許多。該還要高許多之分壓電壓位準足以使該第二 NMOS電晶體（M2)導通，於是使得節點B放電至一較低電堡位 準’該節點B之較低電壓位準會使得該第一 NMOS電晶體（M1) 之導通等效電阻（RM1)呈現較高的電阻值，該第一 NMOS電晶體 (Ml)之該較高的電阻值會於該節點A獲得較高電壓位準，該節 點A之較高電壓位準又會經由一第二反相器（由第二PM〇s電晶體 P2與第二NMOS電晶體M2所組成），而使得該節點B呈現更低 M408099 電壓位準，該節點B之更低電壓位準又會經由一第一反相器（由第 一 PMOS電晶體P1與第一 電晶體M1所組成），而使得該 節點A獲得更高電壓位準，依此循環，即可將該節點a充電至該電 源供應電壓（VDD)，而完成邏輯1的寫入動作。 在此值得注意的是，該第一低電壓節點（VL1)於寫入邏輯丨後， 係具有等於該第四NMOS電晶體（M21)之臨界電壓之電壓位準。 (二）節點A原本儲存邏輯1，而現在欲寫入邏輯1: 在寫入動作發生前（該寫入用字元線為接地電壓），該 • 第一 PM0S電晶體（P1)為導通（〇N>當該寫入用字元線（WWL) 由Low (接地電壓）轉High (該電源供應電壓Vdd)，且該字元線 (WWL)的電壓大於該第=NM〇s電晶體（m3)的臨界電壓時， 該第三NMOS電晶體（M3)由截止（OFF)轉變為導通（ON); 此時因為該寫入用位元線（WBL)是High(該電源供應電壓VDD)， 並且因為該第一 PM0S電晶體（ρι)仍為〇N，所以該節點A的電 壓會維持於該電源供應電壓（VDD)之電壓位準，直到寫入週期結 束。在此值得注意的是，該第一低電壓節點（VLD於寫入邏輯1 % 後’係具有等於該第四NMOS電晶體（M21)之臨界電壓之電壓位 準。 (四）節點A原本儲存邏輯1，而現在欲寫入邏輯〇 : 在寫入動作發生前（該寫入用字元線WWL為接地電壓），該 第一 PMOS電晶體（P1)為導通（on)。當該寫入用字元線（WWL) 由Low (接地電壓）轉High (該電源供應電壓Vdd)，且該寫入用 字元線（WWL)的電壓大於該第三NMOS電晶體（M3)的臨界電 壓時，該第三NMOS電晶體(M3)由截止(OFF)轉變為導通(ON)， 此時因為該寫入用位元線（WBL)是Low (接地電壓），所以會將 該節點A以及該第一低電壓節點（vli)放電而完成邏輯〇的寫入 13 作直到寫入週期結束。在此值得注意的是，該第一低電麼節點 (%〗）於寫入邏輯〇後，係具有接地電壓之位準。 八第6圓所示之本創作較佳實施例，於寫入操作時之HSPICE暫態 析模擬果’如第7圖所示’其係以】evei 49模型且使用TSMC 〇·=微米CMOS抛參數純觀’由該類結果可証實本創作 所提出之具共享_電路之單埠靜罐機存取記隨，能藉由寫入 f輯1時提高該第-低電麼節點（VL1)之電麼位準，以有效避免 習知具單—紅線之雙将紐齡取記紐㉟麟在冑入邏輯丨 相當困難之問題。 (Η )待機模式（standbymode) 此時該待機模式控制信號⑻為邏輯高位準，而該反相待機 模式控撕s號（S)為邏輯低位準，該邏輯低位準之該反相待機模 式控制信號（幻可使得該控制電路⑵中之該第五丽⑽電晶 體（M22)截止（〇FF) ’而該邏輯高位準之該待機模式控制信號 ⑻則使得該第六nM〇S電晶體（M23)導通（〇N)，此時該第 六NMOS電晶體（M23)係作為等化器（equalizer)使用，因此可 藉由呈導通狀態之該第六讓〇s電晶體（廳），以使得該第一低 電壓節點（VL1)之電壓位準相等於該第二低電壓節點（VL2)之 電壓位準’因此該等電壓轉均會等於該第日丽〇5電晶體(M2i ) 之臨界電壓位準。 接下來說明本創作於待機模式（standby m〇de)時如何減少漏 電流’請參考第6圖，第6圖描述有本創作實施例處於待機模式 時戶斤產生之各漏電》il (subthreshold leakage current) Ιι、12、I3 和 I4， 其中假設SRAM晶胞中之該第一反相器之輸出（即節點A )為邏輯 Low(在此值得注意的是，由於待機模式時該第二低電壓節點（) M408099 之電，位準係維持在第四NM0S電晶體（M21)之臨界電壓位準， 因此節點A為邏輯Lgw之電壓位準轉持在該第四刪〇s電晶體 (M21)之臨界電壓位準），而該第二反姆之輸出（即節點b) 為邏輯High (電源供應電壓Vdd)。請參考第5圖之先前技藝與第 ό圖之本猶實_ ’來綱本_職料共享郷電路之單蜂 靜態隨機存取記憶體與第5圖之8T s讀於漏電流方面之比較， 首先關於流經該第三NM〇S電晶體（M3)之漏電流^，由於本創 作於待機模式時節點A之電壓位準係維持在該第四觀〇8電晶體 • (M21)之臨界電壓位準，且假設寫入用字元線（WWL)於待機 模式時係設定成接地電壓，因此本創作之第三麵⑽電晶體⑽） 的閘源極f壓VGS為貞值’反觀於待賊式時第5圖先前技藝之 NM〇S電晶體（M3) _祕電壓Vgs雜Q，根翻極引發没極 >曳漏（Gate Induced Drain Leakage，簡稱 GIDL)效應或 2〇〇5 年 3 月8日第US6865119號專利案第3 (A)及3⑻圖之結果可知， 對於NMOS電晶體而言，閘源極電壓為·〇1伏特時之次臨界電流約 為閘源極電壓為〇伏特時之次臨界電流的1%，因此導因於 • 效，引發之流經本創作之該第三NMOS電晶體（M3)之漏電流 Ιι遠小於第5圖先前技藝之麵〇3電晶體（M3)者；再者，本創 作該第三腕〇8電晶體（M3)之沒源極電壓Vds為該電源供應電 壓VDD扣減該第四圓〇8電晶體（M21)之臨界電麼位準，反觀於 待機模式時傳統第5圖8T靜態隨機存取記憶體之醒〇5電晶體 M3之沒源極電壓Vds係等於該電源供應電壓〜，根據沒極引發 旎障下跌（Drain-Induced Barrier Lowering，簡稱 DIBL)效應，由 於DIBL效應所引發之流經本創作之該第三NMOS電晶體（M3) 之漏電流1丨亦小於第5圖先前技藝之NMOS電晶體（M3)者；結 果’流經本創作之該第三NM〇s電晶體（M3)之漏電流“遠小於 第5圖先前技藝之NM〇s電晶體（M3)者。 接著關於流經該第一 PMOS電晶體（P1)之漏電流〗2，由於待 機模式時該第一 PMOS電晶體（P1)之源極係為該電源供應電壓 (VDD )，而該第一 PMOS電晶體(P1)之汲極係維持在該第四 電晶體（M21)之臨界電壓位準，因此本創作之該第一 pM〇s電晶 體（P1)之源汲極電壓VSD為該電源供應電壓（vDD)扣減該第四 NMOS電晶體（M21)之臨界電壓位準，反觀於待機模式時第5圖 先前技藝之PMOS電晶體（P1)之源汲極電壓VsD係等於該電源供 應電壓（VDD)，根據DIBL效應，因此流經該第一 pM〇s電晶體 (P1)之漏電流I2會小於第5圖先前技藝之PMOS電晶體（P1) 者；最後，關於流經該第二NMOS電晶體（M2)之漏電流13，由 於待機模式時該第二低電壓節點（VL2)之電壓位準係維持在第四 NMOS電晶體（M21)之臨界電壓，節點a之電壓位準亦維持在該 第四NMOS電晶體（M21)之臨界電壓位準，而節點b之電壓位準 係等於該電源供應電壓（VDD)且該第二NM〇s電晶體（M2)之基 底為接地電壓’因此本創作之該第二NMOS電晶體（M2)的基源 極電壓VBS為負值，且該第二NMOS電晶體（M2)之汲源極電壓 VDS為該電源供應電壓（VDD)扣減該第四nmos電晶體（M2i) 之臨界電壓位準’反觀於待機模式時第5圖先前技藝之nmos電晶 體（M2)的基源極電壓VBS等於〇，且nm〇s電晶體（M2)之汲 源極電壓vDS等於該電源供應電壓（Vdd)，根據本體效應（body effect)及DIBL效應可知’流經本創作之該第二麵〇s電晶體(M2 ) 之漏電流I3遠小於第5圖先前技藝之nm〇s電晶體（M2)者。 最後，關於流經NMOS電晶體M4之漏電流u，由於本創作之 具共享控制電路之單埠靜態隨機存取記憶體與傳統8T雙埠靜態隨 機存取記憶體之讀取方式不同，且本創作之具共享控制電路之單琿 靜態隨機存取記憶體待機模式下之讀取用位元線RBL可設定成接 地電壓’而傳統8T雙埠靜態隨機存取記憶體為了防止節點B之電 Μ位準下降，待機模式下之讀取用位元線rbl係設定成電源供應電 壓Vdd ’因此無從比較流經NMOS電晶體Μ4之漏電流14。綜合以 上分析可知，本創作提出之具共享控制電路之單埠靜態隨機存取記 憶體於待機模式時確實可有效減少漏電流》 (III )讀取模式（Readmode) 茲依具共享控制電路之單埠靜態隨機存取記憶體晶胞之二種儲 存資料狀態說明第6圖之具共享控制電路之單埠靜態隨機存取記憶 體如何完成讀取動作。 (一）節點A儲存邏輯0 在讀取動作發生前，（該讀取用字元線RWL為接地電壓）， 該第二NMOS電晶體（M2)為截止（OFF)，該第二PMOS電晶 體（P2)為導通（ON)，節點B為High(電源供應電壓VDD)。 當讀取動作開始時，讀取用字元線（RWL)由Low (接地電壓準） 轉為High(電源供應電壓VDD)，且當該讀取用字元線（RWL)的 電壓大於該第一讀取用電晶體（M4)之臨界電壓時，該第一讀取用 電晶體（M4)由截止（OFF)轉變為導通（ON)，此時由於節點b 為High (電源供應電壓VDD)，該第二讀取用電晶體（M5)為導 通（ON)，因此，會在讀取用位元線（RBL)、該第一讀取用電晶 體（M4)和該第二讀取用電晶體（M5)以及接地間形成電流路徑， 此電流路徑即會使該讀取用位元線（RBL)之電壓位準降低，藉此 即可感測出節點A係儲存邏輯0之資料，並完成邏輯〇的讀取動作。 (二）節點A儲存邏輯1 在讀取動作發生前，（該讀取用字元線RWL為接地電壓），該 第二NMOS電晶體（M2)導通（ON)，該第二PMOS電晶體（p2) 為截止（OFF)，節點B為Low (接地電壓）。當讀取動作開始時， 該讀取用字元線RWL由Low (接地電壓準）轉為High (電源供應 M408099 電壓VDD)，且當該讀取用字元線（RWL)的電壓大於該第一讀取 用電晶體（M4)之臨界電壓時，該第一讀取用電晶體（M4)由截 止（OFF)轉變為導通（ON)，此時由於節點B為Low (接地電 壓）’該第二讀取用電晶體（M5)為截止’因此，並不會在讀取用 位元線（RBL)、該第一讀取用電晶體（M4)和該第二讀取用電晶 體（M5)以及接地間形成電流路徑，結果，讀取用位元線（RBL) 之電壓位準能平穩地保持在High (電源供應電壓Vdd)狀態，藉此 即可感測出節點A係儲存邏輯丨之資料，並完成邏輯丨的讀^動曰作。 至於非操作於寫人、讀取及鑛模式時，由於所有記憶晶胞中之驅 動電晶_祕龍触定祕輯壓，紅作·_於傳統灯 雙埠SRAM晶胞，於此不再累述。V. New description: [New technical field] This creation is about a static random access memory (sram), especially a leakage current. f know that there is a single __ bit material SRAM writer logic 丨 difficult double 埠 static random access memory. [Prior Art] δ hexamedron plays an indispensable role in the computer: L industry. ^ Generally, the memory can be classified as non-volatile according to whether it can save data after the power is turned off (non- Volatile memory and volatile (v〇latile) memory. The storage of non-volatile memory does not disappear due to power off or medium _, while data stored in volatile memory is turned off with power. Or interrupted and eliminated. Common volatile memory types are dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and price, etc., but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed _ and silk work. Missing. On the contrary, the operation of the "SRAM" is easy and does not require an update operation, and therefore has the advantages of high speed and low power consumption. The semiconductor stunner used in mobile electronic devices represented by mobile phones is based on SRAM. This is because SRAM has a small standby current and is suitable for mobile phones with continuous talk time and continuous standby time. The conventional static random access memory (SRAM), as shown in FIG. 1a, mainly includes a memory array (memoly aqing), the memory array is composed of a plurality of memory blocks (memoty block 'MB], MB2, etc., each memory area Μ4〇δ〇99 block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells Composition, each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WI4, WL2, etc.), each word line corresponding to a plurality of columns One of the memory cell cells; and a complex bit line pair (bitlinepairs, BL!, ΒΙΒ^.ΒΙ^, BLBm, etc.), each bit line pair corresponding to one of the plurality of rows of memory cells, and Each bit line pair consists of a bit line (BLi.-.BLm) and a complementary bit line (BLBi...BLBm). Figure lb shows a schematic diagram of a 6T static random access memory (SRAM) cell, where 'PMOS transistors (P1) and (P2) are called load transistors (NMOS transistors) NMOS transistors (Ml) and (M2) are called driving transistors, and NMOS transistors (M3) and (M4) are called access transistors 'WL is word line' and BL And BLB are a bit line and a complementary bit line, respectively, because the sraM unit cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, The cell ratio is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price. The HSPICE % state analysis simulation result of the 6T SRAM cell in the write operation shown in Figure lb is shown in Figure 2, which is simulated by the level 49 model and using TSMC 0.18 micron CM0S process parameters. . The method used to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Fig. 3. The third _ shows a circuit diagram of a 5T SRAM cell with only a single n-line, and the static random sub-fetch of the i-th image. Compared with the sb cell of 'It's 5T static random access memory cell than the 6τ static random access memory « less - «Μ and less - strip line, _ 5τ bribery random access bell ride It is quite difficult to write logic 1 without changing the channel width-to-length ratio of pMGS electrical ρι and ρ2 and touching s 4 M408099 transistor M M2 and M3. Consider the case where the left node of the memory cell is originally stored in the logical state. Since the charge of the node A is only transmitted from the write bit line (wbL) alone, it is difficult to write the previously written logic of the node A into logic. j. Figure 5 shows the 5T SRAM cell, the HSPICE transient analysis simulation result during the write operation. As shown in Figure 4, it uses the level 49 model and uses TSMc 〇 18 μm CMOS process parameters. By simulation, it can be confirmed from the simulation results that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult. To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al.,, A high density, low leakage, 5T SRAM for embedded). Caches, Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And a channel width-to-length ratio of the access transistor to solve the problem of writing logic 1 is difficult to cause damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus susceptible to process variation; Non-Patent Document 2 (M Wieckowski et al., 5 A novel five-transistor (5T) SRAM cell for high performance cache, "IEEE Conference on SOC, pp. 1001-1002, 2005.) 5T SRAM The access transistor of the long channel length is disposed between the two load transistors in the unit cell to solve the problem of difficulty in writing the logic 1, thereby causing a lack of access speed; Patent Document 3 (June 1, 1998) TWM358390) The "SRAM which reduces the power supply voltage during the write operation" can effectively solve the problem of writing logic 1 "but only during write operation" due to the lack of an effective discharge path, resulting in high memory capacity and/or high speed operation. There is a lack of low write speed. Next, we discuss the single-and dual-band architecture of static random access memory (SRAM). The 6T static random access memory (SRAM) cell in lb is the static random memory (SRAM). The unit cell, for example, uses two bit lines bl and blb for reading and writing. That is, both reading and writing are achieved through the same-to-bit line, so that the same-time _ can only To read or write _, therefore, # want to design a double 埠 埠 存取 存取 存取 存取 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲 欲5 shows the circuit, in which ML and WBLB are written by the secret line, coffee and coffee B are read _ bit line, scoop is written with word 7L line, RWL is read treasury line), which makes the memory crystal The area of the lining greatly increases 'if we can simplify the structure of the memory cell, so that one bit line is responsible for reading the action' and the other - bit line is responsible for writing the human action, then design the double 埠 static random access code When you touch it, the memory cell does not need to add two transistors and another pair of 7G lines. The area of the memory cell will decrease. a lot of. The traditional double-click static random access to remember the reason why the cell is not picked up is because the problem of writing logic 1 cannot be achieved as described in the secret. In view of this, the main purpose of this creation is to propose a static random access memory with shared control circuit, which can effectively avoid the conventional double-transfer keystrokes with a single line of 70 lines. It is quite difficult to have a secret of g. The secondary purpose of this creation is to propose a static random access memory with a shared control circuit, which can reduce the leakage current of the Lai mode by controlling the circuit's financial efficiency. [New content] This paper proposes a static random access memory with shared control circuit, which mainly includes a memory array and a plurality of control circuits (2), the memory array is composed of a plurality of memory blocks. Each memory block is provided with a control circuit, and each memory block further includes a plurality of memory cells (1), and each memory cell (1) is accessed by an NMOS transistor. (M3), two NMOS drive transistors (M1 and M2), two PMOS load transistors (pi and P2), and a first and second read transistor (M4 and M5). Each control unit is connected to a source terminal of a second NMOS driving transistor of each memory cell in the corresponding memory block to control source voltages of the source terminals in response to different operating modes, in the write mode And setting a source of the driving transistor (M1) closer to the writing bit line (WBL) in the selected unit cell to a predetermined voltage higher than the ground voltage and selecting another driving transistor in the selected unit cell The source voltage of (M2) is set to the ground voltage to prevent the difficulty of writing logic 1. In the standby mode, 'the source f voltage of all the memory crystals of the memory crystal is set to the high ground voltage. The predetermined voltage is used to reduce the leakage current; and in the read mode, the source voltage of the driving transistor of all the memory cell pads is set to the ground voltage to maintain read stability. In summary, the creation of the shared (4) circuit with the shared (4) circuit of the access control, with the miscellaneous can effectively avoid the knowledge of the single-bit SRAM with a single-bit line of write logic It can also be used to reduce leakage current when in standby mode. Embodiments According to the above main purpose, the present invention provides a single-station static random access memory with a shared control circuit, which mainly includes a note, the memory array is composed of a plurality of record-breaking regions, each The block block further includes a plurality of memory cells (1); and a plurality of health circuits (1), each of which is provided with a control circuit (2). It is worth noting here that the memory boat block can be as simple as a column of memory cells or a row of memory cells. For the sake of convenience, the shared control circuit shown in Figure 6 is statically stored. The memory is only one memory cell (1), one write word line (WWL), one bit line (WBL), one read word line (RWL), and one read bit. The line (RBL) and a control circuit (2) are described as examples. The memory cell (1) includes a first inverter (composed of a first pM〇s transistor P1 and a first NMOS transistor M1) and a second inverter (by a second pM〇s a transistor P2 and a second NMOS transistor M2), a third NMOS transistor (M3), a first read transistor (M4), and a second read transistor (M5). The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second The output of the phase converter (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell, and the third NMOS transistor (M3) is connected between the storage node (a) and the write bit line (WBL). And the gate is connected to the write word line (wwL) for use as an access transistor of the memory cell, and the source, gate and drain of the second read transistor (M5) Minute Connected to a ground voltage, an output of the second inverter (node B) and a source of the first read transistor (M4), a source and a gate of the first read transistor (M4) The > and the poles are respectively connected to the sum of the second read transistor (M5), the read word line (RWL), and the read bit line (RgL). Referring again to FIG. 6, the control circuit (2) is composed of a fourth nmos transistor (M21), a fifth NMOS transistor (M22), a sixth nm 〇S transistor (M23), and a seventh. The NMOS transistor (M24), an ANM〇s transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), and an eleventh NMOS transistor (M28) The source of the fourth nmos M408099 transistor (M21) is connected to a ground voltage, and the gate is connected to the drain line and connected to a first low voltage node (VL1); the fifth_〇8 The source, the gate and the immersion of the transistor (M22) are respectively connected to a ground voltage, an inverted standby mode control signal (3⁄4) and a second low voltage node (VL2), and the sixth NM〇s a source (M23) source, a gate and a drain are respectively connected to the second low voltage node (VL2), a standby mode control signal and the first low voltage node (vli); the seventh NMOS transistor (M24) The source is connected to the ground voltage, the drain is connected to the first low voltage node (VL1), and the gate is connected to the anode of the first ANM〇s transistor (M25). a drain of a nine NM〇S transistor (M26) and a source of a tenth NMOS transistor (M27); a source, a gate and a drain of the eighth nm〇S transistor (M25) are respectively connected to a ground voltage, a write word line (WWL) and a gate of the seventh NMOS transistor (M24); the source, the gate and the drain of the ninth nm 电s transistor (M26) are respectively connected a grounding voltage, the standby mode control signal (S) and a gate of the seventh NMOS transistor (M24); the source, the gate and the immersion of the tenth nm 电s transistor (M27) are respectively connected to a gate of the seventh nmos transistor (M24), an inverting word line ^ψψι ), and a source of a _1 nm 〇S 鲁 Lu crystal (M28); the eleventh nmos transistor (M28) The source, the gate and the gate are respectively connected to the drain of the tenth NMOS transistor (M27), the inverted standby mode control signal (mutual) and a power supply voltage (Vdd). It should be noted here that the inverted standby mode control signal (inter) is obtained by the standby mode control signal (s) via an inverter, and an inverted write word line (WWL) is also This write word line (WWL) is obtained via an inverter. The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and the first time in the write mode The low voltage node (VU) is set to be higher than the ground voltage by 9 M408099 predetermined voltage and the second low voltage node (VL2) is set to the ground voltage to prevent the problem of writing logic 1 _; in the standby mode, The first low voltage node (VU) and the second low voltage _ (VL2) are set to be higher than the grounding voltage to reduce the leakage current; and in the read mode, the first low is The voltage node (VL1) and the second low voltage node (VL2) are set to a ground voltage so that the dimension continues to take stability. The detailed operating voltage level is shown in Table 1, where the voltage at node C is the gate voltage of the seventh NMOS transistor (M24), Max Vtm27) • represents the larger of VTM27 and VTM28. The Vtm27 and the dome 28 respectively indicate a threshold voltage of the tenth NMOS electrode body (M27) and the eleventh NMOS transistor (M28), and V·丨 indicates the first The threshold voltage of the four-sided 〇 电 transistor (M2 i ), it is worth noting that the voltage of the first low voltage node (VL1) is Vtmu when writing 丨, and the first low voltage when writing 〇 The voltage of the node (yj^) is 0V. WE S Node c VL1 VL2 Mode 0 0 VDD-Max(VTM28,VTM27) 0 0 Other 0 V〇d 0 ^TM21 VjM2I Standby Vdd 0 0 VTM21 or 〇0 Write Table 1 Voltage Levels in Various Operating Modes The working mode of the static random access memory with shared control circuit is described as follows: (I) write mode (writemode) (WWL) is a logic high level, the standby mode controls the 10 M408099 signal (s) to a logic low level, and the inverted standby mode control signal (g) is a logic high level, the logic high level of the inverted standby mode control The signal (Xuan) may cause the control circuit (2) to apply the fifth NMOS transistor (M22) to be on, and the logic low level of the standby mode control signal (S) causes the sixth _3 to be electrically The crystal (M23) is turned off (OFF), so that the voltage of the second low voltage node (VL2) can be pulled down to the ground voltage, and the voltage level of the first low voltage node (VL1) is equal to that before the write operation. The level of the threshold voltage of the fourth NMOS transistor (M21) To effectively prevent the problem of difficulty writing a logical one. • Next, the preferred embodiment of the present invention of FIG. 6 illustrates how the write operation is completed, depending on the four write states of the SRAM cell with the shared control circuit. (1) Node A originally stores the logic 〇, but now wants to write logic 〇: Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned on ( ON) »Because the first nmos transistor (Ml) is (ON), the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage Vdd) when the write operation starts. . When the voltage of the write word line (WWL) is greater than the threshold voltage of the third nm 〇s transistor (M3) % (ie, the access transistor), the third NMOS transistor (M3) is turned off ( OFF) turns to ON (0N). At this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 〇 write operation is completed until the end of the write cycle. (2) Node A originally stores the logic 〇, but now wants to write logic 1: Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (Μι) is turned on ( ON). Since the first transistor (M1) is (ON), when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage Vdd), the node The voltage of A rises following the voltage of the write word line (wwl). 11 When the voltage of the write word line (O) is greater than the threshold voltage of the SNMOS transistor (M3), the third surface (10) transistor (M3) is turned from off (〇ff) to on ( ON) 'At this time, because the write bit line (the power supply voltage VDD), and because the first Radisson 5 transistor (5)) is still ON and the node B is still at the voltage level is close to the power supply The initial state of the voltage level of the supply voltage (Vdd), so the first PM〇s transistor ρι is still OFF (OFF) and the node a is rapidly charged toward a divided voltage level, the divided voltage bit The quasi-equal (rm1+Rm2i) / (RM3 + rm1 + rm21) is multiplied by the power supply voltage (Vdd), wherein the RM3 represents the on-resistance equivalent resistance of the third nmos transistor (M3), and the RM1 represents the first The on-resistance equivalent resistance of the NMOS transistor (M1), and the Rm:m represents the on-resistance equivalent resistance of the fourth NMOS transistor (M21), because the third NMOS transistor (M3) still operates in the saturation region ( Saturation regi()n ) and the first NMOS transistor (M1) still operates in a triode region, although the third NMOS transistor The conduction equivalent resistance (rM3) of M3) is much larger than the on-resistance equivalent (rm1) of the first NMOS transistor (M1), but since the fourth NMOS transistor (M21) is connected by a diode, A voltage level equal to the gate-source voltage VGS of the fourth nmos transistor (]V[21) may be provided at the first low-voltage node (VL1), and the voltage-divided voltage level presented by the node a is obtained. The voltage value will be much higher than the voltage level of the node a of the conventional 5T SRAM cell of FIG. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M2), thus causing the node B to discharge to a lower electric gate level. The lower voltage level of the node B causes the The on-resistance equivalent (RM1) of the first NMOS transistor (M1) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M1) obtains a higher voltage level at the node A. The higher voltage level of the node A is again passed through a second inverter (composed of the second PM 〇s transistor P2 and the second NMOS transistor M2), so that the node B exhibits a lower M408099 voltage. Level, the lower voltage level of the node B is again passed through a first inverter (composed of the first PMOS transistor P1 and the first transistor M1), so that the node A obtains a higher voltage level. According to this cycle, the node a can be charged to the power supply voltage (VDD), and the logic 1 write operation is completed. It is worth noting here that the first low voltage node (VL1) has a voltage level equal to the threshold voltage of the fourth NMOS transistor (M21) after writing the logic. (2) Node A originally stores logic 1, and now wants to write logic 1: Before the write operation occurs (the write word line is the ground voltage), the first PM0S transistor (P1) is turned on ( 〇N> when the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage Vdd), and the voltage of the word line (WWL) is greater than the first NM 〇s transistor ( At the threshold voltage of m3), the third NMOS transistor (M3) is turned from off (OFF) to on (ON); at this time, since the write bit line (WBL) is High (the power supply voltage VDD) And because the first PMOS transistor (ρι) is still 〇N, the voltage of the node A is maintained at the voltage level of the power supply voltage (VDD) until the end of the write cycle. The first low voltage node (the VLD is at a write logic of 1%) has a voltage level equal to the threshold voltage of the fourth NMOS transistor (M21). (4) Node A originally stores logic 1, and now wants Write logic 〇: Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor P1) is on. When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage Vdd), and the voltage of the write word line (WWL) is greater than the When the threshold voltage of the third NMOS transistor (M3) is changed, the third NMOS transistor (M3) is turned from OFF to ON, because the write bit line (WBL) is Low ( Ground voltage), so the node A and the first low voltage node (vli) are discharged to complete the logic write 13 until the end of the write cycle. It is worth noting that the first low power node (%)) After writing the logic, it has the level of the ground voltage. The preferred embodiment of the present invention shown in the eighth circle, the HSPICE transient analysis in the write operation is as shown in Figure 7. The shown is 'the system' evei 49 model and uses TSMC 〇·=micron CMOS throw parameters pure view' from this kind of results can confirm the creation of the shared _ circuit of the 罐 static tank machine access record, can By writing the f-series 1 to improve the level of the first-low-power node (VL1), so as to effectively avoid the knowledge of the single-red line It is quite difficult for the new 35 Lin to enter the logic. (Η) Standby mode (standby mode) At this time, the standby mode control signal (8) is a logic high level, and the reverse standby mode control tearing s number (S) is logic. Low level, the logic low level of the inverted standby mode control signal (the magic can make the fifth (10) transistor (M22) in the control circuit (2) cut off (〇FF)' and the logic high level of the standby mode The control signal (8) causes the sixth nM〇S transistor (M23) to be turned on (〇N), and the sixth NMOS transistor (M23) is used as an equalizer, so that it can be turned on. The sixth 〇s transistor (office) such that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2) It will be equal to the threshold voltage level of the day 5 电 5 transistor (M2i). Next, how to reduce the leakage current in the standby mode (standby m〇de) is described. Please refer to Figure 6, which depicts the leakage current generated by the household in the standby mode of the present embodiment. il (subthreshold leakage) Current) Ιι, 12, I3, and I4, where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting that the second low voltage is due to the standby mode) The power of the node () M408099 is maintained at the threshold voltage level of the fourth NM0S transistor (M21), so the node A is the voltage level of the logic Lgw and is transferred to the fourth s transistor (M21). The threshold voltage level), and the output of the second inverse (ie, node b) is a logic high (power supply voltage Vdd). Please refer to the comparison between the previous technique of Figure 5 and the figure of the first figure. The comparison between the single-bee static random access memory of the 'study_worker's shared circuit and the 8T s of the 5th s read in the leakage current First, regarding the leakage current flowing through the third NM〇S transistor (M3), since the voltage level of the node A is maintained in the standby mode, the voltage level of the node A is maintained in the fourth transistor 8 (M21). The threshold voltage level is assumed, and the write word line (WWL) is set to the ground voltage in the standby mode. Therefore, the gate source f voltage VGS of the third side (10) transistor (10) of the present creation is a threshold value. In the case of the thief-style, the previous technique of NM〇S transistor (M3) _ secret voltage Vgs is Q, the root inversion Drill Leakage (GIDL) effect or 2〇〇 As can be seen from the results of Figures 3 (A) and 3 (8) of the US Pat. No. 6,865,119 on March 8, 5, for the NMOS transistor, the subcritical current of the gate source voltage is 〇1 volt is about the gate source voltage. It is 1% of the critical current of the volts, so it is caused by the effect, and the third NMOS transistor that flows through the creation is triggered. The leakage current Ιι of M3) is much smaller than that of the prior art 〇3 transistor (M3) of Fig. 5; further, the source voltage Vds of the third wristband 8 transistor (M3) is the power supply. The voltage VDD deducts the critical electric level of the fourth circular 电8 transistor (M21), and in the standby mode, the conventional 5th FIG. 8T static random access memory wakes up the 5 transistor M3 without the source voltage. Vds is equal to the power supply voltage ~, according to the Drain-Induced Barrier Lowering (DIBL) effect, the leakage current of the third NMOS transistor (M3) flowing through the creation due to the DIBL effect 1丨 is also smaller than the NMOS transistor (M3) of the prior art of FIG. 5; as a result, the leakage current flowing through the third NM〇s transistor (M3) of the present invention is “far less than the NM〇s of the prior art of FIG. 5”. The transistor (M3) is next to the leakage current of the first PMOS transistor (P1), and the source of the first PMOS transistor (P1) is the power supply voltage (VDD) in the standby mode. And the drain of the first PMOS transistor (P1) is maintained in the fourth transistor (M21) The threshold voltage level, so the source bucker voltage VSD of the first pM〇s transistor (P1) of the present invention is the power supply voltage (vDD) minus the threshold voltage level of the fourth NMOS transistor (M21) In contrast, in the standby mode, the source drain voltage VsD of the PMOS transistor (P1) of the prior art of FIG. 5 is equal to the power supply voltage (VDD), and therefore flows through the first pM〇s transistor according to the DIBL effect ( The leakage current I2 of P1) will be smaller than that of the prior art PMOS transistor (P1) of FIG. 5; finally, regarding the leakage current 13 flowing through the second NMOS transistor (M2), the second low voltage due to the standby mode The voltage level of the node (VL2) is maintained at the threshold voltage of the fourth NMOS transistor (M21), and the voltage level of the node a is also maintained at the threshold voltage level of the fourth NMOS transistor (M21), and the node b The voltage level is equal to the power supply voltage (VDD) and the base of the second NM〇s transistor (M2) is the ground voltage. Therefore, the base-source voltage VBS of the second NMOS transistor (M2) is originally created. Is a negative value, and the source voltage VDS of the second NMOS transistor (M2) supplies power to the power source The voltage (VDD) deducts the threshold voltage level of the fourth nmos transistor (M2i). When viewed in the standby mode, the base-source voltage VBS of the nmos transistor (M2) of the prior art of FIG. 5 is equal to 〇, and nm〇 The source voltage vDS of the s transistor (M2) is equal to the power supply voltage (Vdd), and according to the body effect and the DIBL effect, it is known that the second surface 〇s transistor (M2) flowing through the creation is leaked. The current I3 is much smaller than that of the prior art nm〇s transistor (M2) of Figure 5. Finally, regarding the leakage current u flowing through the NMOS transistor M4, the static random access memory of the shared control circuit of the present invention is different from the conventional 8T dual-static static random access memory, and The read bit line RBL in the standby mode of the shared static control memory is set to the ground voltage' while the traditional 8T dual-static static random access memory is used to prevent the node B from being powered. The level is lowered, and the read bit line rbl in the standby mode is set to the power supply voltage Vdd' so that the leakage current 14 flowing through the NMOS transistor Μ4 is not compared. Based on the above analysis, the static random access memory with shared control circuit proposed in this creation can effectively reduce leakage current in standby mode. (III) Read mode (Readmode)二Static Random Access Memory Cell Two Storage Data States Description Figure 6 shows how the static random access memory of the shared control circuit completes the read operation. (1) Node A stores logic 0. Before the read operation occurs, (the read word line RWL is the ground voltage), the second NMOS transistor (M2) is turned off (OFF), and the second PMOS transistor (P2) is ON (ON), and Node B is High (power supply voltage VDD). When the read operation starts, the read word line (RWL) is changed from Low (ground voltage) to High (power supply voltage VDD), and when the read word line (RWL) voltage is greater than the first When the threshold voltage of the transistor (M4) is read, the first read transistor (M4) is turned from OFF to ON, and since the node b is High (power supply voltage VDD) The second read transistor (M5) is turned on (ON), and therefore, the read bit line (RBL), the first read transistor (M4), and the second read A current path is formed between the transistor (M5) and the ground, and the current path lowers the voltage level of the read bit line (RBL), thereby sensing the data of the node A storing the logic 0. And complete the logic 〇 read action. (2) Node A stores logic 1 Before the read operation occurs, (the read word line RWL is the ground voltage), the second NMOS transistor (M2) is turned on (ON), and the second PMOS transistor ( P2) is OFF (OFF) and Node B is Low (ground voltage). When the read operation starts, the read word line RWL is turned from Low (ground voltage quasi) to High (power supply M408099 voltage VDD), and when the read word line (RWL) voltage is greater than the first When the threshold voltage of the transistor (M4) is read, the first read transistor (M4) is turned from off (OFF) to on (ON), at which time the node B is Low (ground voltage). The second read transistor (M5) is turned off. Therefore, it is not in the read bit line (RBL), the first read transistor (M4), and the second read transistor ( A current path is formed between M5) and the ground. As a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High (power supply voltage Vdd) state, thereby sensing the node A system storage logic.丨 丨 ,, and complete the reading of the logic ^. As for the non-operational writing, reading and mining modes, due to the driving electro-crystal in all memory cells, the secret is pressed, the red light is _ in the traditional lamp double-埠 SRAM cell, no longer Repeated.
18 M408099 【圖式簡單說明】 第la圖係顯示習知之靜態隨機存取記憶體，第lb圖係顯示習知6T 靜態隨機存取記憶體晶胞之電路示意圖； 第2圖係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖； 第3圖係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖； 第4圖係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖； 第5圖係顯示習知雙埠靜態隨機存取記憶體晶胞之電路示意圖； 第6圖係顯示本創作較佳實施例所提出之之電路示意圖； 第7圖係顯示第6圖之本創作較佳實施例之寫入動作時序圖。18 M408099 [Simple description of the drawing] The first drawing shows the conventional static random access memory, the lb is a schematic circuit diagram showing the conventional 6T static random access memory unit cell; the second figure shows the conventional 6T Schematic diagram of the write operation of the SRAM cell; Figure 3 shows the circuit diagram of the conventional 5T SRAM cell; Figure 4 shows the conventional 5T SRAM Schematic diagram of the write operation of the cell; Figure 5 is a schematic diagram showing the circuit of the conventional double-static static random access memory cell; Figure 6 is a schematic diagram showing the circuit proposed by the preferred embodiment of the present invention; A timing chart of the write operation of the preferred embodiment of the present invention is shown in FIG.
19 M408099 【主要元件符號說明】19 M408099 [Main component symbol description]
P1 第一 PMOS電晶體 P2 第二PMOS電晶體 Ml 第一 NMOS電晶體 M2 第二NMOS電晶體 M3 第三NMOS電晶體 BL 位元線 A 儲存節點 B 反相儲存節點 Ιι 漏電流 h 漏電流 h 漏電流 I4 漏電流 S 待機模式控制信號 S 反相待機模式控制信號 VL1 第一低電壓節點 VL2 第二低電壓節點 M21 第四NMOS電晶體 M22 第五NMOS電晶體 M23 第六NMOS電晶體 M24 第七NMOS電晶體 M25 第八NMOS電晶體 M26 第九NMOS電晶體 M27 第十NMOS電晶體 M28 第十一 NMOS電晶體 M4 第一讀取用電晶體 M5 第二讀取用電晶體 WWL 寫入用字元線 WWL 反相寫入用字元線 RBL 讀取用位元線 RWL 讀取用字元線 1 SRAM晶胞 2 控制電路 BLr _BLm 位元線 WL, WLn 字元線 BLB 互補位元線 MBr MBk 記憶體區塊 BLB i“BLBm互補位元線 V〇d 電源供應電壓 20P1 first PMOS transistor P2 second PMOS transistor M1 first NMOS transistor M2 second NMOS transistor M3 third NMOS transistor BL bit line A storage node B inversion storage node Ιι leakage current h leakage current h leakage Current I4 Leakage current S Standby mode control signal S Inverting standby mode control signal VL1 First low voltage node VL2 Second low voltage node M21 Fourth NMOS transistor M22 Fifth NMOS transistor M23 Sixth NMOS transistor M24 Seventh NMOS Transistor M25 eighth NMOS transistor M26 ninth NMOS transistor M27 tenth NMOS transistor M28 eleventh NMOS transistor M4 first read transistor M5 second read transistor WWL write word line WWL inverting write word line RBL read bit line RWL read word line 1 SRAM cell 2 control circuit BLr _BLm bit line WL, WLn word line BLB complementary bit line MBr MBk memory Block BLB i "BLBm complementary bit line V〇d power supply voltage 20