TWM399432U - Thermally enhanced thin flip-chip package - Google Patents

Thermally enhanced thin flip-chip package Download PDF

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Publication number
TWM399432U
TWM399432U TW099218883U TW99218883U TWM399432U TW M399432 U TWM399432 U TW M399432U TW 099218883 U TW099218883 U TW 099218883U TW 99218883 U TW99218883 U TW 99218883U TW M399432 U TWM399432 U TW M399432U
Authority
TW
Taiwan
Prior art keywords
insulating layer
heat
chip package
wafer
package structure
Prior art date
Application number
TW099218883U
Other languages
English (en)
Inventor
Chin-Tang Hsieh
Hou-Chang Kuo
Dueng-Shiu Tzou
Chia-Jung Tu
Gwo-Shyan Sheu
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW099218883U priority Critical patent/TWM399432U/zh
Publication of TWM399432U publication Critical patent/TWM399432U/zh
Priority to US13/163,913 priority patent/US8497571B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

五、新型說明： 【新型所屬之技術領域】 [0001] 本創作係有關於一種覆晶封裝構造，特別係有關於 一種薄型散熱覆晶封裝構造。 【先前技術】 [0002] 如第1圖所示’習知薄型覆晶封裝構造1 〇係包含一基 板11、一晶片12、一攔壩13、一封膠體14及一散熱膠15 ’該基板11係具有一上表面11a、一下表面lib及一貫穿 該上表面11 a及該下表面11 b之通孔11 c，該晶片1 2係設 置於該基板11之該上表面11a且電性連接於該基板11，該 晶片12係具有複數個凸塊1_’ _攔^彬成於該基板 11之該上表面11 a且位於該_孔丨沙£术锏、★封膠體14係 形成於該基板11之該上表面1 la且包覆該些凸塊12a，該 散熱膠15係填充於該通孔lie，其中該攔壩丨3係用以擋止 該封膠體14 ’以防止該封膠體14流入於該基板11之該通 ；» **. 孔lie内而污染該散熱膠15〜，但若該攔壩13之高度過高， , 1 ： 則容易導致該晶片12之該些-凸:¾ 12 a無法順利接合至該基 板11 ’反之，若該攔壩13之高度太低，則該攔壩13與該 晶片12之間會形成有空隙（圖未繪出），而導致該封膠 體14由空隙溢流至該基板11之該通孔11 c而污染該散熱膠 15 ° 【新型内容】 [0003] 本創作之主要目的係在於提供一種薄型散熱覆晶封 裝構造’該薄型散熱覆晶封裝構造係包含一基板、一晶 片以及一散熱膠，該基板係具有一絕緣層及一線路層， 表箪編號A0101 第3頁/共16頁 M399432 該絕緣層係具有一上表面、一下表面及複數個形成於該 下表面之凹穴，其中該絕緣層之該下表面係具有一凹穴 設置區及一位於該凹穴設置區外側之非凹穴設置區，該 些凹穴係位於該凹穴設置區且各該凹穴係具有一側壁及 一連接該側壁之底面，各該凹穴之該底面與該絕緣層之 該上表面之間係具有一第一厚度，該絕緣層之該上表面 及該下表面之間係具有一第二厚度，該第二厚度係大於 該第一厚度，該線路層係形成於該絕緣層之該上表面， 該晶片係設於該絕緣層之該上表面，該晶片係具有一晶 片表面及複數個凸塊，該晶片表面係對應於該凹六設置 _，Ί..:. 由於該些凹穴係設置於該絕緣厣之該下表面的該凹穴設 置區，且各該凹穴係具有該側壁及該底面，因此該散熱 膠係可填充於該些凹穴且接觸各該凹穴之該侧壁及該底 面以增加該散熱膠與該絕緣.層之接觸面積，進而提高該 散熱膠與該絕緣層之結合強度，且當一封膠體形成於該 絕緣層之該上表面時，該封膠體係可被限位於該晶片及 該絕緣層之間，因此不需額外設置攔壩，具有節省成本 及縮短製程之功效。 【實施方式】 [0004] 區且該些凸塊係電性連接於雜散#膠係至少 填充於該些凹穴:且該散熱膠穴爹該底面。 請參閱第2圖，其係本創作之一較佳實施例，一種薄 型散熱覆晶封裝構造100係包含一基板110、一晶片120 、一散熱膠130以及一封膠體140，該基板110係具有一 絕緣層111及一線路層112，該絕緣層111係具有一上表 表單编號A0101 第4頁/共16頁 面111a、一下表面111b及複數個形成於該下表面uib之 凹穴111 c，其中該絕緣層111之該下表面11丨^(係具有一 凹穴設置區111 d及一位於該凹穴設置區111 d外側之非凹 穴設置區llle，該些凹穴111c係位於該凹穴設置區iiid 且各該凹穴111 c係具有一側壁111 f及一連接該側壁111 f 之底面11 lg，各該凹六111c之該底面11 lg與該絕緣層 111之該上表面11 la之間係具有一第一厚度T1，該絕緣 層111之該上表面111 a及該下表面111 b之間係具有一第 二厚度T2，該第二厚度T2係大於該第一厚度T1，該線路 層112係形成於該絕緣層111之該上表面11 ia，該晶片 120係設於該絕緣層111之該上表面Ilia >該晶片12〇係 . --· : - 具有一晶片表面121及複數個凸塊1.22"，該晶片表面121 ：- ’：· . -；' 係對應於該凹穴設置區11 ldi該4 Λ塊ί22係電性連接於 該線路層112，該散熱膠130係至少填充於該些凹穴lllc 且該散熱膠130係接觸各該凹穴111c之該底面lllg，較 佳地，該散熱膠130係接觸各該凹穴1;1 lc之該側壁111 f 及該絕緣層111之該下表面11 lb;以增加該散熱膠130與該 絕緣層111之接觸面積，進而為:高备散熱膠130與該絕緣 層111之結合強度，此外，在本實施例中，該散熱穋13 0 係具有複數個導熱顆粒131，該些導熱顆粒131係選自於 錫、銀、銅、钢、船、録、金、絲、銘、氧化銘，氮化 铭，氮化蝴’蝴化欽、二蝴化鈦、碳化石夕、石墨及其等 之組成物，該封膠體140係形成於該絕緣層111之該上表 面111a並包覆該晶片120之該些凸塊122。由於該些凹穴 111 c係設置於該絕緣層111之該下表面111 b的該凹六設 置區11 Id ’且各該凹穴lllc係具有該側壁11 If及該底面 表單編號A0101 第5頁/共16頁 M399432 II lg，因此該散熱膠130係可填充於該些凹穴lllc且接 觸各該凹穴11 lc之該側壁1 11 f及該底面11 lg以增加該散 熱膠130及該絕緣層111之接觸面積，進而提高該散熱膠 130與該絕緣層111之結合強度，且當該封膠體14〇形成 於該絕緣層111之該上表面111a時，該封膠體140係可被 限位於該晶片120及該絕緣層111之間，因此不需額外設 置攔壩，具有節省成本及縮短製程之功效。 [0005] 接著’請參閱第3 A至3 D圖，其係本創作之一較佳實 施例之製程流程圖，首先，請參閱第3A圖，提供一基板 110，該基板110係具有一絕緣層111及一線路層112，該 絕緣層111係具有一上表面与緩一 1 b，其中 該絕緣層111之該下表面11冬設置區丨i ld 及一位於該凹六設置區1 1 1 d外側之非凹穴設置區1 11 e， 該線路層112係形成於該絕緣層ill之該上表面llla，接 著，請參閱第3B圖，設置一晶片1 2 0於該絕緣層111之該 上表面llla ’該晶片120係具有一晶片表面121及複數個 凸塊122，該晶片表面121係對應於該凹穴設置區uid且 該些凸塊122係電性連接於該線路層112，之後，請參閱 第3C圖，形成一封膠體140於該絕緣層ill之該上表面 llla並包覆該晶片120之該些凸塊122，接著，請參閱第 3D圖’利用雷射方式由該絕緣層111之該下表面丨1 ib形 成複數個凹穴111 c ’該些凹穴111 c係位於該凹穴設置區 III d且各該凹穴111 c係具有一側壁111 f及一連接該侧壁 liif之底面liig，各該凹穴111〇之該底面1118與該絕 緣層111之該上表面11 la之間係具有一第一厚度^，該 表單編號A0101 第6頁/共16頁 M399432 絕緣層111之該上表面111 a及該下表面]丨〗b之間係具有 一第二厚度T2，該第二厚度T2係大於該第一厚度τι，最 後，填充一散熱膠130於該絕緣層ill之該下表面1111}及 該些凹穴111 c内以形成如第2圖所示之薄型散熱覆晶封裝 構造100。 [_6] 另，請參閱第4圖，其係本創作之另一具體實施例， 另一種薄型散熱覆晶封裝構造2〇〇係包含一基板21〇、一 晶片220、一散熱膠230、一封膠體240以及一散熱片250 ’該基板21 0係具有一絕緣層211及一線路層21 2，該絕 緣層211係具有一上表面211a ' —下表面21 lb及複數個 形成於該下表面211b之凹穴;2:11 c，莫.中該、絕緣層211之 該下表面211b係具有一凹穴設堇區(2:ί 及一位於該凹穴 * ν:·.. 設置區21 Id外側之非凹穴設置區21 le，該些凹穴211c係 位於該凹穴設置區21 Id且各該凹穴211c係具有一側壁 21 If及一連接該側壁21 If之底面21 lg，各該凹穴21lc j 之該底面211 g與該絕緣層211之該上表面211 a之間係具 有一第一厚度T3，該絕緣層211之該上表面211a及該下 表面21 lb之間係具有一第二厚度T4，該第二厚度T4係大 於該第一厚度T3 ’該線路層212係形成於該絕緣層211之 該上表面211a，該晶片220係設於該絕緣層211之該上表 面211a ’該晶片220係具有一晶片表面221及複數個凸塊 222 ’該晶片表面221係對應於該凹穴設置區211 d且該些 凸塊222係電性連接於該線路層212，該散熱膠230係至 少填充於該些凹穴211c且該散熱膠230係接觸各該凹穴 211c之該底面211g，較佳地，該散熱膠230係接觸各該 表單編號A0101 第7頁/共16頁 M399432 凹穴211c之該側壁211 f及該絕緣層211之該下表面21 lb 以增加該散熱膠230與該絕緣層2Π之接觸面積，進而提 高該散熱膠230與該絕緣層211之結合強度，該封膠體 2 4 0係形成於該絕緣層211之該上表面211 a並包覆該晶片 2 2 0之該些凸塊2 2 2 ’該散熱片2 5 0係設置於該絕緣層211 之該下表面211b並接觸該散熱膠230以增加散熱效率。 [0007] 本創作之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本創作之精神 和範圍内所作之任何變化與修改，均屬於本創作之保護 範圍。 【圖式簡單說明】 歲：:：g [0008] 第1圖：習知薄型覆晶封裝樓造示:意5齒’。 第2圖：依據本創作之一較佳實施例，一種薄型散熱覆晶 封裝構造之截面示意圖。 第3A至3D圖：依據本創作之一較佳實施例，該薄型散熱 覆晶封裝構造之流程圖。 第4圖：依據本創作之另一具體實施例，另—種薄型散熱 覆晶封裝構造之載面示意圖。 【主要元件符號說明】 [0009] 10薄型覆晶封裝構造 11基板 11 b下表面 12晶片 13摘壞 15散熱膠 表單編號A0101 11 a上表面 11c通孔 12a凸塊 14封膠體 第8頁/共16頁 100薄型散熱覆晶封裝構造 110基板 111絕緣層 111a上表面 111b下表面 111 c凹穴 llld凹穴設置區 1 lie非凹穴設置區 lllf側壁 lllg底面 112線路層 120晶片 121晶片表面 122凸塊 130散熱膠 131導熱顆粒 140封膠體 T1第一厚度 T2第二厚度 200薄型散熱覆晶封裝構造 ..... 210基板 211碴緣層 211a上表面 211b下表面 211 c凹穴 211d凹穴設置區 211e非凹穴設置區 21 If側壁 211 g底面 212線路層 220晶片 221晶片表面 222凸塊 230散熱膠 240封膠體 250散熱片 T3第一厚度 T4第二厚度 表單编號A0101 第9頁/共16頁

Claims (1)

  1. M399432 六、申請專利範圍： 1 . 一種薄型散熱覆晶封裝構造，其包含二 -基板，錢具有—職層及—線路層該絕緣層係具有 一上表面、—下表面及複數個形成於該下表面之凹六，其 中該絕緣層之該下表面係具有一凹穴設置區及一位於該凹 穴設置區外側之非凹穴設置區，該些凹穴係位於該凹穴設 置區且各該凹穴係具有一側壁及一連接該側壁之底面，各 該凹穴之該底面與該絕緣層之該上表面之間係具有一第一 厚度，該絕緣層之該上表面及該下表面之間係具有一第二 厚度，該第二厚度係大於該第一厚度，該線路層係形成於 該絕緣層之該上表面； 一晶片，其係設於該絕緣層义|該年案运·，該*片係具 ... '"ΐ ' V '-f- · - v -· 晶片表面及複數個凸塊，該晶片以面係^丨i於該凹穴設置 區且該些&塊係電性連接於該線路層；以及 一散熱膠，其係至少填充於該些凹穴且該散熱膠係接觸各 該凹穴之該底面。 2 .如申請專利範圍第1項所述之薄型散熱覆晶封裝構造其 中該散熱膠係接觸各該凹穴之該側壁。 3 .如申請專利範圍第1項所述之薄型散熱覆晶封裝構造，其 中該散熱膠係接觸該絕緣層之該下表面。 4 ·如申請專利範圍第1項所述之薄型散熱覆晶封裝構造，其 另包含有一封膠體’該封膠體係形成於該絕緣層之該上表 面並包覆該晶片之該些凸塊。 5 .如申請專利範圍第1項所述之薄型散熱覆晶封裝構造，其 中該散熱膠係具有複數個導熱顆粒，該些導熱顆粒係選自 099218883 表單編號A0101 第10頁/共16頁 0992058100-0 M399432 於錫、銀、銅、錮、鉛、銻、金、鉍、鋁、氧化鋁，氮化 鋁，氮化硼，硼化鈦、二硼化鈦、碳化矽、石墨及其等之 組成物。 6 .如申請專利範圍第1項所述之薄型散熱覆晶封裝構造，其 另包含有一散熱片，該散熱片係接觸該散熱膠。
    099218883 表單編號A0101 第11頁/共16頁 0992058100-0
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