TWM298777U - Multi-layer superlattice high-power transistor - Google Patents

Multi-layer superlattice high-power transistor Download PDF

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TWM298777U
TWM298777U TW95203065U TW95203065U TWM298777U TW M298777 U TWM298777 U TW M298777U TW 95203065 U TW95203065 U TW 95203065U TW 95203065 U TW95203065 U TW 95203065U TW M298777 U TWM298777 U TW M298777U
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superlattice
layer
gan
algan
buffer layer
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TW95203065U
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Chinese (zh)
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Shiau-Min Chen
Fang-Bang Chiou
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Arima Optoelectronics Corp
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AOC-05-29-TW AOC-05-29-TWM298777 八、新型說明: 【新型所屬之技術領域】 本創作係有關一種高功率電晶體,尤指一種以 AlGaN/GaN多層超晶格做緩衝層之高電子移動率電晶體 (High Electron Mobility Transistor,HEMT)。 【先前技術】 按,最近幾年網際網路與行動電話等資訊通信系統的發 展極為快速,要求通信網路高速化、大容量化已成為全球各 國的共識,而支撐IT產業主要支柱就是化合物半導體元件 (device) 〇 典型的GaAs與InP等化合物半導體會被應用於高頻元 件,理由之一是它的電子移動速度非常快。AlGaAs,InGaAs, InGaP等包含混晶半導體在内的化合物半導體都採用異質 (hetero)構造,因此可按照預期特性設計band結構。目前高 頻元件正朝著高速化與高功率化兩個方向發展,實際上高頻 元件必需根據使用要求,並考慮材料物性後才能決定最適當 的元件材料與結構。 而,以砷化鎵(GaAs)為主的高電子移動率電晶體(High Electron Mobility Transistor,HEMT),或稱之為高功率電晶體, 係比矽具有一較高的電子移動率(大約是6000cm2/V-s)和一 較低電源極電阻,使得以GaAs為主的元件可以操作在更高 的頻率。然而,GaAs具有一相對小的能隙(室溫下為1.42電 子伏特)和相對小的崩潰電壓,因此阻礙了以GaAs為主的 HEMT在高頻時提供高功率。 -5-AOC-05-29-TW AOC-05-29-TWM298777 VIII. New Description: [New Technology Field] This creation is about a high-power transistor, especially a buffer layer with AlGaN/GaN multilayer superlattice. High Electron Mobility Transistor (HEMT). [Prior Art] In recent years, the development of information communication systems such as Internet and mobile phones has become extremely fast. The demand for high-speed and large-capacity communication networks has become the consensus of all countries in the world. The main pillar supporting the IT industry is compound semiconductors. Devices 化合物 Typical compound semiconductors such as GaAs and InP are used in high-frequency components. One of the reasons is that their electrons move very fast. Compound semiconductors including mixed crystal semiconductors such as AlGaAs, InGaAs, and InGaP use a hetero structure, so that the band structure can be designed in accordance with the intended characteristics. At present, high-frequency components are moving in the direction of high speed and high power. In fact, high-frequency components must be determined according to the requirements of use, and the material properties of materials can be used to determine the most appropriate component materials and structures. However, a high-electron Mobility Transistor (HEMT) based on gallium arsenide (GaAs), or a high-power transistor, has a higher electron mobility than 矽 (about 6000cm2/Vs) and a lower power supply pole resistor allow GaAs-based components to operate at higher frequencies. However, GaAs has a relatively small energy gap (1.42 electron volts at room temperature) and a relatively small breakdown voltage, thus preventing the GaAs-based HEMT from providing high power at high frequencies. -5-

M298777 AOC-05-29-TW 是以,AlGaN/GaN半導體材料製造的改良集中關注於 AlGaN/GaN高功率電晶體用在高頻、高溫及高功率應用的 發展上。AlGaN/GaN有著大能隙,高峰值和飽和電子速度 值。這些特性使得AlGaN/GaN高功率電晶體可以在較高的 頻率下提供高功率。 惟,因缺少晶格匹配的基板,目前成長多用藍寶石 (Sapphire)或者碳化石夕(SiC)做基板,然這些材料彳賈格昂貴,且 藍寶石是絕緣體,所以用Si做基板一直是業者的期待,只是 Si也是與GaN晶格不匹配,而極易產生高的錯位缺陷 (Dislocation),而且其熱膨脹係數2.59父10·6!^與GaN之5 59 X 10 6K 1差別更大,以致當GaN厚度超過l//m時會發生裂 痕。另外Si易與氨(Ammonia)產生SixNy成為絕緣體阻止 GaN之成長。 用MOCVD成長GaN在Si上還有一難處就是回融腐餘 (Meltback Etching),在南溫時Ga與Si易成合金產生極快的 腐蝕反應,將基板及成長的結晶層摧毀,產生粗糙的表面以 及有深洞的基板,因此一般成長GaN在Si時都先成長一層 緩衝層A1N約25nm厚以保護Si。 第一圖所示,為習用一典型的AlGaN/GaN高功率電晶 體(1〇〇),其包含一緩衝層(20)緊鄰一藍寶石或碳化矽基板 (10),一 GaN通道層(channel layer)形成於該GaN緩衝層(20) 上,及一 u-AlGaN障壁層(40)則形成於該GaN通道層(30)之 上。另,源極(50)與汲極(7〇)構成穿越AlGaN障壁層(40)表面 至位於GaN通道層(30)頂之歐姆接點,而閘極(60)即構成對 AlGaN障壁層(4〇)表面之非歐姆接觸。由於晶格中存有鋁 -6 -M298777 AOC-05-29-TW is an improvement in the fabrication of AlGaN/GaN semiconductor materials focused on the development of high-frequency, high-temperature and high-power applications for AlGaN/GaN high-power transistors. AlGaN/GaN has large energy gaps, high peaks and saturated electron velocity values. These characteristics allow AlGaN/GaN high power transistors to provide high power at higher frequencies. However, due to the lack of lattice-matched substrates, sapphire or SiC is currently used as a substrate. However, these materials are expensive and sapphire is an insulator. Therefore, it has always been the expectation of using Si as a substrate. However, Si is also mismatched with GaN lattice, and it is easy to produce high dislocation defects (Dislocation), and its thermal expansion coefficient of 2.59 parent 10.6!^ is more different from GaN's 5 59 X 10 6K 1 , so that when GaN Cracks occur when the thickness exceeds l//m. In addition, Si easily produces a SixNy with ammonia (Ammonia) as an insulator to prevent the growth of GaN. Another difficulty in growing GaN on MO by MOCVD is Meltback Etching, which produces a very fast corrosion reaction between Ga and Si alloys at south temperature, destroying the substrate and the growing crystal layer, resulting in a rough surface. As well as a substrate having a deep hole, in general, when GaN is grown in Si, a buffer layer A1N is grown to a thickness of about 25 nm to protect Si. The first figure shows a typical AlGaN/GaN high-power transistor (1〇〇), which comprises a buffer layer (20) next to a sapphire or tantalum carbide substrate (10), a GaN channel layer (channel layer). Formed on the GaN buffer layer (20), and a u-AlGaN barrier layer (40) is formed over the GaN channel layer (30). In addition, the source (50) and the drain (7〇) constitute an ohmic junction across the surface of the AlGaN barrier layer (40) to the top of the GaN channel layer (30), and the gate (60) constitutes a pair of AlGaN barrier layers ( 4〇) Non-ohmic contact of the surface. Because of the presence of aluminum -6 in the crystal lattice

AOC-05-29-TW AOC-05-29-TWM298777 (A1),故AlGaN之能隙較GaN寬,因此,該GaN通道層(30)與 AlGaN障壁層(40)間介面形成異質結構。 然,上述習知HEMT結構面臨磊晶膜之間的晶格不匹配 及熱膨脹係數之差異,故容易在異質界面累積應變能,這些 應變能在元件製造及使用過程往往會形成錯位缺陷 (Dislocation)以釋放能量,部分錯位缺陷會延伸至晶體表面, 造成品質劣化之缺失,故仍未盡理想,尚有改善空間。 【新型内容】 本創作之主要目的,係在提供一種多層超晶格高功率電 晶體,其係以AlGaN/GaN多層超晶格做緩衝層,不但可以減 少應變能,也可以降低錯位缺陷(Dislocation),具有提昇 HEMT磊晶品質之功效增進。進一步,並可提高移動率 (Mobility),及改善靜電放電保護能力。 為達上述目的,本創作所採用之技術手段包含: 一基板; 一由多層氮化鋁鎵(AlGaN)/氮化鎵(GaN)所構成之超 晶格緩衝層,形成於該基板上;以及 一電晶體磊晶結構,形成於該AlGaN/GaN超晶格緩衝 層上。 依據前揭在bulk GaN緩衝層插入超晶格結構之特徵, 本發明另一可行實施例包含: 一基板; 一成核層,係形成於該基板上; 一第一緩衝層,係形成於該成核層上; 一多層AlGaN/GaN所形成之超晶格結構,係形成於該 -7-AOC-05-29-TW AOC-05-29-TWM298777 (A1), so the energy gap of AlGaN is wider than that of GaN, and therefore, the interface between the GaN channel layer (30) and the AlGaN barrier layer (40) forms a heterostructure. However, the conventional HEMT structure faces the lattice mismatch and the difference in thermal expansion coefficient between the epitaxial films, so it is easy to accumulate strain energy at the hetero interface, and these strains often form dislocation defects during component manufacturing and use. In order to release energy, some of the misaligned defects will extend to the surface of the crystal, resulting in the lack of quality degradation, so it is still not ideal, there is still room for improvement. [New content] The main purpose of this creation is to provide a multi-layer superlattice high-power transistor, which uses AlGaN/GaN multi-layer superlattice as a buffer layer, which can reduce strain energy and reduce misalignment defects (Dislocation). ), has the effect of improving the quality of HEMT epitaxial. Further, it is possible to improve the mobility rate and improve the electrostatic discharge protection capability. In order to achieve the above object, the technical means adopted by the present invention comprises: a substrate; a superlattice buffer layer composed of a plurality of layers of aluminum gallium nitride (AlGaN)/gallium nitride (GaN) formed on the substrate; A transistor epitaxial structure is formed on the AlGaN/GaN superlattice buffer layer. According to a feature of the prior art, a superlattice structure is inserted into the bulk GaN buffer layer. Another possible embodiment of the present invention comprises: a substrate; a nucleation layer formed on the substrate; a first buffer layer formed on the substrate On the nucleation layer; a superlattice structure formed by a multilayer of AlGaN/GaN is formed in the -7-

AOC-05-29-TW AOC-05-29-TWM298777 第一緩衝層上; 第一緩衝層,係形成於該超晶格結構上; 一通道層,係形成於該第二緩衝層上; 一障壁層,係形成於該通層上;以及 一源極、汲極、閘極係分別形成於該障壁層上。 【實施方式】 首先,請參閱第二圖所示,其係揭示本創作高功率電晶 體(200)之剖面示意圖,其包含有: 一基板(10),係選自包括碳化矽(SiC)、氮化鎵(GaN)及氧 化I呂(Al2〇3)其中任一材質所構成。 一成核層(11),係形成於該基板(10)上,但不限定於此,亦 即可視基板(10)材質而作一選擇,較佳之成核層(11)材料為 A1N(氮化鋁),但不限定於此。即AlxGabxN(0S X S 1)之材料 皆可。 一超晶格緩衝層(20a)係形成於該成核層(11)之上,此一 超晶格緩衝層(2 0 a)為本創作之主要特徵,其係在A1N成核層 (11)生長元後,昇溫成長約1 OOnm bulk GaN之後,插入以多層 (Loops) AlGaN/GaN所構成之超晶格結構(SLs)(22),亦即該 超晶格緩衝層(20a)其一實施例包括有:一第一緩衝層(21)係 形成於該成核層(11)上;一多層AlGaN/GaN所形成之超晶袼 結構(22),係形成於該第一緩衝層(21)上;以及一第二緩衝層 (23),係形成於該超晶格結構(22)上。 前述超晶格結構包括可由5〜20層(Loops)之 AlGaN/GaN所構成,其中氮化鋁鎵(A1GaN)之厚度為 10〜3〇 A,而氮化鎵(GaN)之厚度為100〜200人為較佳。 -8-AOC-05-29-TW AOC-05-29-TWM298777 on the first buffer layer; a first buffer layer formed on the superlattice structure; a channel layer formed on the second buffer layer; A barrier layer is formed on the via layer; and a source, a drain, and a gate are formed on the barrier layer, respectively. [Embodiment] First, referring to the second figure, a schematic cross-sectional view of the present high-power transistor (200) is disclosed, which includes: a substrate (10) selected from the group consisting of tantalum carbide (SiC), It is composed of any of gallium nitride (GaN) and oxidized I (Al2〇3). An nucleation layer (11) is formed on the substrate (10), but is not limited thereto, and may be selected according to the material of the substrate (10). Preferably, the nucleation layer (11) is made of A1N (nitrogen). Aluminum, but not limited to this. That is, the material of AlxGabxN (0S X S 1) is acceptable. A superlattice buffer layer (20a) is formed on the nucleation layer (11). This superlattice buffer layer (20 a) is the main feature of the creation, which is in the A1N nucleation layer (11). After the growth element, after heating up to about 100 nm bulk GaN, a superlattice structure (SLs) (22) composed of multiple layers of (Loops) AlGaN/GaN is inserted, that is, the superlattice buffer layer (20a) The embodiment includes: a first buffer layer (21) is formed on the nucleation layer (11); a super-layer structure (22) formed by a multi-layer AlGaN/GaN is formed on the first buffer layer (21) upper; and a second buffer layer (23) formed on the superlattice structure (22). The superlattice structure comprises 5 to 20 layers of AlGaN/GaN, wherein the thickness of the aluminum gallium nitride (A1GaN) is 10~3〇A, and the thickness of the gallium nitride (GaN) is 100~ 200 people are better. -8-

AOC-05-29-TW AOC-05-29-TWM298777 此外,該第一緩衝層(21)及第二緩衝層(23)包括未摻雜 之氮化鎵(u-GaN)所構成。 接續上揭程序之後,一電晶體磊晶結構(80)係形成於該 AlGaN/GaN超晶格緩衝層(20a)上,此一元件層係為習知技 術(Prior Art),非本專利標的,因此其各層磊晶特性,諸如二維 電子氣等及其功用,容不詳述,其大體上包括一由氮化鎵 (GaN)所構成的通道層(30)係形成於該第二緩衝層(23)上;一 由n-AlGaN所構成之障壁層(40)係形成於該通道層(30)上, 以及於該障壁層(40)分別形成有電晶體元件所需之源極 (Surce)(50)、汲極(Drain)(70)及一閘極(Gate)(60)。其元件特 性容不贅述。 是以,本創作在成長完A1N成核層,以5〜20個Loops的 AlGaN/GaN SLs結構插入GaN緩衝層,其中AlGaN的A1成 份可由10%,9%,8%····逐漸降至1%,可以有效改善Strain Release,以及達到Dislocation Bending的效果,對使用A1N成 核層所成長的bulk GaN利用此SLs結構可以有效改善其品 質,並有助於提高其移動率(Mobility),進而使得HEMT元件 的蠢晶品質可以提昇。 附件--三係本創作列舉三組實驗資料提供參考, 其中: 附件一(表一):採用 A1N成核層分別成長有插入 AlGaN/GaN SLs 結構的 bulk GaN。 附件二(表二):在HEMT結構中導入AlGaN/GaN SLs 結構。 附件三(表三):在LED結構中導入AlGaN/GaN SLs -9-AOC-05-29-TW AOC-05-29-TWM298777 In addition, the first buffer layer (21) and the second buffer layer (23) comprise undoped gallium nitride (u-GaN). After the exposing process, a transistor epitaxial structure (80) is formed on the AlGaN/GaN superlattice buffer layer (20a). This component layer is a prior art (Prior Art), which is not the subject of this patent. Therefore, the epitaxial characteristics of each layer, such as two-dimensional electron gas and the like, are not detailed, and generally include a channel layer (30) composed of gallium nitride (GaN) formed in the second buffer. a layer (23); a barrier layer (40) composed of n-AlGaN is formed on the channel layer (30), and a source required for the transistor element is formed on the barrier layer (40) ( Surce) (50), Drain (70) and a Gate (60). Its component characteristics are not described here. Therefore, in the creation of the A1N nucleation layer, the GaN buffer layer is inserted into the AlGaN/GaN SLs structure of 5 to 20 Loops, and the A1 composition of AlGaN can be gradually decreased by 10%, 9%, 8%. Up to 1% can effectively improve the Strain Release and achieve the effect of Dislocation Bending. The use of this SLs structure for bulk GaN grown using the A1N nucleation layer can effectively improve its quality and help improve its mobility (Mobility). In turn, the stupid crystal quality of the HEMT device can be improved. Attachment--The three series of books provide reference for three sets of experimental data, among which: Annex I (Table 1): Bulk GaN with AlGaN/GaN SLs structure is grown by A1N nucleation layer. Annex II (Table 2): Introducing the AlGaN/GaN SLs structure into the HEMT structure. Annex III (Table 3): Introduction of AlGaN/GaN SLs -9- into the LED structure

AOC-05-29-TW M298777 結構.。 由附件之表一〜表三我們可以整理及獲致結論如后: 1、 從表一,可以發現在沒有改變任何成長條件之下, 同樣的bulk u-GaN在插入成長AlGaN/GaN SLs結構經由 Normarski發現,並無任何Cracking line產生;而透過Hall Measuement做進一步探討發現,在濃度相近(約〜6el6cm-3) 其mobility明顯獲得改善約1個order。 2、 從表二,在HEMT結構中導入bulku-GaN在插入成 長 AlGaN/GaN SLs 結構,從 Hall data 分析,其 mobility,Ns 值 > 都如預期般獲得改善。 3、 從表三,將此bulk u-GaN插入成長AlGaN/GaN SLs 結構導入LED,可以發現最明顯的改善是IR,及ESD。 4、 從上述三個論述,我們認為在使用AIN nucleation 時,在bulk u_GaN成長導入AlGaN/GaN SLs結構可以有效改 善其晶品質。 綜上所述,本創作所揭示之構造,為昔所無,且確能達到 預期之功效,並具可供產業利用性,完全符合新型專利要件, > 祈請貴審查委員核賜專利,以勵創新,無任德感。 惟,上述所揭露之圖式、說明,僅為本創作之較佳實施例, 大凡熟悉此項技藝人士,依本案精神範疇所作之修飾或等效 變化,仍應包括在本案申請專利範圍内。 -10 -AOC-05-29-TW M298777 Structure. From Tables 1 to 3 of the Annex, we can sort out and obtain conclusions as follows: 1. From Table 1, we can find that under the conditions of no growth, the same bulk u-GaN is inserted into the growing AlGaN/GaN SLs structure via Normarski. It was found that there was no cracking line produced; and further exploration by Hall Measuement found that the mobility was significantly improved by about 1 order at a similar concentration (about ~6el6cm-3). 2. From Table 2, the introduction of bulky-GaN into the HEMT structure is inserted into the elongated AlGaN/GaN SLs structure. From Hall data analysis, the mobility, Ns value > are improved as expected. 3. From Table 3, inserting the bulk u-GaN into the grown AlGaN/GaN SLs structure into the LED, the most obvious improvement is IR, and ESD. 4. From the above three discussions, we believe that when AIN nucleation is used, the growth of bulk U_GaN into the AlGaN/GaN SLs structure can effectively improve the crystal quality. In summary, the structure revealed by this creation is unprecedented, and it can achieve the expected effect, and is available for industrial utilization, fully in line with the new patent requirements, > pray for the review by the review committee, Inspire innovation, no sense of morality. However, the drawings and descriptions disclosed above are only preferred embodiments of the present invention. Modifications or equivalent changes made by those skilled in the art in accordance with the spirit of the present invention should still be included in the scope of the patent application. -10 -

AOC-05-29-TW M298777 【圖式簡單說明】 第一圖係習用一種高功率電晶體(HEMT)之結構剖面 示意圖。 第二圖係本創作之結構剖面示意圖。 【主要元件符號說明】 (10) 基板 (11) 成核層 (20a)超晶格緩衝層 • (21)第一緩衝層. (22) 超晶格結構 (23) 第二緩衝層 (30)通道層 (40)障壁層 (50)源極 (60)閘極 (70)沒極 (8 0)電晶體蠢晶結構 (200)高功率電晶體 -11 -AOC-05-29-TW M298777 [Simple description of the diagram] The first figure is a schematic diagram of the structure of a high-power transistor (HEMT). The second picture is a schematic cross-sectional view of the structure of the present creation. [Description of main component symbols] (10) Substrate (11) Nucleation layer (20a) Superlattice buffer layer • (21) First buffer layer. (22) Superlattice structure (23) Second buffer layer (30) Channel layer (40) barrier layer (50) source (60) gate (70) immersed (80) transistor crystal structure (200) high power transistor-11 -

Claims (1)

M298777 AOC-05-29-TW 九、申請專利範圍: 1 種多層超晶格高功率電晶體,包含: 一基板; —多層氮化鋁鎵(AlGaN)/氮化鎵(GaN)所構成之超晶 格緩衝層,形成於該基板上;以及 - 電曰曰體蠢晶結構,形成於該AlGaN/GaN超晶格緩衝 層上。 φ 2 ·如申請專利範圍第1項所述之多層超晶格高功率 電晶體,其中,該基板係選自包括碳化矽(SiC)、氮化鎵(GaN) 及氧化紹(八丨2〇3)其中任一材質所構成。 3 ·如申請專利範圍第1項所述之多層超晶格高功率 電晶體,其中,該超晶格緩衝層包括有: 一第一緩衝層,係形成於該基板上, 一多層AlGaN/GaN所形成之超晶格結構,係形成於該 第一緩衝層上;以及 _ 一第一緩衝層,係形成於該超晶格結構之上。 4 ·如申請專利範圍第3項所述之多層超晶格高功率 電晶體,其中,該超晶格結構包括由5〜20層(Loops)之 _ AlGaN/GaN 所構成。 5 ·如申請專利範圍第4項所述之多層超晶格高功率 電晶體,其中,該氮化鋁鎵(AlGaN)之厚度為i 〇〜3〇人,而該氮 化鎵(GaN)之厚度為ι〇0〜2〇〇 A。 -12- M298777 AOC-05-29-TW 如申睛專利範圍第3項所述之多層超晶格高功率 〒,该第一及第二緩衝層包括由未摻雜之氮化鎵 (u-GaN)所構成。 Γ7 曰 如申請專利範圍第1項所述之多層超晶格高功率 電曰曰體,其中,該超晶格緩衝層與該基板間,更包括設有一成 核層。 “ 8如申凊專利範圍第7項所述之多層超晶格高功率 電晶體,其中,該成核層由氮化鋁鎵AlxGa^NCOs X £ 1)所 構成。 9 ·如申請專利範圍第1項所述之多層超晶格高功率 電晶體,其中,該電晶體磊晶結構包括有: 一通道層,係形成於該超晶格緩衝層上; 一障壁層,係形成於該通道層上;以及 ;x卩早i層分別形成有··源極、沒極及閘極者。 1 0 ·如申請專利範圍第9項所述之多層超晶格高功 率電晶體,其中,該通道層包括由氮化鎵(GaN)所構成。 1 1 ·如申請專利範圍第9項所述之多層超晶格高功 率電晶體,其中,該障壁層包括由未摻雜氮化鋁鎵(u_A1GaN) 及 u_AlGaN/n-AlGaN/u-AlGaN 其中任一所構成。 -13- AOC-05-29-TW M298777 1 2 · —種多層超晶格高功率電晶體,包含: 一基板; 一成核層,係形成於該基板上; 一第一緩衝層,係形成於該成核層上; 一多層氮化鋁鎵(AlGaN)/氮化鎵(GaN)所形成之超晶 格結構,係形成於該第一緩衝層上; 一第二緩衝層,係形成於該超晶格結構上; 一通道層,係形成於該第二緩衝層上; 一障壁層,係形成於該通層上;以及 一源極、汲極、閘極係分別形成於該障壁層上。M298777 AOC-05-29-TW IX. Patent application scope: 1 multilayer superlattice high power transistor, including: a substrate; - multilayer aluminum nitride gallium (AlGaN) / gallium nitride (GaN) a lattice buffer layer formed on the substrate; and an electric germanium silica structure formed on the AlGaN/GaN superlattice buffer layer. The multilayer superlattice high power transistor according to claim 1, wherein the substrate is selected from the group consisting of tantalum carbide (SiC), gallium nitride (GaN), and oxidized sho 3) Any of these materials. 3. The multilayer superlattice high power transistor of claim 1, wherein the superlattice buffer layer comprises: a first buffer layer formed on the substrate, a multilayer of AlGaN/ A superlattice structure formed by GaN is formed on the first buffer layer; and a first buffer layer is formed on the superlattice structure. 4. The multilayer superlattice high power transistor of claim 3, wherein the superlattice structure comprises 5 to 20 layers of _AlGaN/GaN. 5. The multilayer superlattice high power transistor according to claim 4, wherein the thickness of the aluminum gallium nitride (AlGaN) is i 〇 〇 3 , , , , , , , , , , , , , , The thickness is ι〇0~2〇〇A. -12- M298777 AOC-05-29-TW The multi-layer superlattice high power enthalpy of claim 3, wherein the first and second buffer layers comprise undoped gallium nitride (u- GaN).多层7 曰 The multi-layer superlattice high-power electric enthalpy according to claim 1, wherein the superlattice buffer layer and the substrate further comprise a nucleation layer. [8] The multilayer superlattice high power transistor according to claim 7, wherein the nucleation layer is composed of aluminum gallium nitride AlxGa^NCOs X £ 1). The multi-layer superlattice high power transistor of claim 1, wherein the transistor epitaxial structure comprises: a channel layer formed on the superlattice buffer layer; a barrier layer formed on the channel layer And a plurality of super-lattice high-power transistors according to claim 9 of the invention, wherein the channel is formed; The layer includes a multi-layer superlattice high power transistor according to claim 9, wherein the barrier layer comprises undoped aluminum gallium nitride (u_A1GaN). And - u-AlGaN/n-AlGaN/u-AlGaN. -13- AOC-05-29-TW M298777 1 2 · A multilayer superlattice high power transistor comprising: a substrate; a nucleation a layer formed on the substrate; a first buffer layer formed on the nucleation layer; a multilayer aluminum nitride a superlattice structure formed by gallium (AlGaN)/gallium nitride (GaN) is formed on the first buffer layer; a second buffer layer is formed on the superlattice structure; a channel layer Formed on the second buffer layer; a barrier layer formed on the via layer; and a source, drain, and gate system respectively formed on the barrier layer. -14--14-
TW95203065U 2006-02-23 2006-02-23 Multi-layer superlattice high-power transistor TWM298777U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505462B (en) * 2010-07-06 2015-10-21 Univ Hong Kong Science & Techn Normally-off iii-nitride metal-2deg tunnel junction field-effect transistors
US9299824B2 (en) 2013-03-14 2016-03-29 Epistar Corporation Field effect transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505462B (en) * 2010-07-06 2015-10-21 Univ Hong Kong Science & Techn Normally-off iii-nitride metal-2deg tunnel junction field-effect transistors
US9299824B2 (en) 2013-03-14 2016-03-29 Epistar Corporation Field effect transistor
US9647102B2 (en) 2013-03-14 2017-05-09 Epistar Corporation Field effect transistor

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