TWM294086U - Package structure of improving the temperature cycle life of solder ball - Google Patents

Package structure of improving the temperature cycle life of solder ball Download PDF

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Publication number
TWM294086U
TWM294086U TW094220748U TW94220748U TWM294086U TW M294086 U TWM294086 U TW M294086U TW 094220748 U TW094220748 U TW 094220748U TW 94220748 U TW94220748 U TW 94220748U TW M294086 U TWM294086 U TW M294086U
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Taiwan
Prior art keywords
wafer
substrate
package structure
modulus
young
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TW094220748U
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English (en)
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Wen-Jeng Fan
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Powertech Technology Inc
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Priority to TW094220748U priority Critical patent/TWM294086U/zh
Publication of TWM294086U publication Critical patent/TWM294086U/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

M294086 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種封裝結構，特別是一種考量母板層級之溫度循 環測試的封裝結構設計。 【先前技術】 隨著半導體產業的高度發展，電子產品在ic元件的設計上朝向 多腳數與多功能化的需求發展，而在元件外觀上亦朝著輕、薄、短、 φ 小的趨勢發展。因此，在封裝製程上亦面臨許多挑戰，諸如基板的設 計曰趨複雜、封裝材料的選用、薄型封裝翹曲變形'散熱性與結構強 度等問題，都是目前封裝產業所遭遇亟欲解決的難題。 第一圖所示為一習知FBGA-BOC(Board-On-Chip)的正面透視 示意圖。以單一晶片封裝體為例，基板100上設置一溝槽110,且基 板100上具有一黏著劑塗佈範圍112,晶片則設置於黏著劑塗佈範圍 112上，錫球114則分布於黏著劑塗佈範圍112内，亦有可能超出黏 著劑範圍外。參照第二圖，一般而言，如此的封裝結構12〇設置完晶 片與塑封材料後，會將該封裝結構12〇的錫球114銲接至母板 _ 130(b〇ard)上，進行高溫與低溫轉換的溫度循環測試（b〇ard T/c testing)，測試中封f結構120各材料及母板13〇因為材料的熱膨脹 係數不匹配之問題，谷易產生熱應力。錫球114因本身材料最為脆弱， 因此錫球H4破裂是最常遇到的破壞模式。此時訊號傳輸的電阻值增 加，可能導致開路(—η)，甚至整個元件纽。因此，如何確保锡球 於測試中的可靠度疋很重要的課題之一。 【新型内容】 為了減>、封衣、構在母板層級之溫度循環測試時應力不匹配的 5 M294086 金1U暴板表面，可吸收不匹配的熱應力。 為了減少封裝結構在母板層級之溫度循環測 (crack)的問題產生’提供一種封 ' 分布於繼射咖鐵❹姻材料 為達到上述目的，本創作之二 加揚氏模數相對較小之晶片黏著材料佔 ^曰片封裝結構’增 面亦塗佈上晶片黏著材料。 未破晶片覆蓋的基板表 【實施方式】 12中間隔地分布複數個晶片14。於 ”中每—晶片陣列 個溝槽16對應每-晶片陣列12，且每:^。基板1()具有複數 14以提供晶片14電性連接時之用。苴-欠’二對應至少任-晶片 晶片Η與基板1G之間，亦可分布於每黏著㈣18介於 之間。換言之，晶片黏著材料18之一部乂 : 12之任兩晶片14 位於晶片Μ之下方，晶片黏著材料1δΡ:另'與晶114重疊’即 上之晶片陣列12可以具有相同或相異數理解，基板10 10相反側的兩個表面。其次，晶片陣列、日日4 ’或疋位於基板 是相同的晶片，亦不排除功能或型態不，的晶片14可以 12中。 的日日片14置於一晶片陣列 一般封裝製程時，係以一晶片陣列丄 塗佈（包含網印、點膠或上乾膜的方式）晶=裝製程，主要包$ 範圍、黏晶（die attach)、打線、包您耆料18於晶片陣歹1 第四圖所示為根據本_之-實施例之晶、植球然後切割。 T衣結構的側面示意圖。晶片封| M294086 黏著材料18位於基板10之第—表面101上，盆中 =片#:者材料18分布於第—表面m上並介 4之 ^，㈣20則包覆晶片14與第—表請，其中被晶 出的曰:片黏者材料18介於塑封材料2〇與第—表面ι〇ι 面3位於第—表面1〇1之相反側，其上分布若干導電墊^ 又防知漆24覆盍，錫球26則位於導電墊以上 FB〇A(fine pitch BGA)„ FBGA.B〇C(B〇ard
上設有溝槽，其位於晶片14之範圍内，藉以提供通道容置 10«1^22〇〇^^28, 14 本創作之精神可應用於晶片線路面朝上或晶片線路面朝下的球栅 ’J冓衣（ie Face Up or Dle Face Down，BGA)，例如應用於晶片線路面
朝上的封裝時，晶片黏著材料18塗佈（包含網印、點膠或上乾臈的方式）範 圍不僅在於黏晶處，亦包含第—表面1Q1之暴露出的部分，如第五圖所示，第 一表面101上尚包含防銲漆24與被暴露出的導電墊22，故於網印晶片 黏著材料18於第一表面1〇1上時亦暴露出導電墊22，再以一道或多道的 打線步驟將導電連接線28電性連接晶片14之導電連接墊3〇 表面101上之導電墊22。就一般材料而言，當應用於溫度循環測試中時，揚 氏模數，例如小於1000 MPa之晶片黏著材料18小於封裝結構中之其他材料 之楊氏模數，例如基板10(硬質材料約200000到300000 MPa，軟質基板約 小於 15000 MPa)、晶片 14(1〇〇〇〇〇〜150000 MPa)或塑封材二 20(15000〜25000 MPa)，因此可吸收不同材料因熱漲冷縮不匹配(thermai mismatch)所造成的熱應力。如此一來，可降低錫球26所承受的熱廡力， 減少錫球26的變形，增加封裝結構於母板層級溫度循環測試中的壽命， 進而提升封裝產品於母板層級的可靠度。 ^ P 根據上述，一種晶片的封裝結構，晶片位於基板之一第一表面。曰片 黏著材料分布於第一表面上並介於第一表面與晶片之間，塑封材料包覆 晶片與第一表面，其中部分晶片黏著材料介於塑封材料與第一表面之間。廣用 於晶片陣列區塊(block of die array)時，複數個晶片陣列間隔地分布於 M294086 基板上，每一晶月陣列中間隔地分布複 複數個晶片與基板之間，且八 一固曰日片。晶片黏著材料介於 以上所述之實施例僅：為二:曰:片陣列之任兩晶片之間。 的在使熟習此項技蓺之人士4本創作之技術思想及特點，其目 能《之限定本創作之之内容並據以實施，當不 均等變化祕飾，仍應涵蓋 ^__示之精神所作之 十A丨F <寻利範圍内。 【圖式簡單說明】 第-圖為習知之—腿實施例之晶片_結構的正 苐一圖所不為一般母板層級溫度循環測試的樣品側面示意妹構。μ 示意圖。 她據本創作之—實關之線路面朝下晶片封裝結構的側面 面示^圖所示為根據本創作之另一實施例之線路面朝上晶片封裝結構的側 【主要7〇件符號說明】 5 載板 • !〇基板 12 晶片陣列 !4 晶片 溝槽 18晶片黏著材料 18a’b晶片黏著材料的一部分 2〇 塑封材料 101第一表面 1〇2弟二表面 22 導電墊 ⑧ 8 M294086 24 防銲漆 26 錫球 28 導電連接線 30 導電連接墊 100 基板 110 溝槽 112 黏著劑塗佈範圍 114 錫球 120 封裝結構 φ 130 母板

Claims (1)

  1. M294086 九、申請專利範圍： 1. 一種晶片的封裝結構，包含： 一基板具有一第一表面與一第二表面分別位於該基板之相反側； 一晶片位於該第一表面上； 一晶片黏著材料分布於該第一表面上並介於該第一表面與該晶片之 間；及 一塑封材料包覆該晶片與該第一表面，其中部分該晶片黏著材料介於該塑 封材料與該第一表面之間。 φ 2.如申請專利範圍第1項所述之晶片的封裝結構，其中該基板更包含複 數個導電墊分布於該第二表面上。 3. 如申請專利範圍第2項所述之晶片的封裝結構，其中該基板更具有一 溝槽（slot)從該第一表面貫穿至該第二表面。 4. 如申請專利範圍第3項所述之晶片的封裝結構，更包含複數個導電連 接線(bonding wire)穿過該溝槽並電性連接該晶片至部分該複數個導 電墊。 5. 如申請專利範圍第4項所述之晶片的封裝結構，其中該塑封材料更 包含包覆該複數個導電連接結構。 6. 如申請專利範圍第2項所述之晶片的封裝結構，更包含複數個導電 連接結構對應該複數個導電墊。 7.如申請專利範圍第1項所述之晶片的封裝結構，其中該晶片黏著材 料的楊氏模數小於該晶片的楊氏模數。 M294086 - 8.如申請專利範圍第1項所述之晶片的封裝結構，其中該晶片黏著材 .料的楊氏模數小於該基板的楊氏模數。 9. 如申請專利範圍第1項所述之晶片的封裝結構，其中該晶片黏著材 料的揚氏模數小於該塑封材料的楊氏模數。 10. 如申請專利範圍第1項所述之晶片的封裝結構，其中該第一表面大 於該晶片的尺寸。 φ 11.如申請專利範圍第1項所述之晶片的封裝結構，其中該晶片的一線 路面接觸該晶片黏著材料或該塑封材料。 12. —種晶片陣列區塊(block of die array)，包含： 複數個晶片陣列間隔地分布於一基板上，其中每一該晶片陣列中間 隔地分布複數個晶片；及 一晶片黏者材料介於該複數個晶片與該基板之間’且分布於每一該 晶片陣列之任兩該晶片之間。 φ 13.如申請專利範圍第12項所述之晶片陣列區塊，其中該基板包含複數個溝 槽對應每一該晶片陣列，且每一該溝槽對應至少任一該晶片。 14.如申請專利範圍第13項所述之晶片陣列區塊，其中任一該晶片包含複數 個金屬材質導線穿過該對應溝槽電性連接至該基板。 15·如申請專利範圍第12項所述之晶片陣列區塊，其中該晶片黏著材料的楊 氏模數小於該基板的楊氏模數。 16·如申請專利範圍第12項所述之晶片陣列區塊，其中該晶片黏著材料的楊 氏模數小於任一該晶片的楊氏模數。 π ⑧ M294086 球栅陣列 17·如申請專利範圍第12項所述之晶片陣列區塊，其中該基板為一 封裝載板。 18· 請專利範圍第12項所述之晶片陣列區塊，其中該球柵陣列封带 更包含複數個導電塾位於該複數個晶片的相反側。 、衣、板 塑封材料於該晶片 封材料接觸任兩該 申明專利範圍第12項所述之晶片陣列區塊，更包含. 陣列上且包覆該複數個晶片。
    片H專利範圍第19項所述之晶牌列區塊，其中該' 曰曰片之間的該晶片黏著材料。
    12
TW094220748U 2005-11-30 2005-11-30 Package structure of improving the temperature cycle life of solder ball TWM294086U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409924B (zh) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng 半導體封裝體及其製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409924B (zh) * 2007-09-12 2013-09-21 Advanced Semiconductor Eng 半導體封裝體及其製造方法

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