TWI898705B - 包含超晶格吸除層之記憶體元件及相關方法 - Google Patents

包含超晶格吸除層之記憶體元件及相關方法

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TWI898705B
TWI898705B TW113124854A TW113124854A TWI898705B TW I898705 B TWI898705 B TW I898705B TW 113124854 A TW113124854 A TW 113124854A TW 113124854 A TW113124854 A TW 113124854A TW I898705 B TWI898705 B TW I898705B
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竹內秀樹
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美商安托梅拉公司
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Abstract

一種半導體元件可包括一半導體底材及該半導體底材上之一記憶體元件，該記憶體元件包括鄰接該半導體底材之一金屬誘發結晶(MIC)通道，及與該MIC通道相關聯之一閘極。該半導體底材可更包括介於該半導體底材及該MIC通道間之一超晶格吸除層。該超晶格吸除層可包括複數個堆疊之層群組，其中各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。該超晶格吸除層可包括從該MIC通道吸除的金屬微粒。

Description

包含超晶格吸除層之記憶體元件及相關方法
本揭示一般而言涉及半導體元件，更具體而言，涉及半導體記憶體元件及相關方法。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與/或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其N型通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部份(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,934號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交替之SiO2/Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上出版的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing)pp.391-402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice,SAS)。此矽/氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電致發光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species)及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的 一種SAS結構包含1.1nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol.89,No.7(2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
授予Wang等人之美國專利第7,105,895號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層/阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公開之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙(aperiodic photonic band-gap,APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積於該沉積層上。作為替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有上述方法存在，但為了實現半導體元件效能的改進，進一步強化先進半導體材料及處理技術的使用，是吾人所期望的。
一種半導體元件，其可包括一半導體底材及該半導體底材上之一記憶體元件，該記憶體元件包括鄰接該半導體底材之一金屬誘發結晶(metal induced crystallization,MIC)通道及與該MIC通道相關聯之一閘極。該半導體元件可更包括介於該半導體底材及該MIC通道間之一超晶格吸除層。該超晶格吸除層可包括複數個堆疊之層群組，其中各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。該超晶格吸除層可更包括從該MIC通道吸除的金屬微粒。
在一示例性實施例中，該記憶體元件可為一NAND記憶體元件。作為示例，該MIC通道可為從該半導體底材往上縱向延伸之一垂直MIC通道。此外，該閘極可包括交替的閘極絕緣層及閘電極層之一堆疊，且每個閘電極層可包括一個鎢閘電極。
在一些實施例中，該半導體元件可更包括該半導體底材中一摻雜擴散層，且該超晶格吸除層可位於該摻雜擴散層內部。在一示例性實施方式中，該半導體元件可更包括介於該閘極與該MIC通道間之一氧化物-氮化物-氧化物襯墊。作為示例，被吸除的金屬微粒可包括鎳微粒。又作為示例，該些基底半導體單層可包括矽，且該些非半導體單層可包括氧。
一種用於製造一半導體元件之方法可包括在一半導體底材上形成一超晶格吸除層。該超晶格吸除層可包括複數個堆疊之層群組，其中各層群組 包括界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層。該方法亦可包括在該超晶格吸除層上方形成一記憶體元件，使其包括鄰接該半導體底材之一金屬誘發結晶(MIC)通道，以及與該MIC通道相關聯之一閘極。該超晶格吸除層可更包括從該MIC通道吸除的金屬微粒。
在一示例性實施例中，形成該記憶體元件包括形成一NAND記憶體元件。作為示例，該MIC通道可為從該半導體底材往上縱向延伸之一垂直MIC通道。此外，該閘極可包括交替的閘極絕緣層及閘電極層之一堆疊，且每個閘電極層可包括一個鎢閘電極。
在一些實施例中，該方法可更包括在該半導體底材中形成一摻雜擴散層，且形成該超晶格吸除層可包括將該超晶格吸除層形成於該摻雜擴散層內部。在一示例性實施方式中，該方法可更包括在該閘極與該MIC通道之間形成一氧化物-氮化物-氧化物襯墊。作為示例，被吸除的金屬微粒可包括鎳微粒。又作為示例，該些基底半導體單層可包括矽，且該些非半導體單層可包括氧。
25,25’:超晶格/超晶格吸除層/MST層
30:半導體元件
31:底材
32:記憶體元件
33:MIC通道
34:閘極
35:植入物層
36:氧化物層
37:氮化物層
38:溝槽
45a~45n,45a’~45n-1’,45n’:層群組
46,46’:基底半導體單層
46a~46n,46a’~46n-1’,46n’:基底半導體部份
50,50’:能帶修改層/非半導體單層
52,52’:頂蓋層
60:閘電極
61:介電薄膜
62:非晶矽通道
63:金屬層
65:圖表
圖1為依照一示例性實施例之半導體元件用超晶格之放大概要剖視圖。
圖2為圖1所示超晶格之一部份之透視示意原子圖。
圖3為依照另一示例性實施例之超晶格放大概要剖視圖。
圖4繪示依照一示例性實施例之包括超晶格吸除層之記憶體元件的剖面圖。
圖5A至圖5J繪示用於製造圖4記憶體元件之一示例性方法的一系列剖面圖。
圖6之圖表繪示具MST吸除層之圖4記憶體元件中鎳的SIMS曲線，以及不具有MST吸除層之類似記憶體元件中鎳的SIMS曲線。
茲參考說明書所附圖式詳細說明示例性實施例，圖式中所示者為示例性實施例。不過，實施例可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之特定示例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(‘)則用以標示不同實施方式中之類似元件。
一般而言，本揭示內容係有關於內部有一增強型半導體超晶格(enhanced semiconductor superlattice)以提供更佳效能之半導體元件。在本揭示內容中，增強型半導體超晶格亦可稱為MST層，或「MST技術」。
詳言之，MST技術涉及進階的半導體材料，例如下文將進一步說明之超晶格25。在先前文獻中，申請人推論本說明書所述之超晶格結構可減少電荷載子之有效質量，從而提高電荷載子遷移率。舉例而言，請參閱美國專利第6,897,472號，其全部內容在此併入成為本說明書之一部。
申請人的進一步開發證實，MST層的存在可有利地改進半導體材料中自由載子之遷移率，例如在矽與絕緣體(如SiO2或HfO2)之間的交界面。申請人之理論認為(但申請人並不欲受此理論所束縛)，這可能因各種機制而發生。其中一種機制為降低界面附近帶電雜質的濃度，減少這些雜質的擴散及/或捕捉雜 質使其無法到達界面附近。帶電雜質會導致庫侖散射(Coulomb scattering)，進而降低遷移率。另一機制為改進界面品質。例如，從MST薄膜釋放的氧可向Si-SiO2界面提供氧，從而減少次化學計量(sub-stoichiometric)SiOx的存在。或者，MST層對間隙子(interstitials)的捕捉可降低Si-SiO2界面附近的間隙矽濃度，從而降低形成次化學計量SiOx之趨勢。已知在Si-SiO2界面處之次化學計量SiOx相對於化學計量SiO2表現出較差之絕緣特性。減少界面處之次化學計量SiOx的量，可更有效侷限矽當中的自由載子(電子或電洞)，從而在平行於界面之電場作用下提高這些載子的遷移率，這是場效應電晶體(field-effect-transistor，「FET」)結構之標準作法。由於界面之直接影響而產生的散射稱為「表面粗糙度散射(surface-roughness scattering)」，其可經由在回火之後或在熱氧化期間因鄰近的MST層而有利地減少。
這些MST結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及/或鐵電特性，下文將進一步討論。
參考圖1及圖2，所述材料或結構是超晶格25的形式，其結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。超晶格25包含複數個堆疊排列之層群組45a-45n，如圖1之概要剖視圖所示。
如圖所示，超晶格25之每一層群組45a-45n包含複數個堆疊之基底半導體單層46(其界定出各別之基底半導體部份46a-46n)以及其上之非半導體單層50。為清楚呈現起見，非半導體單層50於圖1中以雜點表示。
如圖所示，非半導體單層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格 內」一詞，係指來自相對之基底半導體部份46a-46n之至少一些半導體原子，透過該些相對基底半導體部份間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部份46a-46n上面之非半導體材料之量而成為可能，這樣一來，可用之半導體鍵結位點(bonding sites)便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位點。
在其他實施方式中，使用超過一個此種非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成為塊狀，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成為塊狀或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，非半導體單層50與相鄰之基底半導體部份46a-46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。非半導體單層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為超晶格25垂直上下方多個層之間之摻雜物及/或材料擴散之阻擋。因此，這些特性可有利地允許超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利 地減少不需要之散射效應，並改進元件遷移率(device mobility)，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為這些實施方式而實現之能帶工程，超晶格25可進一步具有實質上直接的能帶間隙，此對諸如光電元件等尤其有利。
如圖所示，超晶格25亦可在一上部層群組45n上方包含一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。頂蓋層52可包含基底半導體的2至100個之間的單層，較佳者為10至50個之間的單層。
每一基底半導體部份46a-46n可包含由IV族半導體、III-V族半導體及II-VI族半導體所組成之群組中選定之一基底半導體。當然，IV族半導體亦包含IV-IV族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一非半導體單層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之非半導體單層50，亦應包含層中所有可能位置未完全被佔據之單層(亦即非完全或低於100% 之涵蓋範圍)。舉例來說，參照圖2之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4/1重複結構。氧原子之可能位置僅有一半被佔據。
在其他實施方式及/或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有此處實施方式之超晶格25之半導體元件，可很容易地加以採用並實施，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3/1/5/1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一非半導體單層50’可包含一單一單層。就包含矽/氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目單層之厚度。
茲參考圖4描述一半導體元件30，其納入了上述MST結構作為用於金屬誘發結晶(MIC)處理之吸除層。作為背景說明，已知有不同方法可用於3D NAND記憶體元件及製作。舉例而言，在Y.Aiba等人的「Demonstration of recovery annealing on 7-bits per cell 3D flash memory at cryogenic operation for bit cost scalability and sustainability」,T3-3,VLSI Symposium 2023中報告了磊晶矽通道之3D NAND元件效能明顯優於常規多晶矽通道，其使用MIC技術將非晶矽(a-Si)轉化為結晶矽。另一文獻(Z.Jin等人，「Nickel induced crystallization of amorphous silicon thin films」，第194頁，J.Appl.Phys.1998)報告，沉積在1μm非晶矽上之5-10nm鎳層，可在後續500℃溫度下歷時1小時的回火中，將非晶矽層轉化為結晶矽，而鎳則擴散穿過該非晶矽層。
雖然此類技術提供了增強的通道效能，但因為基於MIC之3D-NAND磊晶矽通道仰賴鎳原子的快速擴散，因此擴散的鎳需要被控制或移除，使其不會擴散到矽底材上的其他電晶體區域。否則將可能導致不樂見的結晶缺陷，造成良率大幅降低。
如圖所示，半導體元件30包含一底材31(例如一半導體底材，像是矽底材)及其上之一記憶體元件32，記憶體元件包括鄰接半導體底材之一MIC通道33，及與MIC通道相關聯之一閘極34。在本示例中，記憶體元件32為3D垂直NAND記憶體元件，但在其他實施例中可使用不同類型的記憶體元件(例如，3D水平通道NAND、3D NOR記憶體元件等)。如圖所示，半導體元件30進一步包括介於底材31及MIC通道33間之一超晶格吸除層25，諸如上述該些MST層。超晶格吸除層25可有利地將MIC製程期間因金屬(例如鎳)快速擴散所產生的金屬微粒(在圖4示例中為鎳)從MIC通道中吸除。
另外參考圖5A至圖5J，現在說明一種用於製造圖4半導體元件30之示例性方法。如上文進一步討論的，該方法始於在底材31上形成一MST層25(圖5A)。作為示例，MST層25之厚度可在例如5-500nm之範圍內。然後，透過植入摻雜劑而形成植入物層35。在本示例中為N+植入物層35(例如，P 10keV 3x1015)，其伴隨一快速熱回火(RTA)(例如，在1000℃下持續5秒)。
在植入物層35形成之後，形成交替的氧化物及氮化物薄膜36、37之堆疊(圖5C)。在所示示例中，堆疊中存在四個氧化物層36及三個氮化物層37，但在不同實施例中可使用不同數目的層。接著，在薄膜堆疊中蝕刻出一溝槽38(圖5D)，接著蝕刻出該些氮化物層之部分凹槽(圖5E)。
然後，可在氮化物附近進行金屬閘電極60(例如鎢)的沉積並進行回蝕，如圖5F所示。然後，可在溝槽38中形成一介電薄膜61並進行回蝕(圖5G)。作為示例，介電薄膜61可為一氧化物-氮化物-氧化物(ONO)薄膜，但在不同實施例中可使用其他適合之介電質。接著，可在溝槽38中於薄膜61上形成非晶矽通道62，如圖5H所示。
MIC製程始於在該堆疊上形成金屬(此處為鎳)層63(圖5I)。作為示例，金屬層63之厚度可在5-10nm之範圍內，但在不同實施例中可使用不同厚度。然後，可進行MIC回火，造成鎳擴散穿過通道62之非晶矽而使其結晶(圖5J)。如圖4所示，來自MIC回火的鎳，原本會擴散到底材31(或其他區域)中，但因為本發明現在會被設置於擴散層35內部的MST層25吸除或捕獲。接着可移除表面鎳/鎳矽層63，並視情況執行進一步的元件處理(例如，接點形成等)，熟習本發明所屬技術領域者當可理解。
上述內容的有效性已透過圖6之圖表65繪示之SIMS曲線確認。在550℃下經由LPCVD沉積約0.9um之非晶矽後，以蒸發方式沉積10nm之鎳薄膜。在後續模擬MIC回火的500℃歷時1小時回火後，測量鎳的深度曲線。從圖表65可明顯看出，相較於不具有MST吸除層的矽底材，具有MST薄膜的矽底材包含從非晶矽/結晶矽界面處之頂部表面擴散的鎳。
本發明方法之另一技術優勢為，透過在起始晶圓上實施MST層25(例如，作為橫跨晶圓表面之空白沉積)，其他區域之周邊電路將獲得MST的益處。這些益處包括，舉例而言，Vt變異性改進、遷移率改進、閘極漏電減少及閘極氧化物可靠性改進。關於MST薄膜吸除能力的進一步細節提供於Takeuchi的美國專利第10,410,880號，該專利亦讓與本申請人，且其全部內容在此併入成為本說明書之一部。
熟習本發明所屬技術領域者將受益於本說明書揭示之內容及所附圖式，從而構思出各種修改例及其他實施方式。因此，應了解的是，本揭示之內容不限於本說明書所述特定實施方式，也包含相關的修改例及實施方式在內。
25: 超晶格吸除層 30: 半導體元件 31: 矽底材 32: 記憶體元件 33: MIC通道 34: 閘極 35: 植入物層 36: 氧化物層 61: 介電薄膜

Claims (20)

  1. 一種半導體元件，其包括： 一半導體底材； 該半導體底材上之一記憶體元件，其包括 鄰接該半導體底材之一金屬誘發結晶(MIC)通道，及 與該MIC通道相關聯之一閘極；以及 介於該半導體底材及該MIC通道間之一超晶格吸除層，該超晶格吸除層包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層； 該超晶格吸除層更包括從該MIC通道吸除的金屬微粒。
  2. 如請求項1之半導體元件，其中該記憶體元件包括一NAND記憶體元件。
  3. 如請求項1之半導體元件，其中該MIC通道包括從該半導體底材往上縱向延伸之一垂直MIC通道。
  4. 如請求項3之半導體元件，其中該閘極包括交替的閘極絕緣層及閘電極層之一堆疊。
  5. 如請求項4之半導體元件，其中每個閘電極層包括一個鎢閘電極。
  6. 如請求項1之半導體元件，其更包括該半導體底材中一摻雜擴散層，且其中該超晶格吸除層位於該摻雜擴散層內部。
  7. 如請求項1之半導體元件，其更包括介於該閘極與該MIC通道間之一氧化物－氮化物－氧化物襯墊。
  8. 如請求項1之半導體元件，其中被吸除的金屬微粒包括鎳微粒。
  9. 如請求項1之半導體元件，其中該些基底半導體單層包括矽。
  10. 如請求項1之半導體元件，其中該些非半導體單層包括氧。
  11. 一種用於製造一半導體元件元件之方法，該方法包括： 在一半導體底材上形成一超晶格吸除層，使該超晶格吸除層包括複數個堆疊之層群組，各層群組包含界定出一基底半導體部分之複數個堆疊之基底半導體單層，以及被拘束在相鄰的基底半導體部分之一晶格內之至少一非半導體單層；及 在該超晶格吸除層上方形成一記憶體元件，使其包括鄰接該半導體底材之一金屬誘發結晶(MIC)通道，以及與該MIC通道相關聯之一閘極； 該超晶格吸除層更包括從該MIC通道吸除的金屬微粒。
  12. 如請求項11之方法，其中形成該記憶體元件包括形成一NAND記憶體元件。
  13. 如請求項11之方法，其中該MIC通道包括從該半導體底材往上縱向延伸之一垂直MIC通道。
  14. 如請求項13之方法，其中該閘極包括交替的閘極絕緣層及閘電極層之一堆疊。
  15. 如請求項14之方法，其中每個閘電極層包括一個鎢閘電極。
  16. 如請求項11之方法，其更包括在該半導體底材中形成一摻雜擴散層，且其中形成該超晶格吸除層包括將該超晶格吸除層形成於該摻雜擴散層內部。
  17. 如請求項11之方法，其更包括在該閘極與該MIC通道之間形成一氧化物－氮化物－氧化物襯墊。
  18. 如請求項11之方法，其中被吸除的金屬微粒包括鎳微粒。
  19. 如請求項11之方法，其中該些基底半導體單層包括矽。
  20. 如請求項11之方法，其中該些非半導體單層包括氧。
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