TWI847040B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI847040B
TWI847040B TW110120937A TW110120937A TWI847040B TW I847040 B TWI847040 B TW I847040B TW 110120937 A TW110120937 A TW 110120937A TW 110120937 A TW110120937 A TW 110120937A TW I847040 B TWI847040 B TW I847040B
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metal layer
semiconductor device
metal
layer
film
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TW110120937A
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TW202233039A (zh
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澤登昭仁
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日商鎧俠股份有限公司
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

半導體裝置，係具備有基板、和被設置於基板處之半導體晶片、和被覆半導體晶片之樹脂、以及被設置於樹脂處之金屬膜。金屬膜，係具備有第1金屬層、和被設置於第1金屬層處之第2金屬層、以及被設置於第2金屬層處之第3金屬層。第1金屬層與第2金屬層，係包含相同之材料。第2金屬層之粒徑係較第1金屬層之粒徑而更小、或/及第2金屬層之電阻率係較第1金屬層之電阻率而更大。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施形態，係有關於半導體裝置及半導體裝置之製造方法。 [關連申請案之引用] 本申請，係以於2021年2月3日所申請之日本特願第2021-015672號的優先權之利益作為基礎，並且謀求其之利益，而將其之內容全體藉由引用而包含於本發明中。
為了對於從半導體裝置所產生的EMI(電磁干擾，Electro Magnetic Interference)作抑制，係會有在半導體裝置之表面上作為電磁遮蔽而被形成有複數之金屬膜的情形。在半導體裝置之特性檢查等之中，係會有複數之金屬膜之中之外側的金屬膜被削去並導致內側之金屬膜露出的情形。
本實施形態，係提供一種難以被造成損傷且遮蔽性為佳之半導體裝置及半導體裝置之製造方法。
由本實施形態所致之半導體裝置，係具備有基板、和被設置於基板處之半導體晶片、和被覆半導體晶片之樹脂、以及被設置於樹脂處之金屬膜。金屬膜，係具備有第1金屬層、和被設置於第1金屬層處之第2金屬層、以及被設置於第2金屬層處之第3金屬層。第1金屬層與第2金屬層，係包含相同之材料。第2金屬層之粒徑係較第1金屬層之粒徑而更小、或/及第2金屬層之電阻率係較第1金屬層之電阻率而更大。
其中一個實施形態，係能夠提供一種難以被造成損傷且遮蔽性為佳之半導體裝置及半導體裝置之製造方法。
以下，參照圖面，對本發明之實施形態作說明。本實施形態，係並非為對於本發明作限定者。在以下之實施形態中，上下方向，係代表當在配線基板中而將搭載半導體晶片之面設為上的情況時之相對方向，而會有與依循於重力加速度之上下方向相異的情形。圖面係為作示意性或概念性展示者，各部分之比例等係並非絕對會與現實之物相同。在說明書與圖面中，關於與前面已揭示之圖面所敘述過的要素相同之要素，係附加相同的元件符號，並省略詳細說明。在對於金屬層之剖面而藉由X光、光學顯微鏡等而進行攝影，並求取出了在剖面處所出現的結晶粒之剖面積時，係亦可將該剖面積假定為圓的面積，並將該圓之直徑作為結晶粒之粒徑。在此，當在剖面處係存在有複數之結晶粒時，係亦可將測定範圍之所有結晶粒之平均值作為粒徑。
(第1實施形態) 第1圖，係為對於由第1實施形態所致之半導體裝置之構成之其中一例作展示之上面圖。第2圖，係為第1圖中之II-II線處的剖面圖。
半導體裝置1，係具備有配線基板10、和半導體晶片50、52、和接合打線30、和樹脂層70、以及金屬膜90。配線基板10，係具有第1面10A、和相對於第1面10A而位於相反側處之第2面10B、以及位於第1面10A與第2面10B之間之側面10C。在配線基板10之內部，係被設置有配線層13～16(參照第3圖)以及將配線層間作絕緣的層間絕緣膜17(參照第3圖)。層間絕緣膜17，係可為玻璃環氧樹脂或陶瓷等。配線基板10，例如，係可為使用有玻璃環氧樹脂之印刷基板或中介板(interposer)等。配線基板10，係具有被與其之內部配線之其中一者作電性連接的墊片12。配線基板10之墊片12以外的第1面10A，係亦可藉由未圖示之阻焊劑等的絕緣膜而被作被覆。墊片12，係包含鋁、金、銅或此些之複合材料。
半導體晶片50，係被設置在配線基板10之第1面10A上。半導體晶片50，係藉由接著層40而被接著於配線基板10之第1面10A上。半導體晶片52，係藉由接著層40而被接著於半導體晶片50上。接著層40，例如，係可為如同NCP(非導電糊，Non Conductive Paste)、DAF(晶圓黏結薄膜，Die Attach Film)一般之糊狀或薄膜狀的樹脂。另外，被作層積之半導體晶片之數量，係亦可為較2而更多。亦可並不作層積，而僅具有半導體晶片50。另外，係亦可被層積有對於半導體晶片50、52作控制之控制器晶片。控制器晶片，係亦可在第1面10A上而被另外作設置。
半導體晶片50，係具有被與被形成於其之表面上的半導體元件之其中一者作電性連接的墊片54。半導體晶片52，係具有被與被形成於其之表面上的半導體元件之其中一者作電性連接的墊片56。墊片54、56，係包含鋁、金、銅或此些之複合材料。
接合打線30，係將墊片12與54之間作連接。接合打線30，係將墊片54與56之間作連接。接合打線30，例如係身為包含有Au線、Cu線、Ag線、作了Pd塗敷之Cu線等的金屬線。
樹脂層70，係在配線基板10上而將半導體晶片50、52以及接合打線30密封並作保護。又，樹脂層70，在配線基板10之側面10C處係亦可並未被作設置。樹脂層70，係身為熱硬化樹脂，例如，係可為環氧樹脂或丙烯酸樹脂。樹脂層70，係可為含有未圖示之無機填充物的樹脂材料。無機填充物，例如，係為二氧化矽，亦即是氧化矽。無機填充物，係除了二氧化矽以外，例如亦可添加氫氧化鋁、碳酸鈣、氧化鋁、氮化硼、氧化鈦、鈦酸鋇等。
金屬膜90，係將樹脂層70之表面以及側面作被覆。金屬膜90，係一直被覆至配線基板10之側面10C處，並在側面10C處被與配線基板10之配線之一部分作電性連接。
第3圖，係為對於第2圖之框III之構成作更詳細的展示之剖面圖。配線基板10，係作為配線層之一部分，而包含有配線層13～16。配線層16，係被設置在第2面10B側處。在配線層16之上方，係被設置有配線層15。在配線層15之上方，係被設置有配線層13、14。配線基板10，係亦可更進而包含有其他之配線層。在配線層13～16之間，係被設置有層間絕緣膜17。另外，配線層13，係亦可被與墊片12作連接，或者是作為墊片12而起作用。配線層16，亦同樣的，係可在第2面10B側處作為墊片而起作用，進而，亦可在配線層16處設置Cu柱等並與未圖示之外部端子作連接。
在配線基板10之側面10C處，一部分的配線層14、15係從層間絕緣膜17而有所露出。從層間絕緣膜17而露出的配線層14、15，例如，係被與特定電壓(例如，接地電壓)作連接。金屬膜90，係將配線基板10之側面10C作被覆，並被與配線層14、15作電性連接。故而，金屬膜90，係經由配線層14、15而被作接地。藉由此，金屬膜90，係能夠發揮作為電磁遮蔽之功用。
第4圖，係為對於第2圖之框IV之構成作更詳細的展示之剖面圖。另外，在第4圖中，係僅對於半導體裝置1之上部作展示。被被覆於樹脂層70之表面以及側面處的金屬膜90，係包含有金屬層91、金屬層92、金屬層93、金屬層94之層積膜。
金屬層91，係被覆樹脂層70之表面、側面以及配線基板10之側面10C。在金屬層91處，例如係使用有包含有不鏽鋼、鎳或鈦之金屬材料。金屬層91之膜厚，例如係為約100nm～300nm。
金屬層92，係被設置在金屬層91上，並隔著金屬層91而被覆樹脂層70之表面、側面以及配線基板10之側面10C。金屬層92，係身為與金屬層91以及金屬層94相異之材料，並且相較於金屬層91、金屬層93以及金屬層94而更為低電阻。在金屬層92處，例如係使用有銅或包含有銅之化合物等的金屬材料。金屬層92之膜厚，例如，係為約1.5μm～2.5μm。其之平均粒徑，係為約0.15μm～0.5 μm。金屬層92，其之電阻率係為未滿2.0μΩ･cm。
金屬層93，係被設置在金屬層92上，並隔著金屬層91、金屬層92而被覆樹脂層70之表面、側面以及配線基板10之側面10C。金屬層93，例如係使用有銅或包含有銅之化合物等的金屬材料，而為與構成金屬層92之材料相同。如同第5圖中所示一般，金屬層93之粒徑係較金屬層92之粒徑而更小。金屬層93之膜厚，例如，係為約0.3μm～1.5μm。其之平均粒徑，係為未滿0.15μm。金屬層93，其之電阻率係為2.0μΩ･cm以上。另外，金屬層92、93之總膜厚，例如，係為1.7μm～4.0μm。更理想，係為1.7μm～3.0μm。
金屬層94，係被設置在金屬層93上，並隔著金屬層91、金屬層92、金屬層93而被覆樹脂層70之表面、側面以及配線基板10之側面10C。金屬層94，係將金屬層93上作被覆，而成為半導體裝置1之最外層。在金屬層94處，例如係使用有包含有不鏽鋼、鎳或鈦之金屬材料。金屬層94，係可為與金屬層91相同之材料。金屬層94之膜厚，例如，係為約300nm～900nm。
(效果) 在第6A圖中，對於金屬層93之粒徑之大小和與金屬層94之間之密著力的說明圖作展示。第6A圖之縱軸，係針對「若是施加何種程度之力則金屬層93會從金屬層94而露出」一事作展示。橫軸，係對於金屬層93之粒徑作展示。根據第6A圖，例如當用以使其成為不會剝離之力的規格值係為CmN的情況時，在粒徑為小之A的情況時，雖然會滿足規格，但是，在粒徑為大之B的情況時，係成為無法滿足規格。根據此，藉由將金屬層93之粒徑縮小，金屬層93與金屬層94之間之密著性係提升，金屬層94係成為難以從金屬層93而剝落。亦即是，金屬層94係能夠更為確實地保護金屬層93。
在第6B圖中，針對金屬層93之電阻值與粒徑之依存性作展示。在第6B圖之線B處，於粒徑為大之B的情況時，若是身為相同之膜厚，則係能夠將電阻率降低，而能夠得到充分的電磁遮蔽效果。另一方面，在第6B圖之線A處，於粒徑為小之A的情況時，電阻率係會變高。於此情況，係無法得到充分的電磁遮蔽效果。例如，在電阻率之規格值為CmΩ/Sq的情況時，於粒徑為大的情況時，係僅需要為X1μm即可，但是，在粒徑為小的情況時，係需要為較X1μm而更大之X2μm。故而，若是想要並不包夾著金屬層92地而僅藉由金屬層91、金屬層93、金屬層94來形成金屬膜90並滿足密著力和電阻率，則係需要將金屬層93之膜厚設為相當厚。然而，若是將金屬層93之膜厚設為相當厚，則由於在成膜中係會耗費時間，因此成本係會變高。
(a)因此，係在金屬層91與金屬層93之間包夾有粒徑為大之金屬層92。金屬層92，係就算是膜厚為薄也能夠將電阻率降低。因此，相較於將金屬層93設為相當厚的情況，係能夠以更低的成本而得到充分的密著力和電磁遮蔽效果。 (b)又，藉由在金屬層92與金屬層93處使用相同之材料，係能夠相較於使用相異種類之材料的情況時而將金屬層92與金屬層93之間之密著力設為更強。
(第1實施形態之半導體裝置之製造方法) 接著，針對由第1實施形態所致之半導體封裝1的製造方法作說明。第7圖以及第8圖，係為對於由第1實施形態所致之半導體封裝的製造方法之其中一例作展示之流程圖。
針對在進行第7圖之步驟1之前的半導體裝置之製造方法作說明。在配線基板10之第1面10A上，隔著接著層40而設置半導體晶片50。在半導體晶片50上，隔著接著層40而設置半導體晶片52。此時，複數之配線基板10，係身為仍有被作連結之狀態，而並未被個片化為各半導體封裝。
接著，在對於配線基板10進行電漿洗淨之後，將配線基板10之墊片12、半導體晶片50之墊片54以及半導體晶片52之墊片56藉由接合打線30來作連接。
另外，半導體晶片50、52，係相對於第1面10A而於略垂直方向上被作層積，但是，半導體晶片，係亦可在第1面10A上橫向並排配置。
接著，在步驟S1處，在配線基板10上設置樹脂層70，而將半導體晶片50、52、接合打線30作密封。
在步驟S2處，使用切刃來將配線基板10個片化為各半導體裝置單位，而形成半導體裝置1。
在步驟S3處，對於被作了個片化後的半導體裝置1之樹脂層70之上面進行標記(marking)。標記，係使用雷射刻印機來將製品名稱和製造者、批次編號等作刻印(engraving)。
在步驟S4處，半導體裝置1係被送入烤箱並進行烘烤處理。烘烤處理，例如，係以100度～260度之間之溫度而被進行處理。藉由烘烤處理，來使在樹脂層70中所包含之水分蒸發，而能夠使其之與後述之金屬膜90的密著性提升。又，藉由進行焊錫之熔點溫度以下，例如260度以下之烘烤處理，係能夠對於接合部分、配線、電晶體等之信賴性的劣化作抑制。進而，係亦可藉由設為真空，來使樹脂層70與配線基板10所含有的氣體被放出。
在步驟S5處，將複數之半導體裝置1，積載於未圖示之金屬或耐熱塑膠等的對於200℃以上之溫度具有耐性的托盤上。
在步驟S6處，複數之半導體裝置1，係在被載置於托盤上的狀態下，被搬入至壓力為較大氣壓力而更低的減壓腔室中。
在步驟S7處，半導體裝置1，係被搬送至蝕刻腔室處，樹脂層70係在蝕刻腔室中被進行蝕刻。樹脂層70，例如，係使用包含有氬(Ar)與氮(N)之電漿而被作蝕刻(濺鍍蝕刻)。氬與氮之流量之比，例如係可設為3：7~7：3。若是落於此範圍之外，則會有使樹脂層70與金屬膜90之間之密著性降低的情況。藉由此蝕刻，相對於無機填充物，樹脂層70係被選擇性地作1~100nm程度之蝕刻。由於無機填充物與金屬膜90之間之密著性係為高，因此，藉由使無機填充物露出，樹脂層70與金屬膜90之間之密著性係提升。
在步驟S8處，半導體裝置1係被導入至成膜腔室中，金屬膜90係被形成於樹脂層70之上面以及側面和半導體裝置1之側面10C處。金屬膜90，例如，係使用濺鍍法，而在將複數之半導體裝置1載置於托盤上的狀態下被形成。在此，蝕刻腔室與成膜腔室係亦可為同一腔室。
如同上述一般，金屬膜90，係身為金屬層91～94之層積膜。金屬層91～94，係在同一之減壓腔室內，一面變更濺鍍之材料來源一面連續地進行成膜。如同第5圖中所示一般，首先，在樹脂層70上成膜金屬層91(S81)。例如，在作為金屬層91而使用有不鏽鋼的情況時，係使用不鏽鋼之來源而藉由濺鍍來進行成膜。不鏽鋼膜之膜厚，例如係為100nm～300nm。
接著，以約200℃來在金屬層91上成膜金屬層92(S82)。此時，係亦可藉由加熱器等來加熱托盤及半導體裝置1。作為金屬層92，係使用銅或包含有銅之合金作為來源，而藉由濺鍍來進行成膜。成膜時之半導體裝置1之溫度，係為約200℃。如同第6B圖中所示一般，金屬層92之粒徑，係成為較以150℃而被成膜的銅之粒徑而更大，金屬層92係相對性而言成為較低電阻。金屬層92之膜厚，例如，係為約1.5μm～2.5μm。其之平均粒徑，係為約0.20μm～0.5μm。
接著，以約150℃來在金屬層92上成膜金屬層93(S83)。此時，係亦可將加熱器等之加熱停止，並等待半導體裝置1之溫度下降。作為金屬層93，係使用與金屬層92相同之材料作為來源，而藉由濺鍍來進行成膜。此時，如同第6A圖中所示一般，金屬層93之銅合金之粒徑係相對性而言成為較小。如同第6B圖中所示一般，金屬層93，係成為較金屬層92而更為高電阻。金屬層93之膜厚，例如，係為約0.3μm～1.5μm。其之平均粒徑，係為0.15μm以下。
接著，在金屬層93上成膜金屬層94(S84)。例如，在作為金屬層94而使用有不鏽鋼的情況時，係使用不鏽鋼之來源而藉由濺鍍來進行成膜。不鏽鋼膜之膜厚，例如係為300nm～900nm。此時，依循於基底之金屬層93，金屬層94亦成為較為平坦且粒徑為小之膜。另外，金屬層91、金屬層93、金屬層94之成膜時之溫度，係亦可為略相同。
另外，金屬層91～94，係亦可藉由CVD(化學氣相沈積，Chemical Vapor Deposition)法、真空蒸鍍法、離子噴濺法來形成。
藉由以上之製造方法，而完成半導體裝置1。 (效果) (a)假設在將半導體裝置1載置於對於150℃以上之溫度並不具有耐性的例如樹脂帶上並進行濺鍍的情況時，當然，係需要以未滿150℃之溫度來成膜金屬膜92、93。故而，金屬膜92、93之粒徑係變小，電阻值係會變得較高。相對於此，在本實施形態中，係將配線基板10搭載在相較於樹脂帶而對於高溫更加具有耐性的托盤上，並進行濺鍍處理。故而，係能夠將金屬層92以身為150℃以上之溫度的200℃來進行成膜，而能夠將其之粒徑增大。其結果，金屬層92，相對而言係成為較低電阻。如此這般，藉由將金屬層92以約200℃之高溫來進行成膜，並將金屬層93以150℃之低溫來進行成膜，係將雖然為低電阻但是與金屬層94之間之密著力為低的金屬層92與雖然為高電阻但是與金屬層94之間之密著力為高的金屬層93作組合，而能夠同時發揮電磁遮蔽性與密著力。 (b)由於金屬層92與金屬層93係身為相同之材料，因此，係能夠使用同一來源來進行成膜，故而，係能夠將成本降低。 (c)由於係將金屬層92與金屬層93在同一之腔室中進行成膜，因此，係能夠減少成膜腔室之數量，故而，係能夠將成本降低。
(其他製造方法) 第9圖，係為半導體裝置1之其他製造方法。金屬膜90，係身為金屬層91～94之層積膜。另外，金屬層91～94之膜厚、成膜方法、成膜溫度等，係設為與在第1實施形態中之半導體裝置1之製造方法略相同。金屬層91～94，係在相異之減壓腔室內進行成膜。
在樹脂層70上成膜金屬層91(S181)。
將半導體裝置1從進行了金屬層91之成膜的成膜裝置搬出(S182)。
將半導體裝置1搬入至與第1腔室相異之高溫用成膜裝置中(S183)。
高溫成膜裝置之平台等，係已被進行預熱而成為目標之成膜溫度。因此，被搬入至高溫成膜裝置中之半導體裝置1，其之直到溫度上升為止所需的待機時間係為少，金屬層92係被成膜(S184)。
將半導體裝置1從高溫成膜裝置搬出(S185)。
將半導體裝置1搬入至成膜裝置中(S186)。此時，成膜裝置係亦可身為進行了其他之金屬層91之成膜之裝置，亦可為作為與第1腔室、第2腔室均相異之「第3腔室」的成膜裝置。
成膜裝置之平台等，係已成為目標之成膜溫度。因此，被搬入至成膜裝置中之半導體裝置1，其之直到溫度下降為止所需的待機時間係為少，金屬層93係被成膜(S187)。
在成膜金屬層93後，成膜金屬層94(S188)。
藉由以上之製造方法，而以其他之製造方法來完成半導體裝置1。
(效果) (d)金屬層92與金屬層93，係在相異之腔室內進行成膜。故而，腔室之升溫、降溫的待機時間係變少。因此，除了第1實施形態之半導體裝置的製造方法之(a)、(b)之效果之外，係更進而能夠以更少的時間來對於半導體裝置1進行處理。
(其他實施形態) (a)在上述實施形態中，於金屬層92與金屬層93之成膜中係使用有同一之來源。但是，係亦可僅在金屬層92處使用純度為4N(99.99%)以上之金屬銅之來源，並在金屬層93處使用純度為較4N而更低之銅之來源。藉由此，由於金屬層92之純度亦成為99.99%以上，因此係能夠成為更加低電阻。進而，在設為低電阻之必要性為低的金屬層93處，係亦可使用純度為低之來源，而將成本降低。例如，在藉由濺鍍來進行成膜時，在金屬層92處，係使用4N以上之銅之濺鍍靶材。在金屬層93處，係使用4N以下之銅之濺鍍靶材。又，此時，就算是金屬層93之銅之純度變得些許低，亦由於主要的構成材料係為銅，因此係能夠維持金屬層92與金屬層93之間之密著力。 (b)在上述實施形態中，金屬層93之成膜溫度雖係為150℃，但是，係亦可為150℃以下，較理想，係為120℃以下，更理想，係為100℃以下。於此情況，由於係能夠更進而縮小第3金屬層93之粒徑，因此，與第4金屬層之間之密著力係提升。 (c)在上述實施形態中，金屬層92之成膜溫度雖係為200℃，但是，只要是身為較150℃而更高之溫度，則就算是為200℃以下，亦能夠得到將粒徑增大之效果。成膜溫度，係亦可為200℃以上，較理想，係為200℃～230℃，更理想，係為230℃～250℃。於此情況，由於係能夠更進而增大金屬層92之粒徑，因此，係能夠將金屬層92之電阻率縮小。 (d)如同第10圖中所示一般，在金屬層91與金屬層92之間，係亦可更進而設置包含有與金屬層92相同之材料並且粒徑為較金屬層92而更小之金屬層95。金屬層95之膜厚，係亦可為較金屬層93而更薄。金屬層91與金屬層95之間之密著力係被強化。進而，由於金屬層92與金屬層95係包含相同之材料，因此，係亦能夠將金屬層92與金屬層95之間之密著性增強。此時，金屬層95，係亦能夠與金屬層93相同地而以150℃以下來進行成膜。 (e)在上述實施形態中，成膜溫度，係身為成膜裝置之平台等之設定溫度。但是，係亦可在半導體裝置處例如安裝溫度感測器等並一面進行成膜一面對於溫度作測定，而將此時之半導體裝置之實際測定到的溫度作為成膜溫度。
雖然是針對本發明之數種實施形態作了說明，但是，該些實施形態，係僅作為例子所提示者，而並非為對於發明之範圍作限定者。此些之實施形態，係可藉由其他之各種形態來實施，在不脫離發明之要旨的範圍內，係可進行各種之省略、置換、變更。此些之實施形態及其變形，係被包含於發明之範圍以及要旨內，並且亦被包含於申請專利範圍中所記載之發明及其均等範圍內。
1:半導體裝置 10:配線基板 50:半導體晶片
52:半導體晶片
30:接合打線
70:樹脂層
90:金屬膜
10A:第1面
10B:第2面
10C:側面
13:配線層
14:配線層
15:配線層
16:配線層
17:層間絕緣膜
12:墊片
40:接著層
54:墊片
56:墊片
91:金屬層
92:金屬層
93:金屬層
94:金屬層
95:金屬層
[第1圖]係為第1實施形態之半導體裝置之示意性上面圖。 [第2圖]係為第1實施形態之半導體裝置之示意性剖面圖。 [第3圖]係為第1實施形態之半導體裝置之部分擴大剖面圖。 [第4圖]係為第1實施形態之半導體裝置之部分擴大剖面圖。 [第5圖]係為第1實施形態之半導體裝置之部分擴大剖面圖。 [第6A圖]係為第1實施形態之半導體裝置之特性圖。 [第6B圖]係為第1實施形態之半導體裝置之特性圖。 [第7圖]係為第1實施形態之半導體裝置之製造方法之流程圖。 [第8圖]係為第1實施形態之半導體裝置之製造方法之流程圖。 [第9圖]係為第1實施形態之半導體裝置之其他的製造方法之流程圖。 [第10圖]係為該其他實施形態之半導體裝置之部分擴大剖面圖。
70:樹脂層
91:金屬層
92:金屬層
93:金屬層
94:金屬層

Claims (13)

  1. 一種半導體裝置，係具備有：基板；和半導體晶片，係被設置於前述基板處；和樹脂層，係被覆前述半導體晶片；和金屬膜，係被設置於前述樹脂處，前述金屬膜，係具有被設置於前述樹脂層處之第1金屬層、被設置於前述第1金屬層處之第2金屬層、以及被設置於前述第2金屬層處之第3金屬層，前述第1金屬層與前述第2金屬層係為相同之金屬材料，前述第2金屬層之平均粒徑係較前述第1金屬層之平均粒徑而更小，前述第2金屬層之電阻率係較前述第1金屬層之電阻率而更大，前述第1金屬層之平均粒徑係較0.20μm而更大並較0.5μm而更小，前述第2金屬層之平均粒徑係較0.15μm而更小。
  2. 如請求項1所記載之半導體裝置，其中，前述金屬膜，係在前述第1金屬層與前述樹脂層之間，具有：第4金屬層，係包含與前述第1金屬層相同之材料，並且平均粒徑為較前述第1金屬層而更小。
  3. 如請求項1或2所記載之半導體裝置，其中，前述第1金屬層與前述第2金屬層係包含有銅。
  4. 如請求項1或2所記載之半導體裝置，其中，前述第1金屬層之電阻率，係為未滿2.0μΩ．cm。
  5. 如請求項1或2所記載之半導體裝置，其中，前述第1金屬層之膜厚係為1.5μm~2.5μm，前述第2金屬層之膜厚係為0.3μm~1.5μm。
  6. 如請求項1或2所記載之半導體裝置，其中，前述第1金屬層係包含純度99.99%以上之銅，前述第2金屬層係包含純度為未滿99.99%之銅。
  7. 一種半導體裝置之製造方法，係包含有下述之步驟：在基板處設置半導體晶片；設置覆蓋前述半導體晶片之樹脂層；在前述樹脂層處以200℃以上而設置第1金屬層；在前述第1金屬層處以150℃以下而設置與前述第1金屬層相同之金屬材料之第2金屬層；在前述第2金屬層處設置第3金屬層，其中，前述第2金屬層之平均粒徑係較前述第1金屬層之平均粒徑而更小，前述第2金屬層之電阻率係較前述第1金屬層之電阻率而更大，前述第1金屬層之平均粒徑係較0.20μm而更大並較0.5μm而更小，前述第2金屬層之平均粒徑係較0.15μm而更 小。
  8. 如請求項7所記載之半導體裝置之製造方法，其中，係包含有在前述樹脂層與第1金屬層之間以150℃以下而設置第4金屬層之步驟。
  9. 如請求項7所記載之半導體裝置之製造方法，其中，係在相異之腔室中而設置前述第1金屬層與前述第2金屬層。
  10. 如請求項7所記載之半導體裝置之製造方法，其中，前述第1金屬層與前述第2金屬層係包含有銅。
  11. 如請求項7~10中之任一項所記載之半導體裝置之製造方法，其中，前述第1金屬層與前述第2金屬層以及前述第3金屬層，係藉由濺鍍而被形成。
  12. 如請求項7~10中之任一項所記載之半導體裝置之製造方法，其中，在前述第1金屬層之成膜中，係使用純度99.99%以上之銅，在前述第2金屬層中，係使用純度為未滿99.99%之銅。
  13. 如請求項7所記載之半導體裝置之製造方法，其中，前述第1金屬層之膜厚係為1.5μm~2.5μm，前述第2金 屬層之膜厚係為0.3μm~1.5μm。
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